CN108198815A - Semiconductor devices and its manufacturing method and the electronic equipment including the device - Google Patents
Semiconductor devices and its manufacturing method and the electronic equipment including the device Download PDFInfo
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- CN108198815A CN108198815A CN201711452736.2A CN201711452736A CN108198815A CN 108198815 A CN108198815 A CN 108198815A CN 201711452736 A CN201711452736 A CN 201711452736A CN 108198815 A CN108198815 A CN 108198815A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 138
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000002184 metal Substances 0.000 claims description 97
- 229910052751 metal Inorganic materials 0.000 claims description 97
- 239000004020 conductor Substances 0.000 claims description 75
- 239000000463 material Substances 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 26
- 239000002019 doping agent Substances 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 18
- 150000001875 compounds Chemical class 0.000 claims description 17
- 238000000926 separation method Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910052707 ruthenium Inorganic materials 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims 8
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 347
- 229920002120 photoresistant polymer Polymers 0.000 description 35
- 238000001020 plasma etching Methods 0.000 description 18
- 238000005530 etching Methods 0.000 description 15
- 239000013078 crystal Substances 0.000 description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 13
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005192 partition Methods 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 239000013598 vector Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Disclose a kind of semiconductor devices and its manufacturing method and the electronic equipment including the device.According to embodiment, semiconductor devices includes：Substrate；The vertical active area formed on substrate, including the first source/drain region, channel region and the second source/drain region vertically set gradually；The grid formed around the periphery of channel region stack；To the first contact site of the second source/drain region above second source/drain region, wherein, the first contact site periphery and the second source/drain region periphery substantial registration.
Description
Technical field
This disclosure relates to semiconductor applications, and in particular, to vertical-type semiconductor devices and its manufacturing method and including
The electronic equipment of this semiconductor devices..
Background technology
In horizontal type device such as mos field effect transistor (MOSFET), source electrode, grid and drain electrode
Along the direction arrangement for being roughly parallel to substrate surface.Due to this arrangement, the area shared by horizontal type device is reduced, it is general to require
Area shared by source electrode, drain and gate reduces, and device performance is made to be deteriorated (for example, power consumption and resistance increase), therefore horizontal type device
The area of part is not easy to further reduce.Unlike this, in vertical-type device, source electrode, grid and drain electrode edge are approximately perpendicular to lining
The direction arrangement of bottom surface.Accordingly, with respect to horizontal type device, the area shared by vertical-type device is easier to reduce.
Invention content
In view of this, the purpose of the disclosure is to provide a kind of vertical-type semiconductor for having and improving performance at least partly
Device and its manufacturing method and the electronic equipment for including this semiconductor devices.
According to one aspect of the disclosure, a kind of semiconductor devices is provided to include：Substrate；What is formed on substrate is vertical
Active area, including the first source/drain region, channel region and the second source/drain region vertically set gradually；Around the periphery of channel region
The grid of formation stack；To the first contact site of the second source/drain region above second source/drain region, wherein, the first contact site periphery and the
Two source/drain region periphery substantial registrations.
According to one aspect of the disclosure, a kind of semiconductor devices is provided, including：Substrate；It is formed on substrate
Vertical active area, including the first source/drain region, channel region and the second source/drain region vertically set gradually；Around channel region
The grid that periphery is formed stack；The divider wall of side wall formation above grid stacking and in active area；Grid stacking above and every
From the autoregistration metal contact portion formed on wall side wall.
According to another aspect of the present disclosure, a kind of method for manufacturing semiconductor devices is provided, including：It sets on substrate
Active area materials layer；Hard mask layer is set on active area materials layer, and hard mask layer is included for limit active area first
Point；Using hard mask layer as mask, active area materials layer is patterned, so as to limit vertical active area；Forming layer on substrate
Between dielectric layer, and planarization process is carried out to it, to expose hard mask layer；Selective etch hard mask layer is covered firmly with removal
Mold layer, so as to be left in interlevel dielectric layer and corresponding first slot of vertical active area；Conduction material is filled in the first slot
Material, to form the first contact site.
According to another aspect of the present disclosure, a kind of electronic equipment is provided, including the collection formed by above-mentioned semiconductor device
Into circuit.
In accordance with an embodiment of the present disclosure, the first contact site periphery and the second source/drain region periphery substantial registration, so as to increase
The integration density of device and reduce masks, so as to reducing manufacture cost, further, since forming self-aligned contacts portion
With contact cylinder, increase integration density and reduce the difficulty to form contact site.It is possible thereby to it is formed with high-aspect-ratio
Metal contacts (avoid and for example etch contact hole using plasma etching method and refilled with the material of such as metal etc
The technology difficulty of contact hole), and the risk of photoetching misalignment is reduced due to reducing lithography step, so as to further increase
Integration density is added.Further, since manufacture cost is not reduced using double compositions.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 to 14 shows the schematic diagram of the flow of the manufacture semiconductor devices according to the embodiment of the present disclosure；
Figure 15 to 21 shows the schematic diagram of the flow of the manufacture semiconductor devices according to another embodiment of the disclosure；
Figure 22 to 29 shows the schematic diagram of the flow of the manufacture semiconductor devices according to the another embodiment of the disclosure.
Through attached drawing, the same or similar reference numeral represents the same or similar component.
Specific embodiment
Hereinafter, it will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, the description to known features and technology is omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structure diagrams according to the embodiment of the present disclosure are shown in the drawings.It is drawn to scale that these figures, which are not,
, wherein for the purpose of clear expression, certain details are exaggerated, and certain details may be omitted.Shown in figure
Various regions, the shape of layer and relative size between them, position relationship are only exemplary, in practice may be due to system
It makes tolerance or technology restriction and is deviated, and in addition those skilled in the art can be designed according to actually required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when by one layer/element be referred to as be located at another layer/element " on " when, which can
There may be intermediate layer/element on another layer/element or between them.If in addition, in a kind of direction
In one layer/element be located at another layer/element " on ", then when turn towards when, which can be located at another layer/member
Part " under ".
The first source/drain being sequentially stacked on substrate can be included according to the vertical-type semiconductor devices of the embodiment of the present disclosure
Layer, channel layer and the second source drain.Can be adjacent to each other between each layer, it is certainly intermediate to be also likely to be present other semiconductor layers, example
Such as leak inhibition layer and/or ON state current enhancement layer (band gap semiconductor layer bigger than adjacent layer or small).In the first source drain and
The source/drain region of device can be formed in second source drain, and the channel region of device can be formed in channel layer.According to this public affairs
The embodiment opened, this semiconductor devices can be conventional field-effect transistor (FET).In the case of fets, the first source/drain
Layer and the second source drain (in other words, the source/drain regions of channel layer both sides) can have identical conduction type (for example, N-shaped or p
Type) doping.Office can form conductive channel between the source/drain region at channel region both ends by channel region.Alternatively, this half
Conductor device can be tunnelling FET.In the case of tunnelling FET, the first source drain and the second source drain (in other words, raceway groove
The source/drain region of layer both sides) there can be the doping of different conduction-types (for example, respectively N-shaped and p-type).In this case, band
Charged particle such as electronics can be tunneled through channel region from source region and enter drain region, so as to make that guiding path is formed between source region and drain region
Diameter.Although routine FET and conduction mechanism in tunnelling FET simultaneously differ, they show can by grid come voltage input/
Electric property whether conducting between drain region.Therefore, for conventional FET and with FET is worn, unification is with term " source drain (source/drain
Area) " and " channel layer (channel region) " describe, although in tunnelling FET and there is no " raceway grooves " on ordinary meaning.
Grid stacking can be formed around the periphery of channel layer.Then, grid length can be determined by the thickness of channel layer itself, and
It is not to be determined as in routine techniques dependent on etching is taken.Channel layer can for example be formed by epitaxial growth, from
And its thickness can control well.Therefore, can well control gate it is long.It the periphery of channel layer can be relative to first,
The periphery of two source drains inwardly concaves.In this way, the grid formed, which stack, can be embedded in channel layer relative to first, second source/drain
Layer it is recessed in.Preferably, grid be stacked on the first source drain, channel layer and the second source drain stacked direction (vertical direction,
Such as be approximately perpendicular to substrate surface) on range be in the female in this direction within the scope of.Thus it is possible to it reduces
Or even avoid being folded with source/drain region, help to reduce the parasitic capacitance between grid and source/drain.
Channel layer can be made of the single-crystal semiconductor material or SiGe (SiGe) of such as monocrystalline silicon, to improve device
Energy.Certainly, first, second source drain can also be made of single-crystal semiconductor material.In this case, the monocrystalline of channel layer half
Conductor material and the single-crystal semiconductor material of source drain can be eutectics.The electronics or sky of channel layer single-crystal semiconductor material
Cave mobility can be more than the electronics or hole mobility of first, second source drain.In addition, the taboo of first, second source drain
Bandwidth can be more than the energy gap of channel layer single-crystal semiconductor material.
In accordance with an embodiment of the present disclosure, channel layer single-crystal semiconductor material can have identical with first, second source drain
Crystal structure.In this case, lattice constant of first, second source drain in the case of no strain can be more than
Lattice constant of the channel layer single-crystal semiconductor material in the case of no strain.Then, channel layer single-crystal semiconductor material
Carrier mobility can be more than its carrier mobility or channel layer single-crystal semiconductor material in the case of no strain
The effective mass of carrier can be less than the effective mass of its carrier in the case of no strain or channel layer monocrystalline
The concentration of the lighter carrier of semi-conducting material can be more than the concentration of its lighter carrier in the case of no strain.It is standby
Selection of land, lattice constant of first, second source drain in the case of no strain can be less than channel layer single-crystal semiconductor material
Lattice constant in the case of no strain.Then, when 110 ＞ directions of the ＜ of channel layer single-crystal semiconductor material and source and drain it
Between current density vectors it is parallel when, the electron mobility of channel layer single-crystal semiconductor material is more than its situation in no strain
Under electron mobility or channel layer single-crystal semiconductor material electronics effective mass be less than its in the case of no strain
Electronics effective mass.
It in accordance with an embodiment of the present disclosure, can be partially into channel layer close to the first source/drain for the doping of source/drain region
The end of layer and the second source drain.It is formed and adulterated close to the end of the first source drain and the second source drain in channel layer as a result,
Distribution, resistance when this helps to reduce break-over of device between source/drain region and channel region, so as to promote device performance.
In accordance with an embodiment of the present disclosure, channel layer can include the semi-conducting material different from first, second source drain.
In this way, be conducive to handle channel layer such as selective etch, to be allowed to recessed relative to first, second source drain.Separately
Outside, the first source drain and the second source drain can include identical semi-conducting material.
For example, the first source drain can be Semiconductor substrate itself.In this case, channel layer can be on substrate
The semiconductor layer of epitaxial growth, the second source drain can be the semiconductor layers of the epitaxial growth on channel layer.Alternatively, first
Source drain can be the semiconductor layer being epitaxially grown on the substrate.In this case, channel layer can be in the first source drain
The semiconductor layer of upper epitaxial growth, the second source drain can be the semiconductor layers of the epitaxial growth on channel layer.
In accordance with an embodiment of the present disclosure, stress can also be set to serve as a contrast on the surface of the first source drain and the second source drain
Layer.For n-type device, stress liner can be with compression, to generate tensile stress in channel layer；For p-type device, stress lining
Layer can be with tensile stress, to generate compression in channel layer.Therefore, device performance can further be improved.
In accordance with an embodiment of the present disclosure, the periphery of the first contact site and the periphery of the second source/drain region are substantially coincident；Or
The semiconductor devices can also be included in the metal-semiconductor compounds layer formed on the surface of the second source/drain region, the first contact
The periphery in portion and the periphery of metal-semiconductor compounds layer formed on the surface of the second source/drain region are substantially coincident.
In accordance with an embodiment of the present disclosure, the first source/drain region includes that the horizontal stroke of the active region above it can be extended beyond
To extension, which further includes：To the second contact of the first source/drain region above the lateral extension portions of first source/drain region
Portion, the second contact site can include being sequentially stacked first part aligned with each other on substrate and in the vertical direction and second
Point, first part can include low-resistance semi-conducting material and/or metal-semiconductor compounds.Second of second contact site
The material identical with the first contact site can be included by dividing, and essentially identical with the thickness of the first contact site in the vertical direction, the
The first part of two contact sites can include semi-conducting material and/or metal-semiconductor compounds material.The of second contact site
Element in the semi-conducting material that a part includes at least partly in the first source/drain region or channel region or the second source/drain region
Part semiconductor element is identical.
In accordance with an embodiment of the present disclosure, the first contact site and/or the second contact site include Ni metal, Co, W, Ru and combinations thereof
Deng.
In accordance with an embodiment of the present disclosure, the second contact site can also include surrounding the gold of first part and second part periphery
Belong to layer, which can include Ni metal, the several combination of Co, W, Ru or wherein arbitrary.
In accordance with an embodiment of the present disclosure, which can also include to grid the third contact site of the grid conductor layer in stacking.
Wherein, third contact site and grid conductor layer can be integrated；Or third contact site includes the material identical with the first contact site
Material.
In accordance with an embodiment of the present disclosure, disclosed herein as well is a kind of semiconductor devices, including：Substrate；On substrate
The vertical active area formed, including the first source/drain region, channel region and the second source/drain region vertically set gradually；Around ditch
The grid that the periphery in road area is formed stack；The divider wall of side wall formation above grid stacking and in active area；Above grid stacking
And the autoregistration Metal contacts formed on divider wall side wall.
In accordance with an embodiment of the present disclosure, the device can also be included in formed above autoregistration Metal contacts with from right
The substantially self aligned third contact site of metalloid contact portion；Can also be included in grid stack top and divider wall side wall conformally
The diffusion impervious layer of formation；Side can include the metal contact layer being conformally formed on the diffusion barrier；In metal contact layer
Side wall can include the thin dielectric layer that is conformally formed.In addition, the device can also include by diffusion impervious layer and metal
The autoregistration metal contact portion that contact layer is formed；Formed in autoregistration metal contact portion with the basic autoregistration of autoregistration metal contact portion
Third contact site.Autoregistration metal contact portion and/or third contact site can include Ni metal, Co, W, Ru and combinations thereof etc..
This semiconductor devices can for example manufacture as follows.Specifically, the first source drain, ditch can be set on substrate
The lamination of channel layer and the second source drain.As set forth above, it is possible to it is set by substrate itself or by being epitaxially grown on the substrate
Put the first source drain.Then, can in the first source drain epitaxial growth channel layer, and can the epitaxial growth on channel layer
Second source drain.In epitaxial growth, the thickness of grown channel layer can be controlled.Due to respectively epitaxial growth, at least one
There can be clearly grain boundary between a little adjacent layers.In addition, each layer can adulterate respectively differently, therefore at least some phases
There can be doping concentration interface between adjacent bed.
For stacked the first source drain, channel layer and the second source drain, active area can be limited wherein.For example,
Can by they successively selective etch be required shape.In general, active area can be in the form of a column (for example, cylindric).In order to
It, can be just for the etching of the first source drain convenient for connecting the source/drain region formed in the first source drain in subsequent technique
The top of first source drain, so as to which the lower part of the first source drain can extend beyond the periphery of upper part.It is then possible to around ditch
The periphery of channel layer forms grid and stacks.
Furthermore it is possible to the periphery of channel layer is made to be inwardly concaved relative to the periphery of first, second source drain, to limit
Accommodate the space that grid stack.For example, this can be realized by selective etch.In this case, grid stacking can be embedded in this
In recessed.
Source/drain region can be formed in first, second source drain.For example, this can be by first, second source drain
It adulterates to realize.For example, ion implanting, plasma doping or the original when growing first, second source drain can be carried out
Position doping.According to an advantageous embodiment, can be formed in the periphery of channel layer relative to the periphery of first, second source drain
In recessed, sacrificial gate is formed, dopant active layer is then formed on the surface of first, second source drain, and for example, by annealing
The dopant in dopant active layer is made to enter in active area through first, second source drain.Sacrificial gate can prevent dopant active layer
In dopant be directly entered in channel layer.However, it is possible to there are element dopants via first, second source drain and enter ditch
Channel layer is close to the end of the first source drain and the second source drain.
The disclosure can be presented in a variety of manners, some of them example explained below.
Fig. 1 to 14 shows the flow chart of the manufacture semiconductor devices according to the embodiment of the present disclosure.
As shown in Figure 1, provide substrate 1001.The substrate 1001 can be various forms of substrates, including but not limited to body
Semiconductive material substrate such as body Si substrates, semiconductor-on-insulator (SOI) substrate, compound semiconductor substrate such as SiGe substrate
Deng.In the following description, for convenience of description, it is described by taking body Si substrates as an example.
On substrate 1001, channel layer 1003, another semiconductor layer 1005 can be sequentially formed for example, by epitaxial growth
With hard mask layer 1031.For example, channel layer 1003 can include the semi-conducting material different from substrate 1001, semiconductor layer 1005
Such as SiGe (atomic percent of Ge can be about 10-40%), thickness is about 10-100nm；Semiconductor layer 1005 can include with
The identical semi-conducting material such as Si of substrate 1001, thickness are about 20-50nm.Hard mask layer 1031 can include nitride as nitrogenized
Silicon, thickness are about 30-100nm.Certainly, the present disclosure is not limited thereto.For example, channel layer 1003 can include and substrate 1001 or half
The identical constituent component of conductor layer 1005, but semi-conducting material that constituent content is different (for example, be all SiGe, but wherein
The atomic percent of Ge is different), if substrate 1001 of the channel layer 1003 on and on semiconductor layer 1005
Has Etch selectivity.
Next, the active area of device can be limited.For example, this can be carried out as follows.Specifically, such as Fig. 2 (a) and 2 (b)
It, can be in Fig. 1 shown in (Fig. 2 (a) is sectional view, and Fig. 2 (b) is vertical view, and AA ' lines therein show the interception position in section)
Shown substrate 1001, channel layer 1003, semiconductor layer 1005 and hard mask layer 1031 lamination on form photoresist and (do not show
Go out), by photoetching (exposed and developed) by photoresist be patterned into two required shapes (it is in this example, generally circular, also may be used
Using other shapes, such as rectangle), and using the photoresist after composition as mask, successively to hard mask layer 1031, semiconductor layer
1005th, channel layer 1003 and substrate 1001 carry out selective etch such as reactive ion etching (RIE).Etching proceeds to substrate 1001
In, but do not proceed at the bottom surface of substrate 1001.Then, hard mask layer 1031, semiconductor layer 1005, channel layer after etching
1003 and substrate 1001 top formed two columns (in this example, cylindric).Accordingly, hard mask layer 1031,
Semiconductor layer 1005 and channel layer 1003 are respectively formed as two part the first hard mask layer 1031-1, the second hard mask layers
1031-2, the first semiconductor layer 1005-1, the second semiconductor layer 1005-2, the first channel layer 1003-1, the second channel layer 1003-
2.Due to active area materials layer be patterned at the bottom surface for proceeding to active area materials layer before stop, then active area materials layer
It is patterned to and the first hard mask layer 1031-1 is corresponding first stacks (i.e. on the left of cylinder) and with the as active area
Two hard mask layer 1031-2 corresponding second stack (i.e. right side cylinder), and the first stacking is stacked on bottom with second and is connected to
Together.RIE can for example be carried out by the direction for being approximately perpendicular to substrate surface, so as to which the first stacking and the second stacking are also substantially hung down
Directly in substrate surface.Later, photoresist can be removed.
The first separation layer such as shallow groove isolation layer can be formed around first stacks (active area) and second stacks
1033, it is electrically isolated with realizing.For example, as shown in Fig. 2 (a), it can be with patterned trench in structure, deposited oxide, and it is etched back
To the position of the upper surface of 1001 bottom of substrate, to form the first separation layer 1033.It, can be to the oxidation of deposit before eatch-back
Object carries out planarization process as chemically-mechanicapolish polished (CMP) or sputtering.Here, the top surface of the first separation layer 1033 can be close to ditch
Interface between channel layer 1003 and substrate 1001.
Then, as shown in figure 3, the periphery of the first channel layer 1003-1 can be made relative to 1001 and first semiconductor of substrate
The periphery of layer 1005-1 is recessed (in this example, recessed along the horizontal direction for being roughly parallel to substrate surface).For example, this can be with
By being realized relative to substrate 1001 and first semiconductor layer 1005-1, further selective etch channel layer 1003-1.Example
Such as, (Atomic Layer Etch) or digitlization etching (Digital Etch) can be etched using atomic layer to be selected
Property etching.For example, first for example, by being deposited on right side cylinder (by the second hard mask layer 1031-2, the second semiconductor layer 1005-
2nd, a part for the second channel layer 1003-2 and substrate 1001 is formed) one layer of nitrogen oxides of top covering, secondly for example it is heat-treated,
Make another part, the first hard mask layer 1031-1, the first channel layer 1003-1 and the first semiconductor layer 1005-1 of substrate 1001
Surface oxidation, and then remove their own surface oxide layer.It is SiGe and substrate 1001 in the first channel layer 1003-1
With the first semiconductor layer 1005-1 in the case of Si, the oxidation rate of SiGe is higher than the oxidation rate of Si, and the oxygen on SiGe
Compound is easier to remove.It is can be with repeated oxidation-removal oxide the step of, recessed needed for realization.Compared to selective quarter
Erosion, this mode can preferably control recessed degree.
In this way, just define active area (substrate 1001 especially upper part, the first ditch after etching of the semiconductor devices
Channel layer 1003-1 and the first semiconductor layer 1005-1, left side cylinder as shown in Figure 3).In this example, active area is substantially in column
Shape.In active area, the periphery substantial alignment of the top of substrate 1001 and the first semiconductor layer 1005-1, and the first channel layer
The periphery of 1003-1 is relatively recessed.The recessed top and bottom sidewall is respectively by the first channel layer 1003-1 and the first semiconductor layer
Interface definition between 1005-1 and the first channel layer 1003-1 and substrate 1001.
Certainly, the shape of active area is without being limited thereto, but can form other shapes according to layout is not counted.For example, bowing
In view, active area can oval, rectangular, rectangle etc..
The first channel layer 1003-1 relative to the top of substrate 1001 and the periphery of the first semiconductor layer 1005-1 shape
Into it is recessed in, will be subsequently formed grid stacking.For subsequent processing is avoided to impact channel layer 1003 or at this it is recessed
In leave unnecessary material so as to influence the formation of subsequent gate stacking, can be in one material layer of recessed middle filling to occupy grid
The space of stacking (therefore, which can be referred to as " sacrificial gate ").For example, this can be by forming sediment in structure shown in Fig. 3
Product nitrogen oxides, is then etched back such as RIE the oxynitride of deposit.Can be approximately perpendicular to the direction of substrate surface into
Row RIE removes extra nitrogen oxides, while technique is formed in the nitrogen oxides on the cylinder of right side before eliminating, and makes nitrogen oxygen
Compound can be only left in recessed, form sacrificial gate 1007, as shown in Figure 4.In this case, sacrificial gate 1007 can be filled out substantially
It is full above-mentioned recessed.
Next, source/drain region can be formed in 1001 and first semiconductor layer 1005-1 of substrate.This can be by lining
1001 and first semiconductor layer 1005-1 of bottom is doped to be formed.For example, this can be carried out as follows.
It specifically, as shown in figure 5, can be with formation dopant active layer 1009 in structure shown in Fig. 4.For example, dopant
Active layer 1009 can include oxide such as silica, wherein containing dopant.For n-type device, n-type dopant can be included；
For p-type device, p-type dopant can be included.Here, dopant active layer 1009 can be a film, so as to pass through example
As chemical vapor deposition (CVD) or atomic layer deposition (ALD) etc. are substantially conformally deposited on the surface of structure shown in Fig. 4.
Then, as shown in fig. 6, can be for example, by annealing, entering the dopant included in dopant active layer 1009 has
In source region and the left side cylinder stacked as second, so as to form doped region wherein, as shown in the dash area in figure.More
Specifically, one of source/drain region 1011-1 can be formed in substrate 1001, and is formed in the first semiconductor layer 1005-1 another
Source/drain region 1011-2.In addition, dopant is also into a part, the second channel layer 1003- for forming the second substrate 1001 stacked
2 and second in semiconductor layer 1005-2.And as can be seen from Figure 6, dopant active layer 1009 includes prolonging along the horizontal surface of substrate 1001
The part stretched, so as to which the doped region formed in substrate 1001 extends beyond the periphery of column.First as column stacks
It stacks with second and in bottom conductive is linked together by the horizontal continuation of the substrate 1001 adulterated, later, can be gone
Except dopant active layer 1009.
In addition, exist in spite of sacrificial gate 1007, but dopant can also be via 1001 and first semiconductor layer of substrate
1005-1 and enter in the first channel layer 1003-1, so as to forming certain mix at the upper and lower ends of the first channel layer 1003-1
Miscellaneous distribution, as shown in the dotted-line ellipse circle in figure.Resistance when this dopant profiles can reduce break-over of device between source-drain area,
So as to promote device performance.
In the above examples, by (drive in) dopant is driven in into active area from dopant active layer come formed source/
Drain region, but the present disclosure is not limited thereto.It for example, can be by ion implanting, plasma doping (for example, along structure in Fig. 4
Surface carry out conformal doping) etc. modes, to form source/drain region.Alternatively, in the processing described above in association with Fig. 1, Ke Yi
Well region is formed in substrate 1001, channel layer 1003 is then grown on, then the grown semiconductor layer on channel layer 1003
Doping in situ is carried out to it on 1005.When growing channel layer 1003, doping in situ can also be carried out to it, so as to adjusting means
Threshold voltage (Vt)。
In addition, in order to reduce contact resistance, source drain and second can also be stacked and carry out silicidation.Such as Fig. 7
(a) shown in, for example, layer of Ni Pt (or Co or Ti) is deposited, for example, Pt contents are about 2- in structure that can be shown in Fig. 6
10%, thickness is about 2-10nm, and is annealed at a temperature of about 200-900 DEG C, makes NiPt and Si (in source drain) or SiGe
(in 1003-2) reacts, so as to generate metal-semiconductor compounds such as SiNiPt or SiGeNiPt.Later, it can remove not
The remaining NiPt of reaction.
Significantly, since the second stacking (that is, right side cylinder) is not used as active area, and it is solely for conductive logical
Therefore road, in another embodiment, as shown in Fig. 7 (b), can make the NiPt being deposited in the second stacking (that is, right side cylinder)
It is fully reacted with Si and SiGe, in the case where right side cylinder is relatively thin, in a part for substrate and the second semiconductor layer 1005-2
Semi-conducting material such as doped silicon and the second channel layer 1006-2 in SiGe can be deposited on right side cylinder on NiPt (or
Person Co or Ti) fully to generate metal-semiconductor compounds completely, (it includes metal silicide and/or metal is silicide-germanide for reaction
Object), whole metal-semiconductor compounds are consequently formed.Later, unreacted residue NiPt can be removed.
The second separation layer can be formed above substrate and shallow groove isolation layer, specifically, as shown in figure 8, in substrate
1001 and the top deposited oxide of shallow groove isolation layer 1033, and channel layer 1003-1 and 1003-2 and substrate are etched back to it
The position at the interface (that is, interface between SiGe layer and Si layers) between 1001, to form the second separation layer 1013.In eatch-back
Before, planarization process can be carried out to the oxide of deposit as chemically-mechanicapolish polished (CMP) or sputtering.
It can be in recessed middle formation gate dielectric layer and grid conductor layer.Specifically, as shown in figure 9, knot that can be shown in Fig. 8
Sacrificial gate 1007 is removed on structure, deposits gate dielectric layer 1015 and grid conductor layer 1017, and the grid conductor layer to being deposited successively
1017 are etched back, and flush its top surface with hard mask layer 1031-1 and 1031-2.For example, gate dielectric layer 1015 can include
High-K gate dielectric such as HfO2；Grid conductor layer 1017 can include metal gate conductor.In addition, in gate dielectric layer 1015 and grid conductor layer
Between 1017, work function regulating course can also be formed, function regulating course can include threshold voltage vt and adjust metal.Forming grid
Before dielectric layer 1015, the boundary layer of such as oxide can also be formed.
In this way, gate dielectric layer 1015 and grid conductor layer 1017 can be embedded into it is recessed in, and gate dielectric layer 1015 and grid
The top surface of conductor layer 1017 is flushed with the top surface of hard mask layer 1031-1,1031-2.
Grid conductor layer will can be patterned, it, specifically, as shown in Figure 10, can be shown in Fig. 9 to form grid stacking
Structure on coat photoresist, photoresist is patterned to form photoresist layer 1039, is then mask with photoresist 1039,
Selective etch such as RIE is carried out to grid conductor layer 1017.In this way, grid conductor layer 1017 is in addition to staying part and light within recessed
Except the part that photoresist 1019 is blocked, the rest part of grid conductor layer 1017, which is etched to, to be not higher than and preferably shorter than channel layer
The top surface of 1003-1,1003-2.
Then, as shown in figure 11, remove photoresist layer 1039, coat photoresist again, and photoresist is patterned with
Photoresist layer 1019 is formed, is then mask with photoresist 1019, carries out selective quarter again to remaining grid conductor layer 1017
Erosion such as RIE.In this way, grid conductor layer 1017 in addition to stay part within recessed and part that photoresist 1039 blocks other than, grid
The rest part of conductor layer 1017 is all etched away.Grid conductor layer is formed only into as a result, stacks week as the first of active area
It encloses, and there is no grid conductor layer around being stacked second.It is stacked at this point, grid conductor layer 1017 and gate dielectric layer 1015 form grid.It should
Grid stacking may be used as gate contact.
It is then possible to as shown in figure 12, interlevel dielectric layer 1021 is formed in the structure shown in Figure 11.Specifically, example
Such as, it can be planarized with deposited oxide and to it and form interlevel dielectric layer 1021, interlevel dielectric layer 1021 such as CMP
It is flattened and is flushed with the top surface with hard mask layer 1031-1,1031-2.
Then, in fig. 13, can selectively etch hard mask layer 1031-1,1031-2, in interlevel dielectric layer
The first groove T1 and the second groove T2 are formed in 1021.Then, as shown in figure 14, contacting metal, and its can be deposited above
Planarized such as CMP to the top surface of interlevel dielectric layer 1021, thus formed in the first groove T1 and the second groove T2 from
The the first Metal contacts 1023-1 and the second Metal contacts 1023-2, the first Metal contacts 1023-1 and/or second of alignment
Metal contacts 1023-2 can include Ni metal, Co, W, Ru and combinations thereof etc..
As shown in figure 14, (it is by for the source/drain region above the first Metal contacts 1023-1 and the first channel layer 1003-1
Semi-conductor layer 1005-1 is formed) alignment, specifically, periphery and the first semiconductor layer of the first Metal contacts 1023-1
The periphery substantial registration of 1005-1, further, the periphery of the first Metal contacts 1023-1 and the first semiconductor layer 1005-
1 periphery is substantially coincident.Also, first Metal contacts 1023-1 may be used as the source/drain region, and (it is by the first semiconductor
Layer 1005-1 formed) contact site.It is right each other in the vertical direction that second Metal contacts 1023-2 is stacked with conductive second
Standard, and can be together as the source/drain region below the first channel layer 1003-1 (it is formed by a part for substrate 1001)
Contact site.As previously mentioned, conductive second stacks and specifically, can include doping including low-resistance semi-conducting material
Semi-conducting material as adulterate silicon and doping germanium and/or metal-semiconductor compounds material.The metal semiconductor chemical combination
Object material includes metal silicide materials and/or metal silicide-germanide material.Obviously, according to aforementioned embodiment, conductive
Two stackings can also be entirely metal-semiconductor compounds material.And the second Metal contacts 1023-2 can include and the first gold medal
Belong to the identical materials of contact site 1023-1.
Figure 14 shows vertical-type semiconductor devices according to an embodiment of the invention as a result, wherein, utilization is self aligned
Metal contacts and conductive piling post body form the conductive contact with high-aspect-ratio, so as to increase integration density and subtract
Lack and formed the difficulty of contact site and (avoid and for example etch contact hole and with the material of such as metal etc using plasma etching method
Material refills the technology difficulty of contact hole).Masks are also reduced simultaneously, so as to reduce manufacture cost.
Figure 15 to 21 shows the schematic diagram of the flow of the manufacture semiconductor devices according to another embodiment of the disclosure.
First half and aforementioned implementation due to the flow of manufacture semiconductor devices according to another embodiment of the present disclosure
The first half of the flow of the manufacture semiconductor devices of example is identical (referring specifically to the associated description part of Fig. 1-9), therefore, in order to
Brief purpose, details are not described herein.
As shown in figure 15, in the structure of Fig. 9, grid conductor layer 1017 is performed etching such as RIE, such grid conductor layer 1017
It is etched to and is not higher than and the preferably shorter than top surface of channel layer 1003-1,1003-2.Then stack what is stacked with second first
Oxide partition wall is formed on side wall.
As shown in figure 16, diffusion impervious layer and contact metal layer can be sequentially formed in superstructure shown in figure 15.Tool
Body, diffusion impervious layer 1043 is conformally deposited in superstructure shown in figure 15 first, diffusion impervious layer 1043 can include
The metal of TiN, TaN or Ti etc. are included, thickness is 1 to 10nm.Then the conformally deposit contact above diffusion impervious layer 1043
Metal layer 1045, contact metal layer 1045 can include Ni metal, Co, W, Ru and combinations thereof etc., the thickness of contact metal layer 1045
It spends for 5-20nm.
Next, it can selectively etch successively such as RIE contact metal layers, etching diffusion impervious layer, etching oxide
Partition wall and etching such as RIE grid conductor layers.For example, this can be carried out as follows.Specifically, such as Figure 17,18 (a) and 18 (b) (Figure 18
(a) it is sectional view, Figure 18 (b) is vertical view, and AA ' lines therein show the interception position in section) shown in, it can be in contact gold
Belong to and form photoresist on layer 1045, and pass through photoetching and be patterned into photoresist 1019 ' to expose and to form the part of contact hole.It
Afterwards, it is mask with the photoresist 1203 after composition, selective etch such as RIE is carried out to contact metal layer 1045 successively, to diffusion
Barrier layer 1043 carries out selective etch, and selective etch is carried out to oxide partition wall and grid conductor layer 1017 is selected
Property etching such as RIE.Here, etching can stop at the gate dielectric layer 1015 and hard mask layer on the upper surface of substrate 1001
On 1031-1,1031-2.Here, grid conductor layer 1017 is in addition to the portion for staying part within recessed and photoresist 1019 ' blocks
/ outer, the rest part of grid conductor layer 1017 is all etched away.Contact metal layer 1045, diffusion impervious layer 1043 and oxidation
The rest part other than the part that photoresist 1019 ' blocks in object partition wall is all etched away.Another embodiment is first right
Contact metal layer 1045 carries out selective etch such as RIE, stops on diffusion impervious layer 1043, to 1043 He of diffusion impervious layer
Grid conductor layer 1017 carries out selective etch, and (such as RIE selectively leaves and is isolated by the metal that contact metal layer 1045 is formed
Wall), it then 1019 ' blocks and performs etching with photoresist again, only retain the metal divider wall part for needing to form upper metal contact.
Side wall metal includes Ni metal, Co, W, Ru etc..
Then, as shown in figure 19, interlevel dielectric layer 1021 can be formed in the structure shown in Figure 11.Specifically, example
Such as, the photoresist shown in Figure 11 can be removed, then conformally thin dielectric layer 1047, and selectively etched away hard
1047 part of thin dielectric layer of the top face of mask layer 1031-1,1031-2.Thin dielectric layer 1047 may be used as protecting
And/or diffusion impervious layer, nitride material can be included, thickness is 2 to 20nm.Then deposited oxide and it is carried out flat
Change such as CMP to form interlevel dielectric layer 1021, interlevel dielectric layer 1021 be flattened with hard mask layer 1031-1,
The top surface of 1031-2 flushes.1021 thickness of interlevel dielectric layer is 40 to 200nm.
Then, as shown in figure 20, the first groove T1, the second groove T2, can be formed in structure as shown in figure 19
Three groove T3.It specifically, can be selectively to etch hard mask layer 1031-1,1031- for being formed such as RIE by nitride material
2 and thin dielectric layer 1047 and the contact metal layer 1045 that is made of metal material and diffusion impervious layer 1043 to identical depth
Degree, to form the first groove T1, the second groove T2 and third groove T3 in interlevel dielectric layer 1021
Then, as shown in figure 21, contacting metal can be deposited above, and it is planarized CMP to interlayer electricity such as and is situated between
Thus the top surface of matter layer 1021 forms self aligned first Metal contacts 1023- in the first groove T1 and the second groove T2
1st, the second Metal contacts 1023-2 and third Metal contacts 1023-3, the first Metal contacts 1023-1, the second metal connect
Contact portion 1023-2 and third Metal contacts 1023-3 can include Ni metal, Co, W, Ru and combinations thereof etc..
First Metal contacts 1023-1 may be used as the source/drain region (it is formed by the first semiconductor layer 1005-1)
Contact site.Second Metal contacts 1023-2 and the second conductive stacking are aligned with each other in the vertical direction, and can be together
It can be used as the contact site of the source/drain region (it is formed by a part for substrate 1001) below the first channel layer 1003-1.Third gold
Category portion 1023-3 can be reinstated with contact metal layer 1045, diffusion impervious layer 1043 and the grid conductor layer 1,017 1 being disposed below
Make gate contact.First Metal contacts 1023-1, the second Metal contacts 1023-2 and third Metal contacts 1023-3
Identical material may be used to be formed.
Figure 21 shows vertical-type semiconductor devices according to another embodiment of the present invention as a result,.Itself and previous implementation
Example difference lies in 1023-3 is contacted using third metal rather than forms gate contact just with grid conductor layer 1017.
In a further embodiment, in order to increase electric conductivity, in order to reduce the contact resistance of each contact site, preceding
Increase the processing step for forming conductive metal in the technique stated.Specifically, Figure 22 to 29 is shown according to another implementation of the disclosure
The schematic diagram of the flow of the manufacture semiconductor devices of example.
First half and aforementioned implementation due to the flow of manufacture semiconductor devices according to another embodiment of the present disclosure
First half (referring specifically to the associated description part of Fig. 1 to 7 (a) or 7 (b)) phase of the flow of the manufacture semiconductor devices of example
Together, therefore, for brief purpose, details are not described herein.
As shown in figure 22, the deposited metal material in the structure shown in Fig. 7 (a), the metal layer material include W, Co
Or Ru.Then, barrier layer/STI oxide etch stop-layer (not shown) on demand.Using photoresist 1042 to metal layer material
Material is patterned and etches away the metal for not being photo-etched the covering of glue 1042, and the metal layer 1041 of composition is consequently formed.Metal layer
1041 are used as metal wire or metal contact.
In fig 23, it is similar with step shown in Fig. 8, photoresist is removed, in substrate 1001 and shallow groove isolation layer
1033 top deposited oxide, and it is etched back between channel layer 1003-1 and 1003-2 and substrate 1001 interface (that is,
Interface between SiGe layer and Si layers) position, to form the second separation layer 1013.It, can be to the oxygen of deposit before eatch-back
Compound carries out planarization process as chemically-mechanicapolish polished (CMP) or sputtering.
It is similar with step shown in Fig. 9 in Figure 24 (a), it can be in recessed middle formation gate dielectric layer and grid conductor layer.Tool
Body, as shown in Figure 24 (a), sacrificial gate 1007 can be removed in the structure shown in Figure 23, deposits gate dielectric layer 1015 successively
With grid conductor layer 1017, and the grid conductor layer 1017 deposited is etched back, makes itself and hard mask layer 1031-1 and 1031-2
Top surface flush.At the same time part of the metal layer 1041 above hard mask layer 1031-2 is had also been removed.For example, gate dielectric layer
1015 can include high-K gate dielectric such as HfO2；Grid conductor layer 1017 can include metal gate conductor.In addition, in gate dielectric layer
Between 1015 and grid conductor layer 1017, work function regulating course can also be formed, function regulating course can include threshold voltage vt tune
Save metal.Before gate dielectric layer 1015 is formed, the boundary layer of such as oxide can also be formed.
In this way, gate dielectric layer 1015 and grid conductor layer 1017 can be embedded into it is recessed in, and gate dielectric layer 1015 and grid
The top surface of conductor layer 1017 is flushed with the top surface of hard mask layer 1031-1,1031-2.
In Figure 24 (b), on the basis of the structure shown in Figure 24 (a), it is etched into one so that nitride and gold
It is recessed to belong to layer 1041, and then deposition of nitride with formed nitride cap 1031-2 (it is consistent with hard mask layer 1031-2 materials,
Also referred to as hard mask layer 1031-2), electric isolution has been better achieved as a result,.
In fig. 25, it is similar with step shown in Fig. 10, grid conductor layer will can be patterned, to form grid stacking,
Specifically, as shown in figure 25, photoresist can be coated in the structure shown in Figure 24 (b), photoresist is patterned to be formed
Then photoresist layer 1039 is mask with photoresist 1039, selective etch such as RIE is carried out to grid conductor layer 1017.In this way, grid
Conductor layer 1017 in addition to stay part within recessed and part that photoresist 1019 blocks other than, grid conductor layer 1017 remaining
Part, which is etched to, to be not higher than and the preferably shorter than top surface of channel layer 1003-1,1003-2.
Then, as shown in figure 26, remove photoresist layer 1039, coat photoresist again, and photoresist is patterned with
Photoresist layer 1019 is formed, is then mask with photoresist 1019, carries out selective quarter again to remaining grid conductor layer 1017
Erosion such as RIE.In this way, grid conductor layer 1017 in addition to stay part within recessed and part that photoresist 1039 blocks other than, grid
The rest part of conductor layer 1017 is all etched away.Grid conductor layer is formed only into as a result, stacks week as the first of active area
It encloses, and there is no grid conductor layer around being stacked second.It is stacked at this point, grid conductor layer 1017 and gate dielectric layer 1015 form grid.It should
Grid stacking may be used as gate contact.
It is then possible to as shown in figure 27, interlevel dielectric layer 1021 is formed in the structure shown in Figure 26.Specifically, example
Such as, it can be planarized with deposited oxide and to it and form interlevel dielectric layer 1021, interlevel dielectric layer 1021 such as CMP
It is flattened and is flushed with the top surface with hard mask layer 1031-1,1031-2.
Then, in Figure 28, can selectively etch hard mask layer 1031-1,1031-2, in interlevel dielectric layer
The first groove T1 and the second groove T2 are formed in 1021.Then, as shown in figure 29, contacting metal, and its can be deposited above
Planarized such as CMP to the top surface of interlevel dielectric layer 1021, thus formed in the first groove T1 and the second groove T2 from
The the first Metal contacts 1023-1 and the second Metal contacts 1023-2 of alignment.Due to being pre-formed with gold in the second groove
Belong to layer 1041, help to realize the better conductive contact of the second contact site, increase electric conductivity.
Various electronic equipments can be applied to according to the semiconductor devices of the embodiment of the present disclosure.For example, by integrated multiple
Such semiconductor devices and other devices (for example, transistor of other forms etc.), can form integrated circuit (IC), and
Thus electronic equipment is built.Therefore, the disclosure additionally provides a kind of electronic equipment including above-mentioned semiconductor device.Electronic equipment
It can also include the components such as the display screen coordinated with integrated circuit and the wireless transceiver coordinated with integrated circuit.This electricity
Sub- equipment is such as smart phone, computer, tablet computer (PC), artificial intelligence, wearable device, mobile power.
In accordance with an embodiment of the present disclosure, the manufacturing method of chip system (SoC) a kind of is additionally provided.This method can include
The method of above-mentioned manufacture semiconductor devices.Specifically, a variety of devices can be integrated on chip, wherein at least some are according to this
Disclosed method manufacture.
In the above description, the technical details such as the composition for each layer, etching are not described in detail.But
It it will be appreciated by those skilled in the art that can be by various technological means, to form layer, region of required shape etc..In addition, it is
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limitation the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from
The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should be all fallen in the disclosure
Within the scope of.
Claims (26)
1. a kind of semiconductor devices, including：
Substrate；
The vertical active area formed on substrate, including vertically set gradually the first source/drain region, channel region and second
Source/drain region；
The grid formed around the periphery of channel region stack；
To the first contact site of the second source/drain region above second source/drain region, wherein, the first contact site periphery and the second source/drain region
Periphery substantial registration.
2. semiconductor devices according to claim 1, wherein,
The periphery of first contact site and the periphery of the second source/drain region are substantially coincident；Or
The semiconductor devices also includes the metal-semiconductor compounds layer formed on the surface of the second source/drain region, wherein, first
The periphery of contact site and the periphery of metal-semiconductor compounds layer formed on the surface of the second source/drain region are substantially coincident.
3. semiconductor devices according to claim 1, wherein,
First source/drain region includes extending beyond the lateral extension portions of the active region above it,
The semiconductor devices further includes：To the second contact of the first source/drain region above the lateral extension portions of first source/drain region
Portion,
Wherein, the second contact site includes being sequentially stacked first part aligned with each other on substrate and in the vertical direction and second
Part,
Wherein, first part includes low-resistance semi-conducting material and/or metal-semiconductor compounds.
4. the semiconductor devices according to claim 1 or 3, wherein, the first contact site and/or the second contact site include metal
Cu, Co, W, Ru and combinations thereof etc..
5. semiconductor devices according to claim 3, wherein,
The second part of second contact site includes the material identical with the first contact site, and with the first contact site in the vertical direction
Thickness it is essentially identical, the first part of the second contact site includes semi-conducting material and/or metal-semiconductor compounds material.
6. semiconductor devices according to claim 5, wherein,
Element in the semi-conducting material that the first part of second contact site includes at least partly with first source/
Part semiconductor element in drain region or channel region or the second source/drain region is identical.
7. semiconductor devices according to claim 3, the second contact site, which further includes, to be surrounded outside first part and second part
The metal layer in week.
8. semiconductor devices according to claim 7, wherein, the first part for surrounding the second contact site and second
Exceptionally all metal layers include Ni metal, the several combination of Co, W, Ru or wherein arbitrary.
9. semiconductor devices according to claim 1, further includes：
The third contact site of grid conductor layer in being stacked to grid.
10. semiconductor devices according to claim 9, wherein,
Third contact site and grid conductor layer are integrated；Or
Third contact site includes the material identical with the first contact site.
11. a kind of semiconductor devices, including：
Substrate；
The vertical active area formed on substrate, including vertically set gradually the first source/drain region, channel region and second
Source/drain region；
The grid formed around the periphery of channel region stack；
The divider wall of side wall formation above grid stacking and in active area；
The autoregistration Metal contacts formed above grid stacking and on divider wall side wall.
12. semiconductor devices according to claim 11 is additionally included in what is formed above the autoregistration Metal contacts
With the substantially self aligned third contact site of the autoregistration metal contact portion.
13. semiconductor devices according to claim 12 is additionally included in above grid stacking and conformal in the side wall of divider wall
The diffusion impervious layer that ground is formed；
The metal contact layer being just conformally formed on the diffusion barrier；
In the thin dielectric layer that the side wall of metal contact layer is conformally formed；
The autoregistration metal contact portion formed by diffusion impervious layer and metal contact layer；
Formed in autoregistration metal contact portion with the substantially self aligned third contact site of autoregistration metal contact portion.
14. the semiconductor devices according to claim 11 or 12, wherein, autoregistration metal contact portion and/or third contact site
Include Ni metal, Co, W, Ru and wherein arbitrary several combination.
15. a kind of method for manufacturing semiconductor devices, including：
Active area materials layer is set on substrate；
Hard mask layer is set on active area materials layer, and hard mask layer includes the first part for limiting active area；
Using hard mask layer as mask, active area materials layer is patterned, so as to limit vertical active area；
Interlevel dielectric layer is formed on substrate, and planarization process is carried out to it, to expose hard mask layer；
Selective etch hard mask layer, to remove hard mask layer, so as to be left in interlevel dielectric layer and vertical active area phase
Corresponding first slot；
Conductive material is filled in the first slot, to form the first contact site.
16. the method according to claim 11, wherein,
Hard mask layer further includes the second part being separated with first part,
When being patterned to active area materials layer, the bottom surface of active area materials layer is proceeded to being patterned at for active area materials layer
Stop before, then active area materials layer be patterned to the first part of hard mask layer it is corresponding as active area first
It stacks and is stacked, and the first stacking is stacked on bottom with second and is connected to the second part corresponding second of hard mask layer
Together,
After selective etch hard mask layer, also left in interlevel dielectric layer and stack corresponding second slot with second,
When conductive material is filled in the first slot, conductive material is also filled into the second slot, so as to form the second contact site.
17. it according to the method for claim 15, further includes：
The portion perimeter that channel region will be formed in being stacked first forms barrier layer；
It is stacked first and dopant active layer is formed on the surface stacked with second；
The dopant in dopant active layer is made to enter a stack of end portion and upper part to be respectively formed the first source/drain
Area and the second source/drain region, and enter in the entire second stacking.
18. it according to the method for claim 17, further includes：
In the case of there are barrier layer, stacked first and metal-semiconductor compounds layer is formed on the surface stacked with second.
19. the method according to claim 11, wherein,
Active area materials layer includes the first source drain, channel layer and the second source drain that are sequentially stacked,
Barrier layer is formed to include：
Selective etch channel layer so that the periphery of channel layer is recessed relative to the periphery of the first source drain and the second source drain
Enter；
The periphery of channel layer relative to first, second source drain periphery formed it is recessed in, form the barrier layer.
20. the method according to any one of claim 15 to 19, further includes：
Separation layer is formed on substrate, and the separation layer exposes the part for being used as channel region in active area；
The periphery for being used as the part of channel region in active area on separation layer forms grid stacking.
21. method during claim 19 is subordinated to according to claim 20, wherein, it forms grid stacking and includes：
Remove barrier layer；
Gate dielectric layer and grid conductor layer are sequentially formed on separation layer；
Grid conductor layer is planarized, to expose hard mask layer；
A part of grid conductor layer is covered using the first masking layer detached is stacked with first；
In the case of there are the first masking layer, it is etched back grid conductor layer so that the top surface of the eatch-back part of grid conductor layer is less than ditch
The top surface of channel layer；
A part of grid conductor layer is covered using the second masking layer to overlap is stacked with first, wherein the second masking layer is completely covered
The grid conductor layer portion covered by the first masking layer；
In the case of there are the second masking layer, grid conductor layer is etched back, wherein eatch-back is carried out to the bottom surface of grid conductor layer.
22. method during claim 19 is subordinated to according to claim 20, wherein, it forms grid stacking and includes：
Remove barrier layer；
Gate dielectric layer and grid conductor layer are sequentially formed on separation layer；
It is etched back grid conductor layer so that the top surface of part of the grid conductor layer except the female is less than the top surface of channel layer；
It is stacked first and medium side wall is formed on the side wall stacked with second；
Form conductive material layer；
A part of conductive material layer is covered using the masking layer to overlap is stacked with first；
In the case of there are masking layer, conductive material layer and grid conductor layer are etched back, wherein eatch-back is carried out to grid conductor
The bottom surface of layer.
23. the method according to claim 11, wherein,
In selective etch hard mask layer, conductive material layer is also removed, so as to leave third slot in interlevel dielectric layer,
When conductive material is filled in the first slot, conductive material is also filled into third slot, so as to form third contact site.
24. a kind of electronic equipment, including the integrated electricity formed as the semiconductor devices as described in any one of claim 1 to 14
Road.
25. electronic equipment according to claim 24, further includes：With the integrated circuit cooperation display and with institute
State the wireless transceiver of integrated circuit cooperation.
26. electronic equipment according to claim 25, which includes smart phone, computer, tablet computer, people
Work intelligence, wearable device or mobile power.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019128076A1 (en) * | 2017-12-27 | 2019-07-04 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing same, and electronic device comprising same |
| CN110957325A (en) * | 2018-09-27 | 2020-04-03 | 苏州东微半导体有限公司 | Semiconductor memory and method of manufacturing the same |
| CN111668294A (en) * | 2020-06-12 | 2020-09-15 | 中国科学院微电子研究所 | Vertical semiconductor device with conductive layer, method of manufacturing the same, and electronic apparatus |
| CN113053943A (en) * | 2021-03-18 | 2021-06-29 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN113257918A (en) * | 2021-04-29 | 2021-08-13 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| WO2023070963A1 (en) * | 2021-10-25 | 2023-05-04 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN116546815A (en) * | 2023-06-21 | 2023-08-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504359A (en) * | 1990-10-31 | 1996-04-02 | Texas Instruments Incorporated | Vertical FET device with low gate to source overlap capacitance |
| CN102832221A (en) * | 2011-06-16 | 2012-12-19 | 三星电子株式会社 | Semiconductor device provided with vertical apparatus and non-vertical apparatus and method for forming the same |
| CN106158935A (en) * | 2014-08-29 | 2016-11-23 | 台湾积体电路制造股份有限公司 | Vertical transistor and manufacture method thereof |
-
2017
- 2017-12-27 CN CN201711452736.2A patent/CN108198815B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504359A (en) * | 1990-10-31 | 1996-04-02 | Texas Instruments Incorporated | Vertical FET device with low gate to source overlap capacitance |
| CN102832221A (en) * | 2011-06-16 | 2012-12-19 | 三星电子株式会社 | Semiconductor device provided with vertical apparatus and non-vertical apparatus and method for forming the same |
| CN106158935A (en) * | 2014-08-29 | 2016-11-23 | 台湾积体电路制造股份有限公司 | Vertical transistor and manufacture method thereof |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019128076A1 (en) * | 2017-12-27 | 2019-07-04 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing same, and electronic device comprising same |
| US11756956B2 (en) | 2017-12-27 | 2023-09-12 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device, manufacturing method thereof, and electronic apparatus including the same |
| CN110957325A (en) * | 2018-09-27 | 2020-04-03 | 苏州东微半导体有限公司 | Semiconductor memory and method of manufacturing the same |
| CN110957325B (en) * | 2018-09-27 | 2022-04-19 | 苏州东微半导体股份有限公司 | Semiconductor memory and method of manufacturing the same |
| CN111668294A (en) * | 2020-06-12 | 2020-09-15 | 中国科学院微电子研究所 | Vertical semiconductor device with conductive layer, method of manufacturing the same, and electronic apparatus |
| CN111668294B (en) * | 2020-06-12 | 2024-05-14 | 中国科学院微电子研究所 | Vertical semiconductor device with conductive layer, method of manufacturing the same, and electronic apparatus |
| CN113053943A (en) * | 2021-03-18 | 2021-06-29 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN113257918A (en) * | 2021-04-29 | 2021-08-13 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| WO2023070963A1 (en) * | 2021-10-25 | 2023-05-04 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN116546815A (en) * | 2023-06-21 | 2023-08-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116546815B (en) * | 2023-06-21 | 2023-11-24 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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|---|---|
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