CN108198754B - Manufacturing method of polycrystalline silicon TFT substrate and polycrystalline silicon TFT substrate - Google Patents

Manufacturing method of polycrystalline silicon TFT substrate and polycrystalline silicon TFT substrate Download PDF

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CN108198754B
CN108198754B CN201711258888.9A CN201711258888A CN108198754B CN 108198754 B CN108198754 B CN 108198754B CN 201711258888 A CN201711258888 A CN 201711258888A CN 108198754 B CN108198754 B CN 108198754B
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CN108198754A (en
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刘丹
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

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Abstract

The embodiment of the invention discloses a manufacturing method of a polycrystalline silicon TFT substrate, which comprises the following steps: step S10, depositing an amorphous silicon film layer on the substrate base plate; step S11, performing excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer; step S12, carrying out ion doping on the channel region of the polysilicon active layer to form a channel doped region; step S13, depositing a gate insulation layer on the polysilicon active layer; step S14, hydrogen ions are injected into the channel region of the active layer polysilicon; step S15, depositing a gate layer on the gate insulating layer; step S16, carrying out ion doping on a source region and a drain region of the polysilicon active layer to form a source doped region and a drain doped region; step S17, depositing an interlayer insulating layer on the gate layer; step S18, forming a first via hole and a second via hole on the interlayer insulating layer, and depositing a source electrode film layer and a drain electrode film layer respectively, which are electrically connected to the source doped region and the drain doped region, respectively. The invention also discloses a corresponding polycrystalline silicon TFT substrate. By implementing the invention, the concentration and the depth of hydrogen atom supplement can be accurately controlled, and the yield of the TFT is improved.

Description

Manufacturing method of polycrystalline silicon TFT substrate and polycrystalline silicon TFT substrate
Technical Field
The present invention relates to the field of display, and in particular, to a method for manufacturing a polysilicon TFT (Thin Film Transistor) substrate and a polysilicon TFT substrate.
Background
In the mainstream polysilicon TFT process at present, an MOS (metal oxide semiconductor) transistor is generally manufactured by ion implantation, and since a crystal itself has some defects and impurities and the implanted ions introduce a new energy level, the electrical properties of doped polysilicon (such as boron doping) cannot meet the requirements. In the prior art, the common solution is to fill the polysilicon crystal defects by hydrogen supplementation, passivate the implanted boron ions, and increase electron mobility. The conventional hydrogen atoms are implanted by thermal diffusion, and hydrogen in an interlayer Insulating Layer (ILD) layer is diffused to the surface layer of the active layer polysilicon by high temperature. The method is difficult to estimate the depth and concentration of hydrogen element supplement (usually, the amount of hydrogen atom supplement is measured according to the time of hydrogen supplement by empirical values), and hydrogen supplement can only be performed after ILD film formation, and is easily broken holes are formed after high temperature due to the influence of organic residue before film formation and the like.
In addition, experiments show that the boron-doped silicon has the advantages of reduced carrier concentration, increased mobility, increased resistivity and reduced capacitance after hydrogenation. The deep distribution analysis of the secondary ion mass spectrum shows that the distribution of hydrogen and boron has a corresponding relationship, and as long as more stable hydrogen molecules are not formed, no matter which model the crystal lattice conforms to, the hydrogen in the boron-hydrogen (B-H) complex always has a passivation effect on the boron. It is inferred that, in the channel (Chanel) region where the electrical characteristics of the TFT are most affected, the optimal electrical characteristics can be obtained if the concentration distributions of boron (B) and hydrogen (H) completely coincide with each other (forming a B — H complex). In fact, however, the thermal diffusion process depends on a concentration gradient, the concentration of the thermal diffusion process decreases progressively from the surface layer to the interior of the polysilicon, and the thermal diffusion process is in a gaussian distribution, as shown in fig. 1, which shows a schematic diagram of a concentration-depth corresponding relationship of thermal diffusion hydrogen supplementation in the prior art; while ion implantation has the highest concentration at the targeted depth, for example, in one example, simulating that 1E 4B + ions were implanted into 500A polysilicon at 8Kev (kilo electron volts) energy, the resulting ion concentration versus depth plot is shown in fig. 2, from which it can be seen that boron ions have the highest concentration at the targeted depth. Therefore, in the polycrystalline silicon, hydrogen is replenished by high-temperature expansion, and the hydrogen concentration and the boron concentration cannot be well overlapped.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a polycrystalline silicon TFT substrate and a corresponding polycrystalline silicon TFT substrate, which can improve the hydrogen supplementing effect in the manufacturing of the polycrystalline silicon TFT substrate, can accurately control the concentration and the depth of hydrogen atom supplementation, and improve the yield and the performance of the polycrystalline silicon TFT substrate.
In order to solve the above technical problem, an aspect of an embodiment of the present invention provides a method for manufacturing a polysilicon TFT substrate, including:
step S10, depositing an amorphous silicon film layer on the substrate base plate;
step S11, performing excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer;
step S12, carrying out ion doping on the channel region of the polysilicon active layer to form a channel doped region;
step S13, depositing a gate insulation layer on the polysilicon active layer;
step S14, controlling to implant hydrogen ions into the channel region of the active layer polysilicon by adopting an ion implanter;
step S15, depositing a gate layer on the gate insulating layer;
step S16, carrying out ion doping on a source region and a drain region of the polysilicon active layer to form a source doped region and a drain doped region;
step S17, depositing an interlayer insulating layer on the gate layer;
step S18, forming a first via hole and a second via hole on the interlayer insulating layer at positions facing the source doped region and the drain doped region, and depositing a source electrode film layer and a drain electrode film layer in the first via hole and the second via hole respectively, so that the source electrode film layer is electrically connected to the source doped region of the polysilicon active layer through the first via hole, and the drain electrode film layer is electrically connected to the drain doped region of the polysilicon active layer through the second via hole.
Wherein the step S12 further includes:
and adopting an ion implanter to control to implant boron-containing ion materials into the channel region of the polycrystalline silicon active layer to form a channel doping region, wherein the boron-containing ion materials are B2H6 or BF 3.
Wherein, the step S12 specifically includes:
setting a first implantation energy value and a boron ion concentration value in an ion implanter, and controlling the boron-containing ion material to be implanted into the polysilicon active layer at the first implantation angle according to the first implantation energy value.
Wherein, the step S13 specifically includes:
and setting a second implantation energy value and a hydrogen ion concentration in an ion implanter, and controlling to implant hydrogen ions into the polysilicon active layer at the second implantation angle according to the first implantation energy value so that the hydrogen ions and the boron ions form a boron-hydrogen complex.
Wherein, further include:
step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer at a position facing the drain electrode film layer;
step S190, forming a pixel electrode layer on the planarization layer, so that the pixel electrode layer extends into the third via hole and is electrically connected to the drain electrode film layer.
Wherein, in the step S16, the method further comprises:
and carrying out ion doping between the source region, the drain region and the channel region of the polycrystalline silicon active layer to respectively form a doping buffer region.
Accordingly, another aspect of the embodiments of the present invention also provides a polysilicon TFT substrate, which is manufactured by the foregoing method, the polysilicon TFT substrate including:
a substrate base plate;
a polycrystalline silicon active layer formed by depositing an amorphous silicon film layer on the substrate and performing excimer laser annealing; the polycrystalline silicon active layer comprises a channel doping region in the middle and source drain doping regions on two sides of the channel doping region, wherein hydrogen ions are implanted into the channel doping region by adopting an ion implanter;
the gate insulation layer is deposited and formed on the polycrystalline silicon active layer;
the gate electrode layer is deposited and formed on the gate insulating layer;
the polycrystalline silicon active layer comprises a gate layer, a source electrode film layer and a drain electrode film layer, wherein the gate layer is formed on the gate layer in a deposition mode, the source electrode film layer is formed on the gate layer in a position, opposite to the source electrode doped region and the drain electrode doped region, the first via hole and the second via hole are respectively formed in a deposition mode, the source electrode film layer is electrically connected with the source electrode doped region of the polycrystalline silicon active layer through the first via hole, and the drain electrode film layer.
Wherein, further include:
the flat layer is arranged on the interlayer insulating layer, and a third through hole is formed in the position, opposite to the drain electrode film layer, of the flat layer;
and the pixel electrode layer is arranged on the flat layer, extends into the third through hole and is electrically connected with the drain electrode film layer.
And doping buffer regions are respectively formed among the source electrode doping region, the drain electrode doping region and the channel region of the polycrystalline silicon active layer through ion doping.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the hydrogen supplementing process is arranged before the manufacture of the gate layer (M1), so that the hydrogen supplementing operation is completed before the manufacture of the gate layer (M1), sufficient hydrogen ions can be supplemented to the channel, and meanwhile, the target depth and concentration of the hydrogen ions can be coincided with the target depth and concentration distribution of boron ions by controlling the injection energy value, so as to form a boron-hydrogen complex, thereby improving the mobility of electrons in the channel;
in addition, because the source of the hydrogen ions does not depend on an interlayer Insulating Layer (ILD), high-temperature annealing is not needed after the ILD is formed, the ILD holes can be avoided, the performance of the thin film transistor is improved, and the yield of products is improved;
in addition, in the embodiment of the invention, the hydrogen supplementing operation is carried out in an ion implantation mode, the depth and the concentration of hydrogen atom supplementing can be accurately controlled, and the process is very simple and feasible.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram illustrating the correspondence between the concentration and the depth of the thermal diffusion hydrogen replenishment in the prior art;
FIG. 2 is a graph showing ion concentration versus depth obtained by implanting boron ions into silicon by ion implantation in one example of the prior art;
FIG. 3 is a schematic flow chart illustrating one embodiment of a method for fabricating a polysilicon TFT substrate according to the present invention;
FIG. 4 is a schematic diagram illustrating simulation of energy versus target depth for boron ion implantation into crystalline silicon in one embodiment;
FIG. 5 is a schematic diagram illustrating simulation of energy versus target depth for hydrogen ion implantation into crystalline silicon in one embodiment;
FIG. 6 is a graphical representation of the energy versus target depth for simulating implantation of hydrogen ions into silicon oxide (SiOx) in one embodiment;
FIG. 7 is a graph illustrating ion concentration versus depth simulated for 1E4 hydrogen ions implanted into 1300A SiO +500A Si at 8Kev energy in one embodiment;
fig. 8 is a schematic structural diagram of an embodiment of a polysilicon TFT substrate provided in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.
Fig. 3 is a schematic main flow chart of fig. 2 illustrating an embodiment of a method for fabricating a polysilicon TFT substrate according to the present invention; in this embodiment, the method comprises at least the following steps:
in step S10, an enhanced chemical vapor deposition method is used to fabricate an amorphous silicon film layer on a substrate, which may be a glass substrate or a flexible PI (polyimide resin) substrate.
And step S11, performing excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer.
Step S12, carrying out ion doping on the channel region of the polysilicon active layer to form a channel doped region; specifically, a small amount of donor or acceptor impurity ions (such as boron ions) are implanted into the channel region by an ion implantation technology to adjust the threshold voltage of the device; specifically, in some examples, this step S12 may include using an ion implanter to control the implantation of boron ions (i.e., boron ion material) into the channel region of the polysilicon active layer to form a channel doped region, where the boron ion material is B2H6, BF3, or the like;
specifically, the step S12 sets a first implantation energy value (e.g., 8Kev) and a boron ion concentration value in an ion implanter, and controls the implantation of the boron-containing ion material into the channel region of the polysilicon active layer at a target angle (90 degrees) with the first implantation energy value.
In step S13, a gate insulation layer (GI) is deposited on the polysilicon active layer.
Step S14, controlling to implant hydrogen ions into the channel region of the active layer polysilicon by adopting an ion implanter; specifically, in an example, the step S14 specifically includes:
setting a second implantation energy value (such as 8Kev) and a hydrogen ion concentration in the ion implanter, and controlling the implantation of hydrogen ions into the channel region of the polysilicon active layer at a target angle (90 degrees) by the second implantation energy value so that the hydrogen ions and free boron ions form a boron-hydrogen complex. It will be appreciated that the control of the supply of hydrogen to the ion implanter is achieved by setting the implantation energy and the hydrogen concentration in the ion implanterAnd the active layer polysilicon is implanted with the targeted depth and concentration of hydrogen ions. The hydrogen ion material may be, for example, B2H6、PH3And so on.
It is understood that in the embodiment of the present invention, the implantation of the hydrogen ions (H +) is provided after the deposition of the gate insulating layer, and the principle thereof is illustrated as follows: because the stopping ability of Si to H + is much weaker than that of Si to boron ions (B +), the theory deduces that if 8Kev is used for injecting B + into a channel region, the same target depth can be achieved only by 2Kev for injecting H +; reference may be made to fig. 4 and 5, which show a schematic diagram of the energy versus target depth for simulating boron ion implantation into crystalline silicon and a schematic diagram of the energy versus target depth for simulating hydrogen ion implantation into crystalline silicon in one example, respectively, from which it can be seen that the hydrogen ion implantation energy is smaller for reaching the same target depth under similar conditions. Wherein "Ion Energy" represents an injection Energy value, "Projected Range" represents a projection Range (target depth), "Longitudinal Stragging" represents Longitudinal dispersion, and "lateral Stragging" represents lateral dispersion; "-dE/dx" indicates the energy loss per unit distance of the incident ion, hindered by the nucleus and the electrons; "Target Density" represents the Target Density, and "Ion Range" represents the Ion Range.
However, the current mainstream implanter in the panel industry is Nissin iG6, 2Kev, which is an operating range that is easy to cause electrode plate discharge (arc) for the Acc power supply of the device. Therefore, in the embodiments of the present invention, the H + implantation process is performed after the gate insulating layer deposition process, and at this time, when H + implantation is performed on the active layer, the gate insulating layer needs to be penetrated, so that in one embodiment, the implantation energy of H + can be controlled to be similar to that of B +, for example, when H + is implanted, 8Kev implantation energy can be used, so that the concentration distributions of B + and H + can be optimally overlapped.
In step S15, a gate layer (M1) is deposited on the gate insulating layer.
In step S16, the source region and the drain region of the polysilicon active layer are ion-doped to form a source-drain doped region, and it is understood that the ion-doped material in this step may be a PHx material. It is understood that, in the step S16, the method further includes: ion doping is carried out between the source region, the drain region and the channel region of the polycrystalline silicon active layer, and a doping buffer region is respectively formed.
In step S17, an interlayer Insulating Layer (ILD) is deposited on the gate layer.
Step S18, forming a first via hole and a second via hole on the interlayer insulating layer at positions opposite to the source region and the drain doped region, respectively depositing a source electrode film layer and a drain electrode film layer (M2) in the first via hole and the second via hole, so that the source electrode film layer is electrically connected with the source region of the polysilicon active layer through the first via hole, and the drain electrode film layer is electrically connected with the drain doped region of the polysilicon active layer through the second via hole.
Step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer at a position facing the drain electrode film layer;
step S190, forming a pixel electrode layer on the planarization layer, so that the pixel electrode layer extends into the third via hole and is electrically connected to the drain electrode film layer.
As shown in fig. 6, a graphical representation of the energy versus target depth for a simulation of hydrogen ion implantation into silicon oxide (SiOx) in one embodiment is shown, from which it can be seen that the relationship therein is very similar to the graph shown in fig. 5.
FIG. 7 is a graph showing ion concentration versus depth simulated for 1E4 hydrogen ions implanted into 1300A SiO2+500A Si at 8Kev energy in one embodiment; it can be seen that hydrogen ions have the highest concentration at an Ion Range (Ion Range) by the Ion implantation. And because the concentration distribution after hydrogen ion implantation is similar to the distribution of boron ions in the channel (can be compared with fig. 2), the implantation method can monitor the hydrogen atom implantation concentration and dosage and maximize the hydrogen implantation effect. Here, "Ion Range" indicates an Ion Range, "Straggle" indicates dispersion, "Skewness" indicates Skewness, "Kurtosis" indicates Kurtosis, the abscissa indicates an implantation Depth (Target Depth), and the ordinate indicates a hydrogen Ion concentration.
Fig. 8 is a schematic structural diagram illustrating an embodiment of a polysilicon TFT substrate according to the present invention. In this embodiment, the polysilicon TFT substrate is manufactured by the method described above, and specifically, the polysilicon TFT substrate 10 includes:
a substrate base plate 10, which may be a glass base plate or a flexible PI (polyimide resin) base plate;
a polycrystalline silicon active layer 13 formed by depositing an amorphous silicon film layer on the substrate base plate 10 and performing excimer laser annealing; the polysilicon active layer 13 includes a channel doping region 130 in the middle, a source doping region 131 and a drain doping region 132 on both sides of the channel doping region 130, wherein hydrogen ions are implanted in the channel doping region by using an ion implanter; a doped buffer region 133 is respectively formed between the source doped region 131, the drain doped region 132 and the channel doped region 130 of the polysilicon active layer by ion doping;
a gate insulating layer 14 deposited on the polysilicon active layer 13;
a gate electrode layer 15 deposited on the gate insulating layer 14;
an interlayer insulating layer 16 deposited on the gate layer 15, wherein a first via 160 and a second via 161 are formed on the interlayer insulating layer 16 at positions facing the source doped region 131 and the drain doped region 132, an active electrode film layer 162 and a drain electrode film layer 163 are respectively deposited in the first via 160 and the second via 161, the active electrode film layer 162 is electrically connected to the source doped region 131 of the polysilicon active layer through the first via 160, and the drain electrode film layer 163 is electrically connected to the drain doped region 132 of the polysilicon active layer through the second via 161;
a planarization layer 17 disposed on the interlayer insulating layer 16, wherein a third via hole 171 is formed on the planarization layer 17 at a position facing the drain electrode film layer 163;
and a pixel electrode layer 18 disposed on the planarization layer 17, wherein the pixel electrode layer 18 extends into the third via hole 171 and is electrically connected to the drain electrode film layer 163.
Further, a buffer layer 12 may be further disposed between the base substrate 10 and the polysilicon active layer 13. It is understood that, in an example, the buffer layer 12, the gate insulating layer 14, and the interlayer insulating layer 16 may be made of SiNx/SiO2 material, the planarization layer 17 may be made of SiNx or organic film material, the pixel electrode layer 18 may be made of metal oxide material (such as ITO), and the source electrode film layer 162 and the drain electrode film layer 163 may be made of metal material, such as metallic titanium, aluminum-titanium alloy, or the like.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the hydrogen supplementing process is arranged before the manufacture of the gate layer (M1), so that the hydrogen supplementing operation is completed before the manufacture of the gate layer (M1), sufficient hydrogen ions can be supplemented to the channel, and meanwhile, the target depth and concentration of the hydrogen ions can be coincided with the target depth and concentration distribution of boron ions by controlling the injection energy value, so as to form a boron-hydrogen complex, thereby improving the mobility of electrons in the channel;
meanwhile, in the invention, the hydrogen supplement operation is arranged after the Excimer Laser Annealing (ELA) process, so that the phenomena of poor crystallization and the like caused by hydrogen explosion in the prior art can be avoided;
in addition, in the embodiment of the invention, the hydrogen supplementing operation is carried out in an ion implantation mode, the depth and the concentration of hydrogen atom supplementing can be accurately controlled, and the process is very simple and feasible.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing is directed to embodiments of the present application and it is noted that numerous modifications and adaptations may be made by those skilled in the art without departing from the principles of the present application and are intended to be within the scope of the present application.

Claims (6)

1. A method for manufacturing a polysilicon TFT substrate is characterized by comprising the following steps:
step S10, depositing an amorphous silicon film layer on the substrate base plate;
step S11, performing excimer laser annealing on the amorphous silicon film layer to form a polysilicon active layer;
step S12, setting a first implantation energy value, a first implantation angle and a boron ion concentration value in an ion implanter, and controlling a boron ion-containing material to be implanted into the channel region of the polysilicon active layer at the first implantation angle according to the first implantation energy value, so as to perform ion doping on the channel region of the polysilicon active layer, thereby forming a channel doped region;
step S13, depositing a gate insulation layer on the polysilicon active layer;
step S14, setting a second implantation energy value and a hydrogen ion concentration in the ion implanter, and controlling to implant hydrogen ions into the channel region of the polysilicon active layer at a targeted angle according to the second implantation energy value, so that the hydrogen ions and the free boron ions form a boron-hydrogen complex;
step S15, depositing a gate layer on the gate insulating layer;
step S16, carrying out ion doping on a source region and a drain region of the polysilicon active layer to form a source doped region and a drain doped region;
step S17, depositing an interlayer insulating layer on the gate layer;
step S18, forming a first via hole and a second via hole on the interlayer insulating layer at positions opposite to the source doped region and the drain doped region, respectively depositing a source electrode film layer and a drain electrode film layer in the first via hole and the second via hole, so that the source electrode film layer is electrically connected with the source doped region of the polysilicon active layer through the first via hole, and the drain electrode film layer is electrically connected with the drain doped region of the polysilicon active layer through the second via hole;
step S19, forming a flat layer on the interlayer insulating layer, and forming a third via hole on the flat layer at a position facing the drain electrode film layer;
step S20, forming a pixel electrode layer on the planarization layer, so that the pixel electrode layer extends into the third via hole and is electrically connected to the drain electrode film layer.
2. The method of claim 1, wherein the boron-ion material is B2H6Or BF3。
3. The method of claim 2, wherein in the step S16, further comprising:
and carrying out ion doping between the source electrode doped region, the drain electrode doped region and the channel region of the polycrystalline silicon active layer to respectively form a doped buffer region.
4. A polysilicon TFT substrate manufactured by the method of any one of claims 1 to 3, the polysilicon TFT substrate comprising:
a substrate base plate;
a polycrystalline silicon active layer formed by depositing an amorphous silicon film layer on the substrate and performing excimer laser annealing; the polycrystalline silicon active layer comprises a channel doping region in the middle and source drain doping regions on two sides of the channel doping region, wherein hydrogen ions are implanted into the channel doping region by adopting an ion implanter;
the gate insulation layer is deposited and formed on the polycrystalline silicon active layer;
the gate electrode layer is deposited and formed on the gate insulating layer;
the polycrystalline silicon active layer comprises a gate layer, a source electrode film layer and a drain electrode film layer, wherein the gate layer is formed on the gate layer in a deposition mode, the source electrode film layer is formed on the gate layer in a position, opposite to the source electrode doped region and the drain electrode doped region, the first via hole and the second via hole are respectively formed in a deposition mode, the source electrode film layer is electrically connected with the source electrode doped region of the polycrystalline silicon active layer through the first via hole, and the drain electrode film layer.
5. The polysilicon TFT substrate of claim 4, further comprising:
the flat layer is arranged on the interlayer insulating layer, and a third through hole is formed in the position, opposite to the drain electrode film layer, of the flat layer;
and the pixel electrode layer is arranged on the flat layer, extends into the third through hole and is electrically connected with the drain electrode film layer.
6. The polycrystalline silicon TFT substrate of claim 5, wherein a doping buffer region is formed between the source doping region, the drain doping region and the channel region of the polycrystalline silicon active layer by ion doping, respectively.
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