CN108155939B - Power test method in GSM _ R digital optical fiber repeater - Google Patents
Power test method in GSM _ R digital optical fiber repeater Download PDFInfo
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
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Abstract
The invention discloses a method and a system for realizing the power test of a GSM _ R digital optical fiber repeater by utilizing a CPU and an FPGA in an AU system. The invention uses an algorithm and design, can be simultaneously suitable for power test of GSM _ R3 signal source (full time slot, 1/2 time slot, 1/8 time slot) formats, and makes the system design simpler. The invention can accurately test the power of the transceiving channels of AU and RU only by utilizing redundant logic resources in the FPGA, thereby avoiding the power test by the traditional hardware circuit design and saving the hardware cost.
Description
Technical Field
The invention relates to the field of digital optical fiber repeaters of wireless communication, in particular to a method and a System for testing time slot power of a GSM _ R (Global System for Mobile Communications-hierarchy) digital optical fiber repeater.
Background
The GSM _ R digital optical fiber repeater system consists of two radio frequency units, namely an AU (Access unit) and an RU (remote unit), wherein the AU and the RU are connected by digital optical fibers. And the AU is connected to an RRU (radio Remote Unit) radio frequency output port of the GSM _ R, and the RU transmits radio frequency signals to an antenna to realize signal coverage. The AU needs to realize power control on the received radio frequency signal from the RRU, and the receiving power of the AU is controlled not to exceed-15 dBfs.
The power calculation formula of the digital domain is
The GSM _ R air interface physical channels are in units of frames. A frame is 4.615ms in length and contains 8 slots, each of which is 0.577ms in length.
The GSM _ R signal source has various formats, such as full-slot signal, 1/2 signal, 1/8-slot signal. When the signal is in the full time slot, the signal is sent out in 8 time slots of a frame of GSM _ R; when 1/2 signals, only 4 time slots of a frame of GSM _ R are signaled, and the other 4 time slots are signaled to be null; at time slot 1/8, only 1 time slot of a frame of GSM _ R is signaled, and the other 7 time slots are signaled as null.
Disclosure of Invention
Aiming at the signal source of the GSM _ R in the prior art, the signal source has three signal source formats of full time slot, 1/2 time slot and 1/8 time slot, so that the AU of the GSM _ R digital optical fiber repeater needs to have the function of testing the time slot power of the three signal source formats at the same time. The invention aims to design a new power test method and a new power test system by utilizing a CPU and an FPGA in a GSM _ R system AU, and the method and the system can simultaneously and compatibly support time slot power test of three signal source formats of GSM _ R.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a GSM _ R digital optical fiber repeater power test method is characterized in that: a dual-channel power test Module is designed in an FPGA chip of an AU system, and the power test Module reports the tested power information to a CPU through a LocalBuss Module to calculate the transceiving digital domain power of the AU.
The power test module consists of a CH0/CH1 channel selection module, a multiplier, an adder, a data storage RAM and a power test control module;
the CH0/CH1 channel selection module selects one path of GSM _ R signal source of CH0 and CH1 to carry out power test according to the control signal Port output by the power test module;
CH0 outputs to CH if Port is 2' b 01;
CH1 outputs to CH if Port is 2' b 10;
the I/Q signal outputs a signal SUM I + Q through a multiplier and an adder; the SUM signal is output to a write input port of the RAM and a power test control module through an absolute value, SUM _ ABS ═ ABS (SUM).
Defining a SYNC signal in the power test module, and negating the SYNC along with each FPGA clock period signal in a frame period; the function of the SYNC signal is to distinguish between RAM reads and writes when power is accumulated.
The power test module comprises the following working steps:
when SYNC is equal to 1, the power test control module controls the SUM _ ABS signal to continuously write in a RAM unit (RAM _ WR is SUM _ ABS) and read out data from the RAM unit in one frame period;
step two, defining a Power variable (Power _ tmp) in the Power test control module:
when SYNC is equal to 0, Power _ tmp is Power _ tmp + SUM _ ABS if data from the start of a frame to the consecutive write RAM is less than M (M ═ N/2);
step three, when SYNC is equal to 0, if the data from the frame start to the continuous writing RAM is more than or equal to M, Power _ tmp is Power _ tmp-RAM _ RD (RAM _ RD is the data read from the RAM);
step four, when SYNC is equal to 1, if the data from the frame start to the continuous writing RAM is more than or equal to M, Power _ tmp is Power _ tmp + RAM _ WR (RAM _ WR is the data written into the RAM);
and step five, defining a Power statistic intermediate signal Power _ m in the Power test control module, wherein the Power _ m is assigned to be 0 at the beginning of each frame. It is judged from the beginning of each frame whether Power _ tmp is greater than Power _ m,
if Power _ tmp is greater than Power _ m, assigning the Power _ tmp to the Power _ m;
if the Power _ tmp is less than or equal to the Power _ m, the value of the Power _ m is kept unchanged;
step six, the power test control module judges whether the ending time of one frame is reached according to the timer, and if the ending time of one frame is reached:
first, Power _ tmp is output to the Power _ out variable and then sent to the CPU over the Localbuss bus. CPU calculates formula according to digital domain power
Calculating the digital domain power;
and secondly, the value of the control signal Port is inverted and output according to bits, and the channel selection module is controlled to be switched to another channel to test the power of the digital domain.
Has the advantages that: the invention has the advantages of 2 advantages that,
1: the invention uses an algorithm and design, can be simultaneously suitable for power test of GSM _ R3 signal source (full time slot, 1/2 time slot, 1/8 time slot) formats, and makes the system design simpler.
2: the invention can accurately test the power of the transceiving channels of AU and RU only by utilizing redundant logic resources in the FPGA, thereby avoiding the power test by the traditional hardware circuit design and saving the hardware cost.
Drawings
Fig. 1 is a block diagram of a GSM _ R AU system according to an embodiment of the present invention.
Fig. 2 is a GSM _ R1/8 time slot diagram according to an embodiment of the invention.
Fig. 3 is a schematic diagram of relative sliding of GSM _ R power test time windows according to an embodiment of the present invention.
FIG. 4 is a block diagram of a PowerMeter system according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples.
The embodiment realizes a method and a system for testing the power of a GSM _ R digital optical fiber repeater by using a CPU and an FPGA in an AU system. Fig. 1 is a system block diagram of an AU. As shown in fig. 1, in this embodiment, a dual-channel power test Module (PowerMeter) is designed inside an FPGA chip of the AU, and the PowerMeter Module reports the tested power information to the CPU through a LocalBuss Module to calculate the transmit-receive digital domain power of the AU.
As shown in fig. 2, when the GSM signal source operates in the 1/8 time slot state, only one time slot in a frame is signaled.
The working principle of the embodiment is to design a power statistics time window inside the PowerMeter module, and the time length of the time window is less than the length of one time slot (0.577 ms).
In the embodiment, the sampling rate of the I/Q data is 30.72MHz, 65536 data are counted by one time window, and the time length of the time window is 2.133 us.
The time window is periodically and circularly slid within a frame time length, and the maximum value of the test power of a time window length within a frame is found.
Fig. 3 is a relative diagram of time window sliding. The power test method is also suitable for power test of full time slot and 1/2 time slot signals.
The PowerMeter power statistic module mainly comprises a CH0/CH1 channel selection module, a multiplier, an adder, a data storage RAM and a power test control module. The system framework is shown in fig. 4.
The function of the CH0/CH1 channel selection module is to select one of the GSM _ R signal sources CH0 and CH1 for power test according to the control signal Port output by the power test control module.
CH0 outputs to CH if Port is 2' b 01;
if Port is 2' b10, CH1 outputs to CH.
The I/Q signal passes through a multiplier and an adder to output a signal SUM I + Q. The SUM signal is output to a write input port of the RAM and a power test control module through an absolute value, SUM _ ABS ═ ABS (SUM). The present invention represents 65536 data by N.
The power test control module realizes the following functions:
firstly, the method comprises the following steps: the CH0/CH1 channel selection module is controlled by the output control signal Port in a period of one frame time length (4.615ms), and the digital signals of CH0 and CH1 are time-division-multiplexed and selected for power test.
II, secondly: the digital domain power of the selected channel is accurately tested by relative sliding of the time windows during the test period of one frame.
A SYNC signal is defined inside the module, and the SYNC is negated with each FPGA clock cycle in one frame period. The function of the SYNC signal is to distinguish between RAM reads and writes when power is accumulated.
The power test control module has the following working procedures:
1: when SYNC is equal to 1, the power test control module controls the SUM _ ABS signal to continuously write into and read out from the RAM unit (RAM _ WR — SUM _ ABS) within one frame period;
2: a Power variable (Power _ tmp) is defined at the Power test control module.
When SYNC is equal to 0, Power _ tmp is Power _ tmp + SUM _ ABS if data from the start of a frame to the consecutive write RAM is less than M (M ═ N/2);
3: when SYNC is equal to 0, Power _ tmp is Power _ tmp-RAM _ RD (RAM _ RD is data read out from RAM) if data from the start of a frame to the continuous writing RAM is equal to or greater than M;
4: when SYNC is equal to 1, Power _ tmp is Power _ tmp + RAM _ WR (RAM _ WR is data written to RAM) if data from the start of a frame to the continuous writing RAM is equal to or greater than M;
5: a Power statistic intermediate signal Power _ m is defined in the Power test control module, and the value of the Power _ m is set to 0 at the beginning of each frame. It is judged from the beginning of each frame whether Power _ tmp is greater than Power _ m,
if Power _ tmp is greater than Power _ m, assigning the Power _ tmp to the Power _ m;
if the Power _ tmp is less than or equal to the Power _ m, the value of the Power _ m is kept unchanged;
6: the power test control module judges whether the ending time of one frame is reached or not according to the timer, and if the ending time of one frame is reached:
first, Power _ tmp is output to the Power _ out variable and then sent to the CPU over the Localbuss bus. CPU calculates formula according to digital domain power
The digital domain power is calculated.
And secondly, the value of the control signal Port is inverted and output according to bits, and the channel selection module is controlled to be switched to another channel to test the power of the digital domain.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent change and modification made to the above embodiment according to the technical spirit of the present invention by those skilled in the art can be still within the protection scope of the present invention without departing from the technical scope of the present invention.
Claims (4)
1. A GSM _ R digital optical fiber repeater power test method is characterized in that: designing a dual-channel power test Module in an FPGA chip of an AU system, reporting the tested power information to a CPU (central processing unit) through a LocalBuss Module by the power test Module, and calculating the transceiving digital domain power of the AU;
defining a SYNC signal in the power test module, and negating the SYNC along with each FPGA clock period signal in a frame period; the function of the SYNC signal is to distinguish the read and write of the RAM when the power is accumulated;
designing a power statistical time window in the power test module, wherein the time length of the time window is less than the length of a time slot;
the power test module comprises the following working steps:
when SYNC is equal to 1, the power test control module controls the SUM _ ABS signal to be continuously written into a RAM unit RAM _ WR (random access memory) (SUM _ ABS) and read out the signal from the RAM unit in one frame period; the I/Q signal outputs a signal SUM I + Q through a multiplier and an adder; the SUM signal is output to a write input port of the RAM and a power test control module through an absolute value, and SUM _ ABS (ABS) (SUM); RAM _ WR is data written to RAM;
step two, defining a Power variable Power _ tmp in the Power test control module:
when SYNC is equal to 0, if the data from the frame start to the continuous writing RAM is less than M, M is N/2, Power _ tmp is Power _ tmp + SUM _ ABS;
step three, when SYNC is equal to 0, if the data from the frame start to the continuous writing RAM is more than or equal to M, Power _ tmp is equal to Power _ tmp-RAM _ RD; RAM _ RD is data read out from RAM;
step four, when SYNC is equal to 1, if the data from the frame start to the continuous writing RAM is more than or equal to M, Power _ tmp is equal to Power _ tmp + RAM _ WR;
defining a Power statistic intermediate signal Power _ m in the Power test control module, judging whether Power _ tmp is larger than Power _ m from the beginning of a frame,
if Power _ tmp is greater than Power _ m, assigning the Power _ tmp to the Power _ m;
if the Power _ tmp is less than or equal to the Power _ m, the value of the Power _ m is kept unchanged;
step six, the power test control module judges whether the ending time of one frame is reached according to the timer, and if the ending time of one frame is reached:
firstly, outputting the Power _ m to a Power _ out variable, and then sending the variable to a CPU (central processing unit) through a Localbus; CPU calculates formula according to digital domain power
Calculating the digital domain power;
and secondly, the value of the control signal Port is inverted and output according to bits, and the channel selection module is controlled to be switched to another channel to test the power of the digital domain.
2. The GSM _ R digital optical fiber repeater power test method according to claim 1, characterized in that:
the power test module consists of a CH0/CH1 channel selection module, a multiplier, an adder, a data storage RAM and a power test control module;
the CH0/CH1 channel selection module selects one of the GSM _ R signal sources of CH0 and CH1 to carry out power test according to the control signal Port output by the power test control module;
CH0 outputs to CH if Port is 2' b 01;
CH1 outputs to CH if Port is 2' b 10;
the I/Q signal outputs a signal SUM I + Q through a multiplier and an adder; the SUM signal is output to a write input port of the RAM and a power test control module through an absolute value, SUM _ ABS ═ ABS (SUM).
3. The GSM _ R digital optical fiber repeater power test method according to claim 2, characterized in that:
the CH0/CH1 channel selection module is controlled by the output control signal Port with the one-frame time length of 4.615ms as a period, and the digital signals of CH0 and CH1 are selected in a time division multiplexing mode to carry out power test.
4. The GSM _ R digital optical fiber repeater power test method according to claim 2, characterized in that:
the digital domain power of the selected channel is accurately tested by relative sliding of the time windows during the test period of one frame.
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| JP4083444B2 (en) * | 2001-11-29 | 2008-04-30 | 富士通株式会社 | Optical transmission system and optical transmission method using Raman amplification |
| CN101296041B (en) * | 2007-04-25 | 2012-05-23 | 京信通信***（中国）有限公司 | Optical fiber transmission repeater and largely dynamic optical receiving-transmitting module |
| CN201742417U (en) * | 2010-07-07 | 2011-02-09 | 深圳国人通信有限公司 | Multi-mode digital optical fiber repeater as well as near-end machine, far-end machine and coverage system thereof |
| CN101977392A (en) * | 2010-10-26 | 2011-02-16 | 三维通信股份有限公司 | Method for detecting input and output power of digital repeater |
| CN102368867A (en) * | 2011-11-16 | 2012-03-07 | 三维通信股份有限公司 | Automatic frequency-selecting GSM (Global System for Mobile Communication) digital optical fiber repeater and realizing method thereof |
| CN102447479A (en) * | 2011-11-22 | 2012-05-09 | 福建邮科通信技术有限公司 | Automatic frequency-selecting technology applied to GSM digital repeater |
| CN102625327B (en) * | 2012-03-09 | 2016-07-06 | 奥维通信股份有限公司 | Digital intermediate frequency optical fiber repeater frequency automatic tracking method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201210678Y (en) * | 2008-06-12 | 2009-03-18 | 洪杰星 | Railway GSM-R digital optical fiber repeater station communication system |
| CN102625435A (en) * | 2012-03-30 | 2012-08-01 | 杭州畅鼎科技有限公司 | Automatic gain control (AGC) device for global system for mobile communication (GSM) digital optical fiber frequency-selecting repeater and quick adaptive time slot method for AGC device |
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