CN108155101A - A kind of stacking nano wire and its manufacturing method - Google Patents
A kind of stacking nano wire and its manufacturing method Download PDFInfo
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- CN108155101A CN108155101A CN201711406301.4A CN201711406301A CN108155101A CN 108155101 A CN108155101 A CN 108155101A CN 201711406301 A CN201711406301 A CN 201711406301A CN 108155101 A CN108155101 A CN 108155101A
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- 239000002070 nanowire Substances 0.000 title claims abstract description 269
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 149
- 239000004065 semiconductor Substances 0.000 claims abstract description 146
- 239000000758 substrate Substances 0.000 claims abstract description 131
- 238000000034 method Methods 0.000 claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 15
- 230000001590 oxidative effect Effects 0.000 claims abstract description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 12
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 229910005898 GeSn Inorganic materials 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 235000007164 Oryza sativa Nutrition 0.000 claims description 5
- 235000012149 noodles Nutrition 0.000 claims description 5
- 235000009566 rice Nutrition 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000002178 crystalline material Substances 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- 230000008569 process Effects 0.000 description 20
- 229910052732 germanium Inorganic materials 0.000 description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 12
- 238000002360 preparation method Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 239000002210 silicon-based material Substances 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 241000209094 Oryza Species 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000035800 maturation Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
Nano wire and its manufacturing method are stacked the invention discloses a kind of, including：Semiconductor substrate is provided；Stacking nano wire is prepared on the semiconductor substrate；The deposited semiconductor film on the stacking nano wire, wherein, the first semi-conducting material of the Semiconductor substrate is differed with the second semi-conducting material of the semiconductive thin film；Oxidizing annealing and the oxide of removal generation are carried out to the stacking nano wire, the semiconductor atom in the semiconductive thin film is promoted to diffuse into the stacking nano wire, forms target nano wire.Apparatus and method for provided by the invention, to solve the technical issues of electrons and holes mobility is low existing for the silicon nanowires prepared on a silicon substrate in the prior art.Realize the method prepared on a semiconductor substrate with the nano wire of substrate different materials.
Description
Technical field
The present invention relates to semiconductor applications more particularly to a kind of stacking nano wire and its manufacturing methods.
Background technology
In past 40 years, the size of device is less and less, in order to solve smaller size of demand, new device architecture
More and more studied.Wherein, nanometer Wiring technology, which is generally considered, can push the scale smaller of CMOS until the limit
Technique.A large amount of research is concentrated on the basis of traditional device architecture, and different technique and material innovation are introduced and received
To improve the electric property of device in rice noodles.
Currently existing nano wire manufacturing process, comparative maturity is silicon substrate preparation process, often on a silicon substrate
Silicon nanowires is prepared, and the electrons and holes mobility of silicon nanowires is relatively weak.
That is, there are the low skills of electrons and holes mobility for the silicon nanowires prepared on a silicon substrate in the prior art
Art problem.
Invention content
The present invention is solved and is made on a silicon substrate in the prior art by providing a kind of stacking nano wire and its manufacturing method
The technical issues of electrons and holes mobility is low existing for standby silicon nanowires.
On the one hand, in order to solve the above technical problems, the embodiment provides following technical solutions：
A kind of manufacturing method of nano wire, including：
Semiconductor substrate is provided；
Stacking nano wire is prepared on the semiconductor substrate；
The deposited semiconductor film on the stacking nano wire, wherein, the first semi-conducting material of the Semiconductor substrate
It is differed with the second semi-conducting material of the semiconductive thin film；
Oxidizing annealing and the oxide of removal generation are carried out to the stacking nano wire, promoted in the semiconductive thin film
Semiconductor atom diffuses into the stacking nano wire, forms target nano wire.
Optionally, the Semiconductor substrate is silicon substrate；The semiconductive thin film is SiGe film or Ge films；The rush
The semiconductor atom in the semiconductive thin film is made to diffuse into the stacking nano wire, forms target nano wire, including：Promote
Ge atoms permeatings in the semiconductive thin film enter the stacking nano wire, form SiGe nano wires or Ge nano wires.
Optionally, second semi-conducting material is non-crystalline material, monocrystal material or polycrystalline material.
Optionally, it is described to prepare stacking nano wire on the semiconductor substrate, including：The Semiconductor substrate is etched,
The fin structure with notch configuration is formed on the semiconductor substrate；The side of false grid and false grid is formed on the fin structure
Wall；It is etched on the fin structure and grows source-drain area material, form source region and drain region, wherein, the source-drain area material point
Not Wei Yu the false grid both sides；The false grid of removal；The fin structure is aoxidized, and removes the oxide that oxidation is formed, forms heap
Folded nano wire.
Optionally, the quantity of the notch configuration on the fin structure is corresponding with the radical for stacking nano wire.
Optionally, it is described to be etched on the fin structure and grow source and drain when the Semiconductor substrate is adulterated for p-type
Area's material, including：It is etched on the fin structure and grows source-drain area material, wherein, the lattice of the source-drain area material is normal
Number is smaller than the lattice constant of the target nanowire channel area material；It is described in institute when the Semiconductor substrate is n-type doping
It states and source-drain area material is etched and grown on fin structure, including：It is etched on the fin structure and grows source-drain area material,
In, the lattice constant of the source-drain area material is bigger than the lattice constant of the target nanowire channel area material.
Optionally, when the Semiconductor substrate is adulterated for p-type, the target nano wire is Si1-xGexIt is described during nano wire
It is etched on the fin structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material
Material, wherein, the source-drain area material is Si, SiC or Si1-yGey, wherein, x and y are natural number, x>y；When the semiconductor serves as a contrast
Bottom is adulterated for p-type, described to be etched on the fin structure and grow source-drain area material when the target nano wire is Ge nano wires
Material, including：Etched on the fin structure and grow source-drain area material, wherein, the source-drain area material for Si, SiGe or
SiC；When the Semiconductor substrate is n-type doping, the target nano wire is Si1-xGexIt is described in the fin during nano wire
It is etched in structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, institute
Source-drain area material is stated as Si1-yGey, wherein, x and y are natural number, x<y；When the Semiconductor substrate be n-type doping, the mesh
It is described to be etched on the fin structure and grow source-drain area material when marking nano wire as Ge nano wires, including：In the fin
It is etched in structure and grows source-drain area material, wherein, the source-drain area material is GeSn or III-V compound semiconductor material.
Optionally, it is described that oxidizing annealing is carried out to the stacking nano wire, including：The stacking is received in dry oxygen atmosphere
Rice noodles are aoxidized, and are annealed in the atmosphere mixed in nitrogen or nitrogen hydrogen to the stacking nano wire, wherein, it is right
The fusing point for stacking the temperature that nano wire is aoxidized and annealed and being below SiGe, wherein, the stacking nano wire is carried out
It aoxidizes and is annealed alternately to the stacking nano wire.
Optionally, the material of the target nano wire and atomic concentration, the stacking in second of semiconductive thin film
The diameter of nano wire and the technological parameter for carrying out oxidizing annealing to the stacking nano wire are related.
Optionally, it after the formation target nano wire, further includes：The depositing gate electrode material on the target nano wire,
Form grid.
On the other hand, a kind of stacking nano wire is provided, including：
Semiconductor substrate,
Target nano wire is prepared on the semiconductor substrate as channel region, wherein, the first of the Semiconductor substrate
Second semi-conducting material of semi-conducting material and the target nano wire differs；
Source region and drain region, the source region and the drain region are located at the both sides of the target nano wire respectively；
Grid, Deposit contact is in the target nano wire.
Optionally, the Semiconductor substrate is silicon substrate；The target nano wire is SiGe nano wires or Ge nano wires.
Optionally, being prepared in the Semiconductor substrate has fin structure；The target nano wire is located at the fin structure
On.
Optionally, the target nano wire includes more linear channel regions.
Optionally, the grid material of the grid is filled between described more linear channel regions.
Optionally, when the Semiconductor substrate is n-type doping, the crystalline substance of the material in the material of the source region and the drain region
Lattice constant of the lattice constant than the target nanowire channel area material is small；When the Semiconductor substrate is adulterated for p-type, institute
The lattice constant of the material of source region and the material in the drain region is stated than the lattice constant of the target nanowire channel area material
Greatly.
Optionally, when the Semiconductor substrate is n-type doping, the target nano wire is Si1-xGexIt is described during nano wire
The material of source region and the material in the drain region are Si, SiC or Si1-yGey, wherein, x and y are natural number, x>y；It is partly led when described
Body substrate is n-type doping, and when the target nano wire is Ge nano wires, the material in the material of the source region and the drain region is
Si, SiGe or SiC；When the Semiconductor substrate is adulterated for p-type, the target nano wire is Si1-xGexDuring nano wire, the source
The material in area and the material in the drain region are Si1-yGey, wherein, x and y are natural number, x<y；When the Semiconductor substrate is P
Type adulterates, and when the target nano wire is Ge nano wires, the material in the material of the source region and the drain region is GeSn or three or five
Group iii v compound semiconductor material.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages：
Nano wire provided by the embodiments of the present application and its manufacturing method first prepare stacking nano wire on a semiconductor substrate,
The different semiconductive thin film of material of deposition and the Semiconductor substrate on nano wire is stacked again, and will by oxidizing annealing
Semiconductor atom in semiconductive thin film diffuses into stacking nano wire, so as to fulfill being prepared on a semiconductor substrate with substrate not
With the nano wire of material, a kind of method that can prepare non-silicon material nano wire on a silicon substrate is provided, maturation can be used
The corresponding preparation process of silicon substrate, can be prepared by the nano wire (Ge nanoline or germanium silicon nanowires) of non-silicon material, so as to
Improve the mobility of electrons and holes in nano wire.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only the embodiment of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to the attached drawing of offer other
Attached drawing.
Fig. 1 is the flow chart of the manufacturing method of nano wire in the embodiment of the present application；
Fig. 2 is the process flow chart one that nano wire is manufactured in the embodiment of the present application；
Fig. 3 is the process flow chart two that nano wire is manufactured in the embodiment of the present application；
Fig. 4 is the process flow chart three that nano wire is manufactured in the embodiment of the present application；
Fig. 5 is the process flow chart four that nano wire is manufactured in the embodiment of the present application；
Fig. 6 is the process flow chart five that nano wire is manufactured in the embodiment of the present application；
Fig. 7 is the process flow chart six that nano wire is manufactured in the embodiment of the present application；
Fig. 8 is the process flow chart seven that nano wire is manufactured in the embodiment of the present application；
Fig. 9 is the process flow chart eight that nano wire is manufactured in the embodiment of the present application；
Figure 10 is the process flow chart nine that nano wire is manufactured in the embodiment of the present application；
Figure 11 is the process flow chart ten that nano wire is manufactured in the embodiment of the present application；
Figure 12 is the structure chart that nano wire is manufactured in the embodiment of the present application.
Specific embodiment
The embodiment of the present application is solved in the prior art by providing a kind of manufacturing method for stacking nano wire in silicon substrate
The technical issues of electrons and holes mobility is low existing for the silicon nanowires of upper preparation.Realize prepare on a semiconductor substrate with
The method of the nano wire of substrate different materials.
In order to solve the above technical problems, the general thought that the embodiment of the present application provides technical solution is as follows：
The present embodiment provides a kind of manufacturing method of nano wire, including：
Semiconductor substrate is provided；
Stacking nano wire is prepared on the semiconductor substrate；
The deposited semiconductor film on the stacking nano wire, wherein, the first semi-conducting material of the Semiconductor substrate
It is differed with the second semi-conducting material of the semiconductive thin film；
Oxidizing annealing and the oxide of removal generation are carried out to the stacking nano wire, promoted in the semiconductive thin film
Semiconductor atom diffuses into the stacking nano wire, forms target nano wire.
Nano wire provided by the embodiments of the present application and its manufacturing method, by preparing stacking nanometer on a semiconductor substrate
Line, then the different semiconductive thin film of material of deposition and the Semiconductor substrate on nano wire is stacked, and pass through oxidation and move back
Semiconductor atom in semiconductive thin film is diffused into stacking nano wire by fire, so as to fulfill preparing and serving as a contrast on a semiconductor substrate
The nano wire of bottom different materials provides a kind of method that can prepare non-silicon material nano wire on a silicon substrate.
In order to better understand the above technical scheme, above-mentioned technical proposal is carried out below in conjunction with specific embodiment
It is described in detail, it should be understood that the specific features in the embodiment of the present invention and embodiment are to the detailed of technical scheme
Illustrate rather than the restriction to technical scheme, in the absence of conflict, in the embodiment of the present application and embodiment
Technical characteristic can be combined with each other.
Embodiment one
In the present embodiment, a kind of manufacturing method for stacking nano wire is provided, as shown in Figure 1, the method includes：
Step S101, provides Semiconductor substrate；
Step S102 prepares stacking nano wire on the semiconductor substrate；
Step S103, the deposited semiconductor film on the stacking nano wire, wherein, the first the half of the Semiconductor substrate
Conductor material and the second semi-conducting material of the semiconductive thin film differ；
Step S104 carries out oxidizing annealing and the oxide of removal generation to the stacking nano wire, promotes described partly to lead
Semiconductor atom in body thin film diffuses into the stacking nano wire, forms target nano wire.
It should be noted that the technique for preparing device on a silicon substrate is comparative maturity, therefore the prior art uses mostly
Silicon substrate prepares nano wire, however, through research, metal oxide semiconductor field-effect of the germanium as sub-10 nano technology node
The potential raceway groove of transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) MOSFET element
Material has the mobility of higher electrons and holes compared with silicon, better device performance can be brought as channel region material,
If however, Ge nanoline is prepared in germanium substrate, it is necessary to change the silicon preparation process of existing maturation, introduce many new works
Skill, for present inventor by creative research, germanium nanometer can be prepared on a silicon substrate by providing one kind in the present embodiment
The new process of line or germanium silicon nanowires, it is very compatible with existing silicon technology.
In the embodiment of the present application, the Semiconductor substrate is silicon substrate；The semiconductive thin film is SiGe film or Ge
Film；The semiconductor atom promoted in the semiconductive thin film diffuses into the stacking nano wire, forms target nanometer
Line, including：The Ge atoms permeatings in the semiconductive thin film is promoted to enter the stacking nano wire, form SiGe nano wires or Ge
Nano wire.
Certainly, in specific implementation process, method provided in this embodiment can also be used to prepare germanium silicon in germanium substrate
Nano wire, alternatively, preparing silicon nanowires in gallium arsenide substrate, this is not restricted, also will not enumerate.
In the following, using the Semiconductor substrate as Si substrates, the target nano wire is SiGe nano wires or Ge nano wires are
The detailed step of the application providing method is discussed in detail with reference to Fig. 1-11 for example, wherein, Fig. 2-Figure 11 is followed successively by manufacture nano wire
During process sequence diagram by elder generation after：
First, step S101 is performed, Semiconductor substrate 1 is provided.
In the embodiment of the present application, the type of device prepared as needed is different, and the Semiconductor substrate can be that N-type is mixed
Miscellaneous substrate or the substrate of p-type doping, this is not restricted.
In specific implementation process, the Semiconductor substrate can be body silicon substrate or SOI substrate, herein not
It is restricted.
Then, step S102 is performed, is prepared in the Semiconductor substrate 1 and stacks nano wire 2.
In the embodiment of the present application, as illustrated in figs. 2-7, the preparation method of the stacking nano wire can be：
It please refers to Fig.2, first etches the Semiconductor substrate 1, band recess shown in Fig. 2 is formed in the Semiconductor substrate 1
The fin structure 3 (Fin) of structure 31 (notch).Wherein, right part of flg and the view directions of left hand view are vertical in Fig. 2, right part of flg and
Left hand view is the structure chart of same processing step.
Specifically, the technique of the etching generation fin structure shown in Fig. 2 can be divided into three steps：The first step, respectively to
Anisotropic etch generates fin structure 3；Second step, plasma protection fin structure surface；Third walks, isotropic plasma
Etching forms notch configuration 31.In specific implementation process, above-mentioned etch step can be repeated several times, to generate multiple recess knots
Structure 31.
It should be noted that the quantity of the notch configuration 31 formed on the fin structure 3 in above-mentioned etch step with
The radical for the stacking nano wire being subsequently generated corresponds to.For example, 3 notch configurations are generated when fin etches as shown in Figure 2
31, then it is follow-up to generate 3 nano wires as shown in Figure 8.
It please refers to Fig.3, after etching generates the fin structure 3 with notch configuration 31, is isolated between fin structure 3
The deposition of material 4.Shallow-trench isolation (Shallow Trench Isolation) STI techniques specifically may be used in the fin knot
Shallow-trench isolation is formed between structure 3.Wherein, right part of flg and the view directions of left hand view are vertical in Fig. 3, and right part of flg and left hand view are same
The structure chart of one processing step.
Optionally, the isolated material 4 is SiN, Si3N4、SiO2Or SiCO.
It please refers to Fig.4 and Fig. 5, the side wall 6 of false grid 5 and false grid 5 is formed on the fin structure 3.
The processing step of the specific side wall 6 for forming false grid 5 and false grid 5 is, as shown in figure 4, first depositing the grid material of false grid 5
Material, then etches the grid material and forms false grid 5, the etching may be used wet etching or dry etching, not make herein
Limitation.Then, it as shown in figure 5, first depositing the spacer material of side wall 6, then etches the spacer material and forms side wall 6, it is described
Wet etching or dry etching may be used in etching, and this is not restricted.Wherein, right part of flg and left hand view regard in Fig. 4 and Fig. 5
Angular direction is vertical, and the right part of flg and left hand view in each figure are the structure chart of same processing step.
In the embodiment of the present application, the false grid 5 can be metal material or polycrystalline silicon material, and the metal material can be with
For W, certainly, the metal material may be Al, Cu or TiAl, and this is not restricted.
Fig. 6 is please referred to, etched on the fin structure 3 and grows source-drain area material, forms source region 71 and drain region 72,
In, the source-drain area material is located at the both sides of the false grid 5 respectively.
In the embodiment of the present application, the source region and the drain region can first be etched using dry etching or wet etching
Go out groove, source-drain area material is then grown by regioselectivity epitaxy technique again, this is not restricted.
Specifically, in order to improve the performance of the device of preparation, the type of the source-drain area material of growth need to set with
The type of the doping type of Semiconductor substrate 1 and the target nano wire of preparation is related.Details are as follows：
When the Semiconductor substrate 1 is adulterated for p-type, answered in order to which source region and drain region is made to provide to open for nanowire channel area
Power so as to improve the mobility of channel region carrier, sets the lattice constant of the source-drain area material than the target nanometer
The lattice constant of wire channel area material is small；
It, should in order to which source region and drain region is made to provide pressure for nanowire channel area when the Semiconductor substrate 1 is n-type doping
Power so as to improve the mobility of channel region carrier, sets the lattice constant of the source-drain area material than the target nanometer
The lattice constant of wire channel area material is big.
Further：
When the Semiconductor substrate is adulterated for p-type, the target nano wire is Si1-xGexIt is described described during nano wire
It is etched on fin structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material,
In, the source-drain area material is Si, SiC or Si1-yGey, wherein, x and y are natural number, x>y；
It is described in the fin knot when the Semiconductor substrate is adulterated for p-type, and the target nano wire is Ge nano wires
It is etched on structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, it is described
Source-drain area material is Si, SiGe or SiC；
When the Semiconductor substrate is n-type doping, the target nano wire is Si1-xGexIt is described described during nano wire
It is etched on fin structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material,
In, the source-drain area material is Si1-yGey, wherein, x and y are natural number, x<y；
It is described in the fin knot when the Semiconductor substrate is n-type doping, and the target nano wire is Ge nano wires
It is etched on structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, it is described
Source-drain area material is GeSn or III-V compound semiconductor material.
Then, Fig. 7 is please referred to, false grid are removed, in order to subsequently prepare stacking nano wire.The technique of the specific false grid of removal can
To use dry or wet etch technique, this is not restricted.Wherein, right part of flg and the view directions of left hand view are vertical in Fig. 6,
Right part of flg and left hand view are the structure chart of false grid removal step.
Fig. 8 is please referred to, aoxidizes the fin structure 3, and removes the oxide that oxidation is formed, is formed and stacks nano wire 2.
In specific implementation process, the fin structure 3 is aoxidized and is removed the setting of the technological parameter of oxide
It is related to the diameter of stacking nano wire 2 being subsequently generated.For example, the oxidization time the long, the stacking nano wire 2 generated
Diameter is smaller, therefore the diameter of stacking nano wire 2 that needs can be controlled to generate by setting the technological parameter of oxidation.
As shown in figure 8, after by aoxidizing and removing oxide, on the fin structure 3, the position of recess is by oxidation removal
Fall, leave more linear stacking nano wires 2.
Subsequently, step S103 is performed, as shown in figure 9, the deposited semiconductor film 8 on the stacking nano wire 2,
In, the first semi-conducting material of the Semiconductor substrate 1 and the second semi-conducting material of the semiconductive thin film 8 differ.
In the embodiment of the present application, the semiconductive thin film 8 is germanium film or SiGe film, and this is not restricted, described half
Second semi-conducting material of conductor thin film 8 is non-crystalline material, monocrystal material or polycrystalline material, is not also restricted herein.
As described in Figure 9,8 uniform fold of semiconductive thin film is deposited on the stacking nano wire 2.
Then, step S104 is performed, as shown in Figure 10, the stacking nano wire 2 is aoxidized and is annealed, and gone
Except the oxide of generation, the semiconductor atom in the semiconductive thin film 8 is promoted to diffuse into the stacking nano wire 2, is formed
Target nano wire.
Specifically, it is described that oxidizing annealing is carried out to the stacking nano wire 2, including：
The stacking nano wire 2 is aoxidized in dry oxygen atmosphere, and the atmosphere mixed in nitrogen or nitrogen hydrogen
In anneal to the stacking nano wire 2, wherein, stacking nano wire 2 temperature that is aoxidized and annealed is below
The fusing point of SiGe, wherein, the stacking nano wire 2 is aoxidized and is annealed alternately to the stacking nano wire,
The germanium atom in the semiconductive thin film 8 to be promoted to diffuse into the stacking nano wire 2, in the stacking nano wire 2
Even distribution, and the silicon atom in the stacking nano wire 2 is promoted partly or entirely to be changed into the oxide of silicon, it forms SiGe and receives
Rice noodles or Ge nano wires.
It should be noted that the target nano wire ultimately produced is SiGe nano wires or Ge nano wires and most
The determinant of the content of germanium includes in the target nano wire generated afterwards：
Atomic concentration in the semiconductive thin film 8, the diameter for stacking nano wire 2 and to the stacking nano wire 2 into
The technological parameter of row oxidizing annealing.
For example, the germanium atom concentration in the semiconductive thin film 8 is higher, in the situation that other process conditions are constant
Under, the germanium atom content of the target nano wire of generation is higher；The diameter for stacking nano wire 2 is bigger, in other process conditions
In the case of constant, the germanium atom content of the target nano wire of generation is lower；Oxidizing annealing is carried out to the stacking nano wire 2
Time is longer, and in the case where other process conditions are constant, the germanium atom content of the target nano wire of generation is higher；To the heap
The temperature that folded nano wire 2 carries out oxidizing annealing is higher, in the case where other process conditions are constant, the target nano wire of generation
Germanium atom content can be higher.
Further, after target nano wire is formed, as shown in figure 11, gate medium, grid are deposited on the target nano wire
Electrode material forms grid 9.The gate medium can be the high-g values such as HfO2, Al2O3, not be limited herein.
The gate electrode can be metal material or polycrystalline silicon material, and the metal material can be W, certainly, the gold
It may be Al, Cu or TiAl to belong to material, and this is not restricted.
So as to complete the manufacture of the nano wire.
Specifically, the manufacturing method of nano wire provided in this embodiment by preparing stacking nanometer on a semiconductor substrate
Line, then deposition and the different semiconductive thin film of material of the Semiconductor substrate on nano wire is stacked, and pass through oxidation and
Semiconductor atom in semiconductive thin film is diffused into stacking nano wire by annealing, so as to fulfill prepare on a semiconductor substrate with
The nano wire of substrate different materials.
Conceived based on same one side, present invention also provides devices prepared by the method using embodiment one, refer to implementation
Example two.
Embodiment two
In the present embodiment, as shown in figure 12, a kind of stacking nano wire is provided, including：
Semiconductor substrate 1201,
Target nano wire 1202 is prepared as channel region in the Semiconductor substrate 1201, wherein, the semiconductor lining
First semi-conducting material at bottom 1201 and the second semi-conducting material of the target nano wire 1202 differ；
Source region 1203 and drain region 1204, the source region 1203 and the drain region 1204 are located at the target nano wire respectively
1202 both sides；
Grid 1205, Deposit contact is in the target nano wire 1202.
In the embodiment of the present application, the Semiconductor substrate 1201 is silicon substrate；
The target nano wire 1202 is SiGe nano wires or Ge nano wires.
In the embodiment of the present application, being prepared in the Semiconductor substrate 1201 has fin structure；The target nano wire
1202 are located on the fin structure.
In the embodiment of the present application, the target nano wire 1202 includes more linear channel regions.
In the embodiment of the present application, the grid material of the grid 1205 is filled between described more linear channel regions.
In the embodiment of the present application, when the Semiconductor substrate 1201 for p-type adulterate when, the material of the source region 1203 and
Lattice constant of the lattice constant of the material in the drain region 1204 than 1202 channel region material of target nano wire is small；
When the Semiconductor substrate 1201 is n-type doping, the material of the source region 1203 and the material in the drain region 1204
Lattice constant of the lattice constant of material than 1202 channel region material of target nano wire is big.
In the embodiment of the present application, when the Semiconductor substrate 1201 is adulterated for p-type, the target nano wire 1202 is
Si1-xGexDuring nano wire, the material of the source region 1203 and the material in the drain region 1204 are Si, SiC or Si1-yGey, wherein, x
With y be natural number, x>y；
When the Semiconductor substrate 1201 is adulterated for p-type, and the target nano wire 1202 is Ge nano wires, the source region
1203 material and the material in the drain region 1204 are Si, SiGe or SiC；
When the Semiconductor substrate 1201 is n-type doping, the target nano wire 1202 is Si1-xGexDuring nano wire, institute
The material of source region 1203 and the material in the drain region 1204 are stated as Si1-yGey, wherein, x and y are natural number, x<y；
When the Semiconductor substrate 1201 is n-type doping, and the target nano wire 1202 is Ge nano wires, the source region
1203 material and the material in the drain region 1204 are GeSn or III-V compound semiconductor material.
By the device that the embodiment of the present invention two is introduced, the prepared device of the method to implement the embodiment of the present invention one
Part, so based on the method that the embodiment of the present invention one is introduced, the affiliated personnel in this field can understand the concrete structure of the device
And deformation, so details are not described herein.
Technical solution in above-mentioned the embodiment of the present application, at least has the following technical effect that or advantage：
Nano wire provided by the embodiments of the present application and its manufacturing method first prepare stacking nano wire on a semiconductor substrate,
The different semiconductive thin film of material of deposition and the Semiconductor substrate on nano wire is stacked again, and will by oxidizing annealing
Semiconductor atom in semiconductive thin film diffuses into stacking nano wire, so as to fulfill being prepared on a semiconductor substrate with substrate not
With the nano wire of material, a kind of method that can prepare non-silicon material nano wire on a silicon substrate is provided, maturation can be used
The corresponding preparation process of silicon substrate, can be prepared by the nano wire (Ge nanoline or germanium silicon nanowires) of non-silicon material, so as to
Improve the mobility of electrons and holes in nano wire.Mobility channel is prepared on a silicon substrate using ripe silicon technology to receive
Rice noodles improve device performance, and compatible with existing silicon technology.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (17)
1. a kind of manufacturing method for stacking nano wire, which is characterized in that including：
Semiconductor substrate is provided；
Stacking nano wire is prepared on the semiconductor substrate；
The deposited semiconductor film on the stacking nano wire, wherein, the first semi-conducting material of the Semiconductor substrate and institute
The second semi-conducting material for stating semiconductive thin film differs；
The stacking nano wire is aoxidized and annealed, and removes the oxide of generation, promotes the semiconductive thin film
In semiconductor atom diffuse into the stacking nano wire, form target nano wire.
2. the method as described in claim 1, it is characterised in that：
The Semiconductor substrate is silicon substrate；
The semiconductive thin film is SiGe film or Ge films；
The semiconductor atom promoted in the semiconductive thin film diffuses into the stacking nano wire, forms target nanometer
Line, including：The Ge atoms permeatings in the semiconductive thin film is promoted to enter the stacking nano wire, form SiGe nano wires or Ge
Nano wire.
3. the method as described in claim 1, which is characterized in that second semi-conducting material is non-crystalline material, monocrystal material
Or polycrystalline material.
4. the method as described in claim 1, which is characterized in that it is described to prepare stacking nano wire on the semiconductor substrate,
Including：
The Semiconductor substrate is etched, forms the fin structure with notch configuration on the semiconductor substrate；
The side wall of false grid and false grid is formed on the fin structure；
It is etched on the fin structure and grows source-drain area material, form source region and drain region, wherein, the source-drain area material point
Not Wei Yu the false grid both sides；
The false grid of removal；
The fin structure is aoxidized, and removes the oxide that oxidation is formed, is formed and stacks nano wire.
5. method as claimed in claim 4, which is characterized in that the quantity of the notch configuration on the fin structure and the heap
The radical of folded nano wire corresponds to.
6. method as claimed in claim 4, it is characterised in that：
It is described to be etched on the fin structure and grow source-drain area material when the Semiconductor substrate is adulterated for p-type, packet
It includes：It is etched on the fin structure and grows source-drain area material, wherein, the lattice constant of the source-drain area material is than the mesh
The lattice constant for marking nanowire channel area material is small；
It is described to be etched on the fin structure and grow source-drain area material when the Semiconductor substrate is n-type doping, packet
It includes：It is etched on the fin structure and grows source-drain area material, wherein, the lattice constant of the source-drain area material is than the mesh
The lattice constant for marking nanowire channel area material is big.
7. method as claimed in claim 6, it is characterised in that：
When the Semiconductor substrate is adulterated for p-type, the target nano wire is Si1-xGexIt is described in the fin knot during nano wire
It is etched on structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, it is described
Source-drain area material is Si, SiC or Si1-yGey, wherein, x and y are natural number, x>y；
It is described on the fin structure when the Semiconductor substrate is adulterated for p-type, and the target nano wire is Ge nano wires
It etches and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, the source and drain
Area's material is Si, SiGe or SiC；
When the Semiconductor substrate is n-type doping, the target nano wire is Si1-xGexIt is described in the fin knot during nano wire
It is etched on structure and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, it is described
Source-drain area material is Si1-yGey, wherein, x and y are natural number, x<y；
It is described on the fin structure when the Semiconductor substrate is n-type doping, and the target nano wire is Ge nano wires
It etches and grows source-drain area material, including：It is etched on the fin structure and grows source-drain area material, wherein, the source and drain
Area's material is GeSn or III-V compound semiconductor material.
8. the method as described in claim 1-7 is any, which is characterized in that it is described to it is described stacking nano wire aoxidized and
Annealing, including：
The stacking nano wire is aoxidized in dry oxygen atmosphere, and to institute in the atmosphere mixed in nitrogen or nitrogen hydrogen
Stacking nano wire is stated to anneal, wherein, the temperature that the stacking nano wire is aoxidized and annealed is below the molten of SiGe
Point, wherein, the stacking nano wire is aoxidized and is annealed alternately to the stacking nano wire.
9. the method as described in claim 1-7 is any, which is characterized in that the material of the target nano wire and the semiconductor
Atomic concentration in film, the diameter for stacking nano wire and the technological parameter that carries out oxidizing annealing to the stacking nano wire are equal
It is related.
10. the method as described in claim 1-7 is any, which is characterized in that after the formation target nano wire, further include：
The depositing gate electrode material on the target nano wire forms grid.
11. a kind of stacking nano wire, which is characterized in that including：
Semiconductor substrate,
Target nano wire is prepared on the semiconductor substrate as channel region, wherein, the first the half of the Semiconductor substrate leads
Body material and the second semi-conducting material of the target nano wire differ；The crystal orientation of the Semiconductor substrate is received with the target
The crystal orientation of rice noodles is identical；
Source region and drain region, the source region and the drain region are located at the both sides of the target nano wire respectively；
Grid, Deposit contact is in the target nano wire.
12. nano wire as claimed in claim 11, it is characterised in that：
The Semiconductor substrate is silicon substrate；
The target nano wire is SiGe nano wires or Ge nano wires.
13. nano wire as claimed in claim 11, which is characterized in that being prepared in the Semiconductor substrate has fin structure；Institute
Target nano wire is stated to be located on the fin structure.
14. nano wire as claimed in claim 13, which is characterized in that the target nano wire includes more linear channel regions.
15. nano wire as claimed in claim 14, which is characterized in that be filled with the grid between described more linear channel regions
The grid material of pole.
16. nano wire as claimed in claim 11, it is characterised in that：
When the Semiconductor substrate is adulterated for p-type, the lattice constant of the material in the material of the source region and the drain region compares
The lattice constant of the target nanowire channel area material is small；
When the Semiconductor substrate is n-type doping, the lattice constant of the material in the material of the source region and the drain region compares
The lattice constant of the target nanowire channel area material is big.
17. nano wire as claimed in claim 16, it is characterised in that：
When the Semiconductor substrate is adulterated for p-type, the target nano wire is Si1-xGexDuring nano wire, the material of the source region and
The material in the drain region is Si, SiC or Si1-yGey, wherein, x and y are natural number, x>y；
When the Semiconductor substrate is p-type doping, when the target nano wire is Ge nano wires, the material of the source region and described
The material in drain region is Si, SiGe or SiC；
When the Semiconductor substrate is n-type doping, the target nano wire is Si1-xGexDuring nano wire, the material of the source region and
The material in the drain region is Si1-yGey, wherein, x and y are natural number, x<y；
When the Semiconductor substrate is n-type doping, and the target nano wire is Ge nano wires, the material of the source region and described
The material in drain region is GeSn or III-V compound semiconductor material.
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Application publication date: 20180612 |