CN108140354B - Liquid crystal display panel and correction method thereof - Google Patents

Liquid crystal display panel and correction method thereof Download PDF

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CN108140354B
CN108140354B CN201680061810.5A CN201680061810A CN108140354B CN 108140354 B CN108140354 B CN 108140354B CN 201680061810 A CN201680061810 A CN 201680061810A CN 108140354 B CN108140354 B CN 108140354B
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source bus
liquid crystal
source
crystal display
display panel
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CN108140354A (en
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下敷领文一
吉田壮寿
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

The liquid crystal display panel includes: a plurality of 1 st source drivers (35a) provided in the 1 st frame region (20a) and configured to supply a1 st display signal voltage to each of the associated plurality of source bus lines (14 s); and a plurality of 2 nd source drivers (35b) provided in the 2 nd frame region (20b) and respectively supplying the 2 nd display signal voltage to the associated plurality of source bus lines among the plurality of source bus lines. In each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines in a superimposed manner, and the respective polarities of the 1 st display signal voltage and the 2 nd display signal voltage do not change in each vertical scanning period.

Description

Liquid crystal display panel and correction method thereof
Technical Field
The present invention relates to a liquid crystal display panel and a method for correcting the same, and more particularly, to a large liquid crystal display panel for a high definition television and a method for correcting a disconnection of a source bus thereof. Here, unless otherwise specified, the liquid crystal display panel refers to a TFT type liquid crystal display panel.
Background
The applicant of the present application is engaged in the manufacture and sale of high-definition large-sized liquid crystal display panels. For example, in a large-sized high-definition liquid crystal display panel exceeding FHD such as 4K, 8K, etc., the charging capability required for a source driver (signal line driving circuit) that supplies a display signal voltage to a source bus line (signal line) may become large. In a high-definition and/or large-sized liquid crystal display panel, a driving method (hereinafter, referred to as a "double-sided input driving structure") may be employed in which source drivers are provided in respective frame regions on both sides of a display region of the liquid crystal display panel (for example, above and below the display region), and display signal voltages are input to respective source bus lines from the respective source drivers. The liquid crystal display panel having the both-side input driving structure has a high charging capability because 2 source drivers for driving the respective source bus lines are provided. Compared to a liquid crystal display panel having a driving method in which a source driver is provided in a frame region above or below a display region of the liquid crystal display panel and a display signal voltage is input from 1 source driver to each source bus line (in contrast to the above-described two-side input driving structure, this driving method is sometimes referred to as a "one-side input driving structure").
Patent document 1 discloses a liquid crystal display device having the above-described both-side input drive structure. According to the liquid crystal display device of patent document 1, when the source bus line is disconnected, display can be performed without any trouble even if correction is not performed.
Various studies have been made to improve the display quality of liquid crystal display panels. Each pixel of the liquid crystal display panel exhibits a luminance corresponding to the magnitude of a voltage applied to the liquid crystal layer. A pixel electrically exhibits a liquid crystal capacitance including a pixel electrode/a liquid crystal layer/a counter electrode, and the magnitude of a voltage applied to the pixel (liquid crystal layer) is expressed with reference to the potential of the counter electrode. The liquid crystal material is a dielectric and deteriorates when a dc voltage is applied for a long time. To prevent this, the voltage (electric field) applied to the liquid crystal layer is reversed in polarity (direction) every fixed time (referred to as "ac drive"). Frame inversion driving (or field inversion driving) has been employed in which the polarity (direction of an electric field) of a voltage applied to each pixel is inverted every vertical scanning period. The "vertical scanning period" refers to a period from when a certain scanning line (gate bus line) is selected to when the scanning line is selected again.
However, in a liquid crystal display panel for mass production, it is difficult to accurately match the absolute values of the voltages before and after the polarity inversion of the voltage, and the absolute value of the voltage slightly varies every time the polarity is inverted. As a result, when a still image is displayed, the luminance changes every time the polarity is inverted, and flicker (flicker) occurs in the display. Therefore, the following method has been adopted: flicker is reduced by utilizing the effect of spatially averaging the luminance of pixels due to the adjacent arrangement of pixels to which voltages of mutually opposite polarities are to be applied in the display region. A typical method thereof is a driving method in which the polarities of voltages applied to mutually adjacent pixels are inverted, and a state called "dot inversion" (sometimes also called "1-dot inversion driving") is realized. "dot" refers to a pixel.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 62-271574
Disclosure of Invention
Problems to be solved by the invention
The present inventors have found that, in the liquid crystal display device of patent document 1 having the double-side input drive structure, when 1-dot inversion driving is performed to improve display quality, a problem occurs in that the source driver generates excessive heat (problem 1). According to the research of the inventors of the present invention, the above problem 1 is caused by the reason that the liquid crystal display panel has the two-side input driving structure, which is not generated in the liquid crystal display panel having the one-side input driving structure. The details will be described later.
Further, according to the study of the inventors of the present invention, in the liquid crystal display device of patent document 1, when the source bus line is disconnected, the operation can be performed without correction, but the following problem (problem 2) may occur: when the source bus lines are disconnected, a dark portion is generated in the display region of the liquid crystal display panel. Problem 2 is particularly noticeable in a high-definition and/or large-sized liquid crystal display panel, which is caused by insufficient charging capability of the source driver. The details will be described later.
An object of the present invention is to solve at least the above problem 1, and an object thereof is to provide a liquid crystal display panel in which heat generation of source drivers is suppressed and charging capability required for each source driver is reduced, and a correction method thereof.
Means for solving the problems
A liquid crystal display panel according to an embodiment of the present invention includes: a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns; a plurality of transistors connected to any 1 of the plurality of pixels, respectively; a plurality of gate bus lines extending in a row direction and connected to any one of the plurality of transistors; a plurality of source bus lines extending in the column direction and connected to any one of the plurality of transistors; a plurality of 1 st source drivers provided in a1 st frame region above a display region divided by the plurality of pixels, for supplying a1 st display signal voltage to each of the plurality of source bus lines associated therewith; and a plurality of 2 nd source drivers provided in a2 nd frame region below the display region, each of the 2 nd source drivers supplying a2 nd display signal voltage to a corresponding one of the plurality of source bus lines, wherein the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines in a superimposed manner in each vertical scanning period, and the polarities of the 1 st display signal voltage and the 2 nd display signal voltage do not change in each vertical scanning period.
In one embodiment, the plurality of source bus lines include 1 st source bus lines arranged corresponding to the respective pixel columns, the transistors connected to 2 pixels adjacent to each other in the row direction are connected to the 1 st source bus lines different from each other, and polarities of the 1 st display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period, and polarities of the 2 nd display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period.
In one embodiment, the transistors connected to 2 pixels adjacent to each other in the column direction are connected to the 1 st source bus lines different from each other.
In one embodiment, when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N (N is 2 or more and is an integer of 2 times or less a quotient obtained by dividing m by 1080) pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction are connected to the 1 st source bus line arranged corresponding to the pixel column adjacent to the pixel column.
In one embodiment, the plurality of source bus lines include a1 st source bus line and a2 nd source bus line disposed corresponding to each pixel column, and polarities of the 1 st display signal voltage supplied to the 1 st source bus line and the 2 nd source bus line in each vertical scanning period are opposite to each other, and polarities of the 2 nd display signal voltage supplied to the 2 nd source bus line in each vertical scanning period are opposite to each other.
In one embodiment, the polarities of the 1 st display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other in each vertical scanning period, and the polarities of the 2 nd display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other in each vertical scanning period.
In one embodiment, in each pixel row, one pixel of 2 pixels adjacent to each other in the row direction is connected to the 1 st source bus line, and the other pixel is connected to the 2 nd source bus line.
In one embodiment, in each pixel row, 2 pixels adjacent to each other in the row direction are connected to the 1 st source bus line or the 2 nd source bus line.
In one embodiment, in each pixel column, the transistor connected to a certain pixel is connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistor connected to a pixel adjacent to the certain pixel in the column direction is connected to the 2 nd source bus line arranged corresponding to the pixel column.
In one embodiment, when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N (N is 2 or more and is an integer 2 times or less a quotient obtained by dividing m by 1080) pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction are connected to the 2 nd source bus line arranged corresponding to the pixel column.
In one embodiment, the number of the plurality of rows included in the plurality of pixels exceeds 1080.
In one embodiment, the liquid crystal display panel further includes: a plurality of 1 st buffer circuits provided in the 1 st frame region, each of the 1 st buffer circuits being provided corresponding to each of the 1 st source drivers and the associated plurality of source buses of each of the 1 st source drivers, and including a plurality of 1 st buffers; and a plurality of 2 nd buffer circuits provided in the 2 nd frame region, each of the 2 nd buffer circuits being provided corresponding to each of the plurality of 2 nd source drivers and the associated plurality of source bus lines of each of the plurality of 2 nd source drivers, and including a plurality of 2 nd buffers.
In one embodiment, the input wiring and the output wiring connected to each 1 st buffer of the 1 st buffers are disposed adjacent to each other, and the input wiring and the output wiring connected to each 2 nd buffer of the 2 nd buffers are disposed adjacent to each other.
In one embodiment, each of the 1 st buffers includes a1 st switching mechanism, the 1 st switching mechanism controls switching from a state in which the 1 st buffer does not operate to a state in which the 1 st buffer operates, and each of the 2 nd buffers includes a2 nd switching mechanism, the 2 nd switching mechanism controls switching from a state in which the 2 nd buffer does not operate to a state in which the 2 nd buffer operates.
In one embodiment, the plurality of 1 st buffers and the plurality of 2 nd buffers included in the 1 st buffer circuit and the 2 nd buffer circuit provided corresponding to the source bus line in which the disconnection does not occur among the plurality of source bus lines are in a non-operating state.
A liquid crystal display panel correction method according to an embodiment of the present invention is the liquid crystal display panel correction method according to any one of the above-described embodiments, including the steps of: when 1 of the plurality of source bus lines is disconnected, and a distance from a portion where the disconnection occurs to the 1 st source driver is longer than a distance from the portion where the disconnection occurs to the 2 nd source driver, the source bus line where the disconnection occurs is connected to the 1 st buffer of the plurality of 1 st buffers, and when 1 of the plurality of source bus lines is disconnected, and a distance from a portion where the disconnection occurs to the 2 nd source driver is longer than a distance from a portion where the disconnection occurs to the 1 st source driver, the source bus line where the disconnection occurs is connected to the 1 nd buffer of the plurality of 2 nd buffers.
In one embodiment, the correction method further includes the steps of: the state of the 1 st buffer not operating is switched to the state of the 1 st buffer operating by operating the 1 st switching mechanism of the 1 st buffer connected to the source bus line where the disconnection has occurred, or the state of the 2 nd buffer not operating is switched to the state of the 2 nd buffer operating by operating the 2 nd switching mechanism of the 2 nd buffer connected to the source bus line where the disconnection has occurred.
Effects of the invention
According to the embodiments of the present invention, a liquid crystal display panel and a correction method thereof can be provided in which heat generation of source drivers is suppressed and charging capability required for each source driver is reduced.
Drawings
Fig. 1 is a schematic plan view of a liquid crystal display panel 100A according to embodiment 1 of the present invention.
Fig. 2 (a) is a schematic plan view of the TFT substrate 10a1 used in the liquid crystal display panel 100, and (b) is a diagram showing waveforms of various voltages used in driving of the liquid crystal display panel having the TFT substrate 10a 1.
Fig. 3 (a) is a schematic plan view of the TFT substrate 10a2 used in the liquid crystal display panel according to embodiment 1 of the present invention, and (b) is a waveform diagram showing various voltages used for driving the liquid crystal display panel having the TFT substrate 10a 2.
Fig. 4 (a) is a schematic plan view of the TFT substrate 10A3 used in the liquid crystal display panel according to embodiment 1 of the present invention, and (b) is a diagram showing waveforms of various voltages used for driving the liquid crystal display panel having the TFT substrate 10 A3.
Fig. 5 is a schematic plan view of the TFT substrate 10B1 used in the liquid crystal display panel according to embodiment 2 of the present invention.
Fig. 6 is a diagram showing waveforms of various voltages used in driving of the liquid crystal display panel having the TFT substrate 10B 1.
Fig. 7 is a schematic plan view of the TFT substrate 10B2 used in the liquid crystal display panel according to embodiment 2 of the present invention.
Fig. 8 is a schematic plan view of the TFT substrate 10B3 used in the liquid crystal display panel according to embodiment 2 of the present invention.
Fig. 9 is a schematic plan view of a TFT substrate 10C1 used in a liquid crystal display panel according to embodiment 3 of the present invention.
Fig. 10 is a diagram showing waveforms of various voltages used in driving of the liquid crystal display panel having the TFT substrate 10C 1.
Fig. 11 is a schematic plan view of a TFT substrate 10C2 used in the liquid crystal display panel according to embodiment 3 of the present invention.
Fig. 12 is a schematic plan view of a TFT substrate 10C3 used in the liquid crystal display panel according to embodiment 3 of the present invention.
Fig. 13 is a schematic plan view of a liquid crystal display panel 200 according to embodiment 4 of the present invention.
Fig. 14 (a) and (b) show an example of a schematic plan view of the 2 nd buffer circuit 34b, respectively, and (c) is a diagram showing a part of (a) in an enlarged manner.
Fig. 15 (a) and (b) are each an example of a circuit diagram of the 2 nd buffer circuit 34 b.
Fig. 16 (a) is a schematic plan view of the TFT substrate 10X used in the liquid crystal display panel of comparative example 1, (b) is a diagram showing waveforms of various voltages used for driving the liquid crystal display panel of comparative example 1 having the TFT substrate 10X, and (c) is a diagram for explaining a cause of excessive heat generation of the source driver in the liquid crystal display panel of comparative example 1.
Fig. 17 is a cross-sectional view of a crystalline silicon TFT710A and an oxide semiconductor TFT710B in an active matrix substrate 700 used in a liquid crystal display panel according to embodiment 5 of the present invention.
Detailed Description
First, the cause of the problem of excessive heat generation of the source driver (problem 1) found by the present inventors will be described with reference to (a) to (c) of fig. 16. Fig. 16 (a) is a schematic plan view of the TFT substrate 10X used in the liquid crystal display panel of comparative example 1, and is a diagram showing the electrical connection relationship between the transistors of the respective pixels and the gate bus lines 12 and the source bus lines 14s, and the polarity of the display signal voltage applied to the respective pixels in a certain vertical scanning period. Fig. 16 (b) is a diagram showing waveforms of various voltages used for driving the liquid crystal display panel of comparative example 1 having the TFT substrate 10X. Fig. 16 (c) is a diagram for explaining the cause of excessive heat generation by the source driver in the liquid crystal display panel of comparative example 1.
The liquid crystal display panel of comparative example 1 has a two-side input drive structure in the same manner as the liquid crystal display panel according to the embodiment of the present invention (for example, the liquid crystal display panel 100 in fig. 1). Reference will sometimes be made to fig. 1 in the description of the two-side input drive configuration. Here, fig. 1 is a schematic plan view of a liquid crystal display panel 100 according to embodiment 1 of the present invention. The liquid crystal display panel of comparative example 1 is different from the liquid crystal display panel of the embodiment of the present invention in the electrical connection relationship between the transistor of each pixel and the source bus line 14s and/or the display signal voltage supplied to the source bus line 14 s.
The liquid crystal display panel of comparative example 1 includes a TFT substrate 10X, a counter substrate (not shown), and a liquid crystal layer (not shown) provided between the two substrates. The TFT substrate 10X includes: a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns; a plurality of transistors; a plurality of gate bus lines 12; and a plurality of source bus lines 14 s. The plurality of transistors are connected to 1 arbitrary pixel of the plurality of pixels, respectively. The display area of the liquid crystal display panel of comparative example 1 was divided by a plurality of pixels.
As shown in fig. 16 (a), the TFT substrate 10X has a multi-pixel structure, and each pixel P has 2 sub-pixels SPa and SPb. The 2 sub-pixels SPa and SPb are arranged along the column direction. The TFT substrate 10X includes 2 sub-pixel electrodes (1 st sub-pixel electrode 11a and 2 nd sub-pixel electrode 11b) corresponding to the 2 sub-pixels (1 st sub-pixel SPa and 2 nd sub-pixel SPb). The 2 sub-pixel electrodes 11a and 11b are supplied with a display signal voltage from a common source bus line 14s, for example, through 2 transistors 18a and 18b connected to the common gate bus line 12.
As shown in fig. 16 (a), the plurality of source bus lines 14s are arranged corresponding to the respective pixel columns. The transistors 18a and 18b connected to the pixels in each pixel column are connected to the source bus line 14s arranged corresponding to the pixel column. That is, the transistors 18a and 18b connected to the pixels included in the nth pixel column are connected to the source bus line s (n) disposed corresponding to the nth pixel column.
As shown in fig. 1, the liquid crystal display panel of comparative example 1 further includes: a1 st source driver 35a provided in the 1 st frame region 20a above the display region and configured to supply a1 st display signal voltage to the plurality of source bus lines 14 s; and a2 nd source driver 35b provided in the 2 nd frame region 20b below the display region 10d and supplying a2 nd display signal voltage to the plurality of source bus lines 14 s. In each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines 14s in a superimposed manner. The 1 st display signal voltage and the 2 nd display signal voltage are generated from a common input display signal. The 1 st source driver 35a and the 2 nd source driver 35b generate a1 st display signal voltage and a2 nd display signal voltage to be supplied to each pixel, respectively, based on the gray scale to be displayed by the pixel supplied by the input display signal. The 1 st display signal voltage and the 2 nd display signal voltage generated from the respective source drivers are the same in an ideal situation.
Fig. 16 (b) shows waveforms of voltages supplied to the source bus lines s (n) and the gate bus lines g (m). Among the display signal voltages supplied to the respective source bus lines s (n), the 1 st display signal voltage is indicated by a solid line, and the 2 nd display signal voltage is indicated by a dotted line. As shown in fig. 16 (b), the 1 st display signal voltage and the 2 nd display signal voltage supplied to each source bus line are inverted in polarity every 1 horizontal scanning period (1H). As a result, as shown in fig. 16 (a), in each vertical scanning period (also referred to as a frame period), the polarities of the signal voltages supplied to the pixels adjacent to each other are opposite to each other, and a state called dot inversion is exhibited. Here, the 1 horizontal scanning period (1H) is a difference (period) between a timing of selecting a certain scanning line (gate bus line) and a timing of selecting the next scanning line in each vertical scanning period.
Since the 1 st display signal voltage and the 2 nd display signal voltage are supplied from the source drivers 35a or 35b different from each other, as shown in fig. 16 (b), the timings of supplying the signals to the source bus lines 14s may be different from each other. At this time, polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the respective source bus lines 14s may be different from each other. As shown in fig. 16 (c), when a potential difference is generated between the 1 st source driver 35a and the 2 nd source driver 35b, an abnormal current is generated in the direction of the arrow in the drawing. The 1 st source driver 35a and the 2 nd source driver 35b may generate excessive heat due to the generation of the abnormal current. If the 1 st source driver 35a and the 2 nd source driver 35b are overheated, a failure may be caused. The abnormal current does not occur in the liquid crystal display panel having the one-side input driving structure.
In the liquid crystal display panel of comparative example 1, since the 1 st display signal voltage and the 2 nd display signal voltage are inverted in polarity every 1 horizontal scanning period (1H), the 1 st display signal voltage and the 2 nd display signal voltage have different polarities from each other at high frequency, and a potential difference occurs between the 1 st source driver and the 2 nd source driver at high frequency. For example, an abnormal current may be generated every 1 horizontal scanning period (1H). On the other hand, if the period of the polarity oscillations of the 1 st display signal voltage and the 2 nd display signal voltage is made longer, the display quality may be degraded. For example, if the polarities of the 1 st display signal voltage and the 2 nd display signal voltage are inverted every 1 vertical scanning period (1V), the polarities of the signal voltages supplied to the pixels adjacent to each other are the same in each vertical scanning period (frame period), and therefore flicker may occur.
Hereinafter, a liquid crystal display panel and a correction method thereof according to an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiments exemplified below. In the following drawings, components having substantially the same function are denoted by common reference numerals, and description thereof may be omitted.
(embodiment mode 1)
A liquid crystal display panel 100 according to embodiment 1 of the present invention will be described with reference to fig. 1 and 2. Fig. 1 is a schematic plan view of a liquid crystal display panel 100 according to embodiment 1 of the present invention. Fig. 2 (a) is a schematic plan view of the TFT substrate 10a1 used in the liquid crystal display panel 100, and fig. 2 (b) is a diagram showing waveforms of various voltages used in driving the liquid crystal display panel having the TFT substrate 10a 1.
As shown in fig. 1, the liquid crystal display panel 100 includes a TFT substrate 10a1, a counter substrate (not shown), and a liquid crystal layer (not shown) provided between the substrates. The TFT substrate 10a1 includes a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns, a plurality of transistors, a plurality of gate bus lines 12, and a plurality of source bus lines 14 s.
The plurality of transistors are connected to 1 arbitrary pixel of the plurality of pixels, respectively. The display area 10d of the liquid crystal display panel 100 is divided by a plurality of pixels. In a region of the TFT substrate 10a1 corresponding to the display region 10d of the liquid crystal display panel 100, there are formed: pixel electrodes arranged in a matrix (for example, see the sub-pixel electrodes 11a and 11b in fig. 2 (a)); transistors (for example, see transistors 18a and 18b in fig. 2 (a)) having drain electrodes connected to the respective pixel electrodes; a gate bus line 12 connected to a gate electrode of the transistor; and a source bus line 14s connected to the source electrode of the transistor. The plurality of gate bus lines 12 extend in the row direction, respectively, and are connected to any one of the plurality of transistors. The plurality of source bus lines 14s extend in the column direction, respectively, and are connected to any one of the plurality of transistors. The electrical connection relationship between the transistors of each pixel and the gate bus line 12 and the source bus line 14s will be described with reference to fig. 2 to 4.
The liquid crystal display panel 100 has, for example, a gate driver 32 on the right or left of the display region 10 d. The gate signal voltages are supplied from the gate driver 32 to the plurality of gate bus lines 12. The gate driver 32 may be provided on either or both of the right and left sides of the display region 10 d. A plurality of gate drivers 32 may also be provided. In the case where a plurality of gate drivers 32 are provided to the right or left of the display region 10d, each gate driver 32 supplies a gate signal voltage to an associated plurality of gate bus lines of the plurality of gate bus lines 12.
The liquid crystal display panel 100 further includes: a plurality of 1 st source drivers 35a provided in the 1 st frame region 20a above the display region 10 d; and a plurality of 2 nd source drivers 35b provided in the 2 nd frame region 20b below the display region 10 d. Each 1 st source driver 35a of the plurality of 1 st source drivers 35a supplies the 1 st display signal voltage to an associated plurality of source bus lines of the plurality of source bus lines 14 s. Each of the 2 nd source drivers 35b of the plurality of 2 nd source drivers 35b supplies the 2 nd display signal voltage to the associated plurality of source bus lines of the plurality of source bus lines 14 s. In each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines 14s in a superimposed manner. The polarities of the 1 st display signal voltage and the 2 nd display signal voltage do not change in each vertical scanning period.
With regard to each 1 st source driver 35a of the plurality of 1 st source drivers 35a, the associated plurality of source bus lines refers to, for example, source bus lines electrically connected to each 1 st source driver 35a of the plurality of 1 st source drivers 35 a. With regard to each 2 nd source driver 35b of the plurality of 2 nd source drivers 35b, the associated plurality of source bus lines refer to, for example, source bus lines electrically connected to each 2 nd source driver 35b of the plurality of 2 nd source drivers 35 b.
The liquid crystal display panel 100 has a two-side input driving structure, and thus charging capability required for each source driver is reduced as compared with a liquid crystal display panel having a one-side input driving structure. That is, the liquid crystal display panel 100 has a high charging capability as compared with a liquid crystal display panel having a one-side input driving structure. Evaluation of the charging capability of the liquid crystal display panel 100 will be described later.
As shown in the figure, the gate driver 32 and the source drivers 35a and 35b are mounted on the TFT substrate 10A using, for example, COF (chip on film). The 1 st and 2 nd frame regions 20a and 20b may include COFs. However, the gate driver 32 and/or the source drivers 35a and 35b may be mounted on the TFT substrate 10A by using COG (chip on glass). The 1 st frame region 20A and the 2 nd frame region 20b may be included in the TFT substrate 10A.
A1 st display signal voltage and a2 nd display signal voltage are generated from a common input display signal. The 1 st source driver 35a and the 2 nd source driver 35b generate a1 st display signal voltage and a2 nd display signal voltage to be supplied to each pixel, respectively, based on the gray scale to be displayed by the pixel supplied by the input display signal. The 1 st display signal voltage and the 2 nd display signal voltage generated from the 1 st source driver 35a and the 2 nd source driver 35b are the same in an ideal situation.
In the liquid crystal display panel 100, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14s in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel 100, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to each source bus line 14s differ from each other in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation of the source driver is suppressed. The frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to each source bus line 14s differ from each other in polarity is, for example, at most 1 time per 1 vertical scanning period (1V). For example, in a panel of 4K2K (sometimes simply referred to as "4K") (about 4000 pixels horizontal × about 2000 pixels vertical), if the value in the liquid crystal display panel of comparative example 1 is 1, the value in the liquid crystal display panel 100 is about 1 in 2000, regarding the frequency at which the polarities of the 1 st display signal voltage and the 2 nd display signal voltage are different from each other.
The electrical connection relationship between the transistor of each pixel and the gate bus line 12 and the source bus line 14s will be described with reference to fig. 2 (a). Fig. 2 (a) shows the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14s, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period.
The TFT substrate 10a1 has a multi-pixel structure, and each pixel P has 2 sub-pixels SPa and SPb. The 2 sub-pixels SPa and SPb are arranged along the column direction. The 2 sub-pixels SPa and SPb can exhibit gray levels (brightness) different from each other. With respect to the gray scale to be displayed by the pixel P in accordance with the source signal voltage (gray scale signal voltage) input to the pixel P, one sub-pixel Spa exhibits a higher gray scale, the other sub-pixel SPb exhibits a lower gray scale, and the pixel P as a whole exhibits a gray scale corresponding to the input source signal voltage. The multi-pixel structure is particularly suitable for a liquid crystal display panel of a vertical alignment mode, and can improve the viewing angle dependence of the gamma characteristic. The structure of a liquid crystal display panel having a multi-pixel structure and a driving method thereof are described in, for example, japanese patent application laid-open No. 2005-189804 (japanese patent No. 4265788) by the applicant of the present application. The entire disclosure of Japanese patent application laid-open No. 2005-189804 is incorporated herein by reference for reference.
The TFT substrate 10a1 has 2 sub-pixel electrodes (1 st sub-pixel electrode 11a and 2 nd sub-pixel electrode 11b) corresponding to the 2 sub-pixels (1 st sub-pixel SPa and 2 nd sub-pixel SPb). The 2 sub-pixel electrodes 11a and 11b are supplied with a display signal voltage from a common source bus line 14s, for example, through 2 transistors 18a and 18b connected to the common gate bus line 12. Of course, the 2 transistors 18a and 18b need only be on/off controlled at the same timing, and therefore need not necessarily be connected to the common gate bus line 12. The same applies to the source bus line 14 s. However, if the number of gate bus lines and/or source bus lines increases, this may cause a decrease in the aperture ratio, and therefore, it is preferable that 2 transistors 18a and 18b corresponding to 2 sub-pixels SPa and SPb constituting 1 pixel P are connected to the common gate bus line 12 and the common source bus line 14 s.
The liquid crystal display panel 100 has a single source structure. The plurality of source bus lines 14s include source bus lines (sometimes referred to as "1 st source bus lines") 14s arranged corresponding to the respective pixel columns. The source bus line arranged corresponding to the nth pixel column (i.e., a plurality of pixels arranged in the column direction) may be referred to as s (n). In the liquid crystal display panel 100, the transistors 18a, 18b connected to 2 pixels adjacent to each other in the column direction are connected to 1 st source bus lines different from each other. The transistors 18a, 18b connected to 2 pixels adjacent to each other in the row direction are connected to mutually different source bus lines 14 s. In each vertical scanning period, the polarities of the 1 st display signal voltages supplied to the mutually adjacent 2 source bus lines 14s are opposite to each other, and in each vertical scanning period, the polarities of the 2 nd display signal voltages supplied to the mutually adjacent 2 source bus lines 14s are opposite to each other. As described above, in each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines 14s in a superimposed manner, and the respective polarities of the 1 st display signal voltage and the 2 nd display signal voltage do not change in each vertical scanning period. Therefore, as shown in fig. 2 (a), in each vertical scanning period (also referred to as a frame period), the polarities of the signal voltages supplied to the pixels adjacent to each other are opposite to each other, and a dot inversion state is exhibited. The liquid crystal display panel 100 can suppress the occurrence of flicker, and therefore can suppress heat generation of the source driver without degrading display quality.
Fig. 2 (b) shows waveforms of voltages supplied to the source bus lines s (n) and the gate bus lines g (m). The gate bus line arranged corresponding to the mth pixel row (i.e., a plurality of pixels arranged in the row direction) may be referred to as g (m). Among the display signal voltages supplied to the respective source bus lines s (n), the 1 st display signal voltage is indicated by a solid line, and the 2 nd display signal voltage is indicated by a broken line. As shown in fig. 2 b, the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines are inverted in polarity (with a period of 2V) every 1 vertical scanning period (1V). That is, in a certain vertical scanning period, the polarity of the display signal voltage applied to each pixel is inverted in the next vertical scanning period, as shown in fig. 2 (a). However, the period of the polarity inversion of the 1 st display signal voltage and the 2 nd display signal voltage may be, for example, 4V or more. If the period of polarity inversion between the 1 st display signal voltage and the 2 nd display signal voltage is long, the frequency of occurrence of abnormal current can be reduced and power consumption can be reduced.
Here, the charging ability of the liquid crystal display panel was evaluated. The charging capability of the liquid crystal display panel is proportional to the charging time of each pixel, and inversely proportional to the source bus load (the product of capacitance and resistance (also referred to as "CR product") of each source driver. With the increase in size and/or high definition of liquid crystal display panels, the charging capability of the liquid crystal display panels needs to be improved.
The liquid crystal display panel 100 has a two-side input drive structure, and therefore, as described below, has a higher charging capability than a liquid crystal display panel having a one-side input drive structure (which may be referred to as a "liquid crystal display panel of comparative example 2"). As described below, if the liquid crystal display panel of comparative example 2 is assumed to have a1, the source bus load for each source driver is 1/4 in the liquid crystal display panel 100. In the liquid crystal display panel 100, since the source drivers are connected to both sides of the source bus lines, each source driver drives substantially half of each source bus line. Therefore, with each source driver, the source bus resistance becomes 1/2, and the source bus capacitance becomes 1/2, so the source bus load, which is the product of these, becomes 1/4. The liquid crystal display panel 100 and the liquid crystal display panel of comparative example 2 each have a single source structure, and thus the charging time of each pixel is the same. From the above, the charging capability of the liquid crystal display panel 100 was evaluated to be 4 times that of the liquid crystal display panel of comparative example 2.
In the liquid crystal display panel 100 having the multi-pixel structure, the 1 st sub-pixel Spa has a1 st auxiliary capacitance, and the 2 nd sub-pixel SPb has a2 nd auxiliary capacitance. The auxiliary capacitance voltages different from each other are supplied from the auxiliary capacitance line CSa connected to the 1 st auxiliary capacitance of the 1 st sub-pixel SPa and the auxiliary capacitance line CSb connected to the 2 nd auxiliary capacitance of the 2 nd sub-pixel SPb, whereby the effective voltages applied to the liquid crystal layer of the 1 st sub-pixel SPa and the liquid crystal layer of the 2 nd sub-pixel SPb are different. Here, the auxiliary capacitance lines CSa and CSb are electrically independent from the gate bus lines 12. In addition, the entire liquid crystal display panel 100 is provided with, for example, 12 types of storage capacitor lines electrically independent of each other, such as the storage capacitor lines CSa and CSb, and the storage capacitor voltage is supplied to the storage capacitor electrode of the corresponding sub pixel in accordance with the phase of the storage capacitor voltage. For example, 12 kinds of auxiliary capacitance voltages are supplied from 12 auxiliary capacitance rails to the respective auxiliary capacitance lines.
In a general liquid crystal display panel, since the same voltage as that of a liquid crystal capacitor is applied to an auxiliary capacitor, the same voltage as that of a pixel electrode is supplied to one electrode of a pair of electrodes constituting the auxiliary capacitor, and the same voltage (common voltage) as that of a common electrode (counter electrode) is supplied to the other electrode. In contrast, in the liquid crystal display panel having the multi-pixel structure, different oscillation voltages (voltages oscillating in 1 vertical scanning period) are supplied from the auxiliary capacitance lines CSa and CSb. The oscillation voltage is typically a voltage that is 180 ° out of phase with respect to the auxiliary capacitance line CSa and the auxiliary capacitance line CSb. Among the pair of electrodes included in the storage capacitor, the electrode connected to the storage capacitor wiring is also referred to as a storage capacitor counter electrode.
The storage capacitor wiring and the storage capacitor electrode connected thereto are formed of, for example, the same metal layer as the gate bus line (referred to as a gate metal layer). The dielectric layer of the auxiliary capacitor is formed of, for example, a gate insulating layer. The electrode formed on the dielectric layer on the auxiliary capacitance electrode is formed of the same conductive layer as the pixel electrode (sub-pixel electrode) or the same metal layer (source metal layer) as the source bus line, and is electrically connected to the drain of the TFT or the pixel electrode (sub-pixel electrode). The structure of these auxiliary capacitors is well known, and therefore, the illustration thereof is omitted.
For example, as shown in fig. 2 (a), the storage capacitor lines CSa and CSb of the TFT substrate 10a1 each include: a1 st storage capacitor wire 16_1 connected to a1 st storage capacitor (storage capacitor included in the 1 st sub-pixel SPa) belonging to 1 pixel row (i.e., a plurality of pixels arranged in the row direction) and extending in the row direction; a2 nd auxiliary capacitance line 16_2 connected to a2 nd auxiliary capacitance (auxiliary capacitance included in the 2 nd sub-pixel SPb) belonging to 1 pixel row and extending in the row direction; and a3 rd auxiliary capacitance line 16_3 provided in parallel to the 1 st and 2 nd auxiliary capacitance lines 16_1 and 16_2 associated with mutually adjacent pixel rows and electrically connected to the 1 st and 2 nd auxiliary capacitance lines 16_1 and 16_ 2.
For example, when 2 pixels arranged in the column direction are set as pixels in the k-th row and pixels in the k + 1-th row, and the 2-th sub-pixel SPb is arranged in the column direction of the 1-th sub-pixel SPa in each pixel, each of the auxiliary capacitance lines CSa and CSb further includes a 2-th auxiliary capacitance line 16_2 associated with the 2-th sub-pixel SPb of the pixels in the k-th row, a 1-th auxiliary capacitance line 16_1 associated with the 1-th sub-pixel SPa of the pixels in the k + 1-th row, a 3-th auxiliary capacitance line 16_3 provided between the 2-th auxiliary capacitance line 16_2 and the 1-th auxiliary capacitance line 16_1, and an auxiliary capacitance connection line 16cn electrically connecting these lines. The storage capacitor connection line 16cn is electrically connected to the storage capacitor electrodes of the 1 st storage capacitor (the storage capacitor of the 1 st sub-pixel SPa) and the 2 nd storage capacitor (the storage capacitor of the 2 nd sub-pixel SPb).
In this way, the auxiliary capacitance lines CSa and CSb have a branch structure (including a ladder structure) including a plurality of lines, and thus the resistance of the auxiliary capacitance lines CSa and CSb can be reduced. Therefore, in a high-definition and/or large-sized liquid crystal display panel, delay of the storage capacitor voltage and occurrence of waveform blunting can be suppressed.
In the above example, the liquid crystal display panel 100 has a multi-pixel structure, but the present embodiment is not limited thereto.
For example, the multi-pixel structure and/or the multi-pixel driving method of the liquid crystal display panel of the present embodiment are not limited to the illustrated ones. That is, the method of causing 2 sub-pixels included in each pixel to exhibit different gray levels (luminances) from each other is not limited to the illustrated method. For example, in addition to the transistor and the storage capacitor connected to each sub-pixel, one of the sub-pixels may be driven by one transistor and a capacitor connected thereto. Such a multi-pixel structure having 3 transistors per pixel has been disclosed in, for example, fig. 8 and 9 of japanese laid-open patent publication No. 2013-250545.
The liquid crystal display panel of the present embodiment may not have a multi-pixel structure. The liquid crystal display panel of the present embodiment may not be driven by multiple pixels.
The liquid crystal display panel of the present embodiment is not limited to the vertical alignment mode (VA mode). The liquid crystal display panel of the present embodiment may be in a horizontal electric field mode (including an IPS mode and an FFS mode).
The transistor of the liquid crystal display panel 100 may be a known TFT such as an amorphous silicon TFT (a-Si TFT), a polycrystalline silicon TFT (p-Si TFT), or a microcrystalline silicon TFT (μ C-Si TFT), but a TFT having an oxide semiconductor layer (oxide TFT) is preferably used.
The oxide semiconductor included in the oxide semiconductor layer may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. The crystalline oxide semiconductor includes a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer plane, and the like.
The oxide semiconductor layer may have a stacked structure of 2 or more layers. In the case where the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures may be included. In addition, a plurality of amorphous oxide semiconductor layers may be included. In the case where the oxide semiconductor layer has a 2-layer structure including an upper layer and a lower layer, it is preferable that the energy gap of the oxide semiconductor included in the upper layer is larger than the energy gap of the oxide semiconductor included in the lower layer. However, when the difference between the energy gaps of these layers is small, the energy gap of the lower oxide semiconductor may be larger than that of the upper oxide semiconductor.
The materials, structures, film formation methods, and structures of the amorphous oxide semiconductor and the crystalline oxide semiconductors described above are disclosed in, for example, japanese patent application laid-open No. 2014-007399. The entire disclosure of Japanese patent application laid-open No. 2014-007399 is incorporated herein by reference.
The oxide semiconductor layer may also include at least 1 metal element of In, Ga, and Zn, for example. The oxide semiconductor layer includes, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In: ga: zn is 2: 2: 1. in: ga: 1, Zn: 1: 1. in: ga: 1, Zn: 1: 2, etc. Such an oxide semiconductor layer can be formed of an oxide semiconductor film including an In-Ga-Zn-O-based semiconductor. Further, a channel-etched TFT having an active layer including an oxide semiconductor such as an In-Ga-Zn-O based semiconductor is sometimes referred to as a "CE-OS-TFT".
The In-Ga-Zn-O semiconductor may be amorphous or crystalline. The crystalline In-Ga-Zn-O-based semiconductor is preferably a crystalline In-Ga-Zn-O-based semiconductor having a c-axis oriented substantially perpendicular to a layer plane.
Further, crystalline structures of crystalline In-Ga-Zn-O-based semiconductors are disclosed In, for example, Japanese patent laid-open Nos. 2014-007399, 2012-134475, 2014-209727, and the like. For reference, the entire disclosures of Japanese patent laid-open Nos. 2012-134475 and 2014-209727 are incorporated herein by reference. The TFT having the In-Ga-Zn-O-based semiconductor layer has high mobility (more than 20 times as high as that of an a-si TFT) and low leakage current (less than 1: 100 as compared with an a-si TFT), and is therefore suitable for use as a driving TFT (e.g., a TFT included In a driving circuit provided on the same substrate as a display region In the periphery of the display region including a plurality of pixels) and a pixel TFT (TFT provided In a pixel).
The oxide semiconductor layer may contain another oxide semiconductor instead of the In-Ga-Zn-O semiconductor. For example, an In-Sn-Zn-O semiconductor (e.g., In) may be contained2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc). Alternatively, the oxide semiconductor layer may contain an In-Al-Zn-O semiconductor, an In-Al-Sn-Zn-O semiconductor, a Zn-O semiconductor, an In-Zn-O semiconductor, a Zn-Ti-O semiconductor, a Cd-Ge-O semiconductor, or a Cd-Pb-O semiconductorA conductor, CdO (cadmium oxide), Mg-Zn-O-based semiconductor, In-Ga-Sn-O-based semiconductor, In-Ga-O-based semiconductor, Zr-In-Zn-O-based semiconductor, Hf-In-Zn-O-based semiconductor, Al-Ga-Zn-O-based semiconductor, etc.
In the above example, the liquid crystal display panel 100 exhibits a dot inversion state (1 row 1 column dot inversion state), but the present embodiment is not limited thereto. As described below, the liquid crystal display panel of the present embodiment may exhibit a dot inversion state of N rows and 1 column (N is an integer of 2 or more). A case where N is 2 will be described with reference to fig. 3, and a case where N is 3 or more will be described with reference to fig. 4.
Another example of the present embodiment will be described with reference to fig. 3. Fig. 3 (a) is a schematic plan view of the TFT substrate 10a2 used in the liquid crystal display panel of embodiment 1, and is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14s, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period. Fig. 3 (b) is a diagram showing waveforms of various voltages used for driving the liquid crystal display panel having the TFT substrate 10a 2.
As shown in fig. 3 (a), the liquid crystal display panel of embodiment 1 having the TFT substrate 10a2 is different from the liquid crystal display panel 100 having the TFT substrate 10a1 in that it exhibits a dot inversion state of 2 rows and 1 columns. That is, in each pixel column (an nth pixel column) of the TFT substrate 10a2, the transistors 18a and 18b connected to 2 pixels adjacent to each other are connected to the 1 st source bus line S (n) disposed corresponding to the pixel column (the nth pixel column), and the transistors 18a and 18b connected to 2 pixels adjacent to each other, which are adjacent to the 2 pixels in the column direction, are connected to the 1 st source bus line S (n +1) disposed corresponding to the pixel column (the n +1 th pixel column) adjacent to the pixel column. The liquid crystal display panel of embodiment 1 having the TFT substrate 10a2 may be the same as the liquid crystal display panel 100, except for the electrical connection relationship between the transistors of the respective pixels and the source bus lines.
The liquid crystal display panel of embodiment 1 having the TFT substrate 10a2 has a two-side input drive structure, and therefore the charging capability required for each source driver is reduced as compared with a liquid crystal display panel having a one-side input drive structure.
In the liquid crystal display panel of embodiment 1 having the TFT substrate 10a2, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14s in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel of embodiment 1 having the TFT substrate 10a2, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to each source bus line 14s differ in polarity from each other is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation by the source driver is suppressed.
The liquid crystal display panel of embodiment 1 having the TFT substrate 10a2 exhibits a dot inversion state of 2 rows and 1 columns in each vertical scanning period, and therefore flicker is suppressed. However, as long as the resolution is the same, the dot inversion state of 1 row and 1 column is more preferable than the dot inversion state of 2 row and 1 column from the viewpoint of suppressing the occurrence of flicker.
Still another example of the present embodiment will be described with reference to fig. 4. Fig. 4 (a) is a schematic plan view of the TFT substrate 10a3 used in the liquid crystal display panel of embodiment 1, and is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14s, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period. Fig. 4 (b) is a diagram showing waveforms of various voltages used in driving the liquid crystal display panel having the TFT substrate 10a 3.
As shown in fig. 4 (a), the liquid crystal display panel of embodiment 1 having the TFT substrate 10A3 is different from the liquid crystal display panel 100 having the TFT substrate 10a1 in that it exhibits an N row 1 column dot inversion state (N is an integer of 3 or more). That is, in each pixel column (an nth pixel column) of the TFT substrate 10a3, the transistors 18a and 18b connected to N pixels adjacent to each other are connected to the 1 st source bus line S (N) disposed corresponding to the pixel column (the nth pixel column), and the transistors 18a and 18b connected to N pixels adjacent to each other and adjacent to the N pixels in the column direction are connected to the 1 st source bus line S (N +1) disposed corresponding to the pixel column (the N +1 th pixel column) adjacent to the pixel column. The liquid crystal display panel of embodiment 1 having the TFT substrate 10a3 may be the same as the liquid crystal display panel 100, except for the electrical connection relationship between the transistors of the respective pixels and the source bus lines.
The liquid crystal display panel of embodiment 1 having the TFT substrate 10a3 has a two-side input drive structure, and therefore the charging capability required for each source driver is reduced as compared with a liquid crystal display panel having a one-side input drive structure.
In the liquid crystal display panel of embodiment 1 having the TFT substrate 10a3, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14s in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel of embodiment 1 having the TFT substrate 10a3, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to each source bus line 14s differ in polarity from each other is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation by the source driver is suppressed.
The liquid crystal display panel of embodiment 1 having the TFT substrate 10a3 exhibits an N row 1 column dot inversion state in each vertical scanning period. As long as the resolution is the same, the dot inversion state of 1 row and 1 column is more preferable than the dot inversion state of N row and 1 column from the viewpoint of suppressing the occurrence of flicker. However, in a high-definition display panel having a resolution exceeding FHD (pixel number of 1080 rows × 1920 columns), such as 4K (pixel number of about 2000 rows × about 4000 columns), 8K (pixel number of about 4000 rows × about 8000 columns), there are cases where: even if inversion is performed for each of a plurality of lines, flicker is not visually recognized, and there is almost no problem in display quality. In order to suppress flicker, when the pixel rows of the plurality of pixels defining the display region 10d are m rows, N in the N row-1 column dot inversion state is preferably an integer equal to or less than 2 times the quotient of m divided by 1080, for example.
(embodiment mode 2)
A liquid crystal display panel according to embodiment 2 of the present invention will be described with reference to fig. 5 and 6. Fig. 5 is a schematic plan view of the TFT substrate 10B1 used in the liquid crystal display panel according to embodiment 2 of the present invention, and fig. 6 is a diagram showing waveforms of various voltages used for driving the liquid crystal display panel having the TFT substrate 10B 1. The following description will focus on differences between the liquid crystal display panel of the present embodiment and the liquid crystal display panel of embodiment 1. The same applies to the following embodiments.
The liquid crystal display panel of embodiment 2 is different from the liquid crystal display panel of embodiment 1 in that it has a double source structure.
Fig. 5 is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14a and 14b, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period. In the liquid crystal display panel of embodiment 2, the plurality of source bus lines includes the 1 st source bus line 14a and the 2 nd source bus line 14b arranged corresponding to each pixel column. In the figure, the source bus line provided on the left side of the pixel is denoted as the 1 st source bus line 14a, and the source bus line provided on the right side of the pixel is denoted as the 2 nd source bus line 14 b. The 1 st source bus line arranged corresponding to the nth pixel column (i.e., a plurality of pixels arranged in the column direction) may be referred to as sa (n), and the 2 nd source bus line arranged corresponding to the nth pixel column may be referred to as sb (n).
As shown in fig. 5, the polarities of the 1 st display signal voltages supplied in each vertical scanning period are opposite to each other for the 1 st source bus line 14a and the 2 nd source bus line 14b, and the polarities of the 2 nd display signal voltages supplied in each vertical scanning period are opposite to each other. In each vertical scanning period, the polarities of the 1 st display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other, and in each vertical scanning period, the polarities of the 2 nd display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other. In each pixel row, one pixel of 2 pixels adjacent to each other in the row direction is connected to the 1 st source bus line 14a, and the other pixel is connected to the 2 nd source bus line 14 b. As shown in fig. 6, in the liquid crystal display panel having the TFT substrate 10B1, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14B in a superimposed manner do not change in each vertical scanning period. As shown in fig. 5, in each vertical scanning period, the polarities of the signal voltages supplied to the pixels adjacent to each other are opposite to each other, and a dot inversion state is exhibited.
In the liquid crystal display panel having the TFT substrate 10B1, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14B differ in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation by the source driver is suppressed.
The liquid crystal display panel having the TFT substrate 10B1 can suppress the occurrence of flicker, and therefore can suppress heat generation of the source driver without degrading the display quality.
Fig. 6 shows waveforms of voltages supplied to the 1 st source bus line sa (n), the 2 nd source bus lines sb (n), and the gate bus lines g (m). Among the display signal voltages supplied to the source bus lines sa (n), sb (n), the 1 st display signal voltage is indicated by a solid line, and the 2 nd display signal voltage is indicated by a broken line. The 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines sa (n), sb (n) are inverted in polarity every 1 vertical scanning period (1V), for example.
Since the liquid crystal display panel having the TFT substrate 10B1 has a dual source structure, 2 gate bus lines can be simultaneously selected as shown in fig. 6. For example, as shown in fig. 6, transistors connected to 2 pixels adjacent to each other in the column direction are turned on at the same timing. For example, transistors connected to 2 pixels adjacent to each other in the column direction are connected to gate bus lines G (m) and G (m +1) different from each other, and the gate bus lines G (m) and G (m +1) are simultaneously selected. The transistors connected to 2 pixels adjacent to each other in the column direction may be on/off controlled by a common scanning signal.
The liquid crystal display panel having the TFT substrate 10B1 has a two-side input driving structure, and thus the charging capability required for each source driver is reduced as compared with the liquid crystal display panel having a one-side input driving structure. That is, the liquid crystal display panel having the TFT substrate 10B1 has a higher charging capability than the liquid crystal display panel having the one-side input drive structure. The charging ability of the liquid crystal display panel having the TFT substrate 10B1 was evaluated as follows.
When 2 gate bus lines are simultaneously selected and driven, in the liquid crystal display panel having the TFT substrate 10B1, a sufficient charging time for the pixels can be ensured. The charging time per pixel is 2 times that of the liquid crystal display panel of embodiment 1 having a single source structure. The source bus line load of each source driver is the same as that of the liquid crystal display panel of embodiment 1 having a single source structure. Here, considering the influence of the parasitic capacitance of the transistor connected to the source bus line, the source bus line load per source driver is smaller than that of the liquid crystal display panel of embodiment 1. This is because the liquid crystal display panel of embodiment 2 having the double source structure is half the liquid crystal display panel of embodiment 1 having the single source structure with respect to the number of transistors connected to each source bus line.
As described above, when the charging capability of the liquid crystal display panel of embodiment 1 having the single-source structure and the double-side input drive structure is 1, the charging capability of the liquid crystal display panel of embodiment 2 having the double-source structure and the double-side input drive structure is 2. The charging capability of the liquid crystal display panel of embodiment 2 was evaluated to be 8 times or more that of the liquid crystal display panel of comparative example 2 having a single source structure and having a one-side input driving structure.
In the above example, the liquid crystal display panel of embodiment 2 has a multi-pixel structure, but the present embodiment is not limited thereto.
As described in embodiment 1, the multi-pixel structure and/or the multi-pixel driving method of the liquid crystal display panel of this embodiment are not limited to those exemplified. That is, the method of causing 2 sub-pixels included in each pixel to exhibit different gray levels (luminances) from each other is not limited to the illustrated method. The liquid crystal display panel of the present embodiment may not have a multi-pixel structure. The liquid crystal display panel of the present embodiment may not be driven by multiple pixels. The liquid crystal display panel of the present embodiment is not limited to the vertical alignment mode (VA mode). The liquid crystal display panel of the present embodiment may be in a horizontal electric field mode (including an IPS mode and an FFS mode).
In the above example, the liquid crystal display panel having the TFT substrate 10B1 exhibits a dot inversion state (1 row 1 column dot inversion state), but the present embodiment is not limited thereto. As described below, the liquid crystal display panel of the present embodiment may exhibit a dot inversion state of N rows and 1 column (N is an integer of 2 or more). A case where N is 2 will be described with reference to fig. 7, and a case where N is 3 or more will be described with reference to fig. 8.
Another example of the present embodiment will be described with reference to fig. 7. Fig. 7 is a schematic plan view of the TFT substrate 10B2 used in the liquid crystal display panel of embodiment 2, and is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14a and 14B, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period.
As shown in fig. 7, the liquid crystal display panel having the TFT substrate 10B2 exhibits a2 row 1 column dot inversion state, which is different from the liquid crystal display panel having the TFT substrate 10B 1. That is, in each pixel column (an nth pixel column) of the TFT substrate 10B2, the transistors 18a and 18B connected to 2 pixels adjacent to each other are connected to the 1 st source bus line 14a arranged corresponding to the pixel column (the nth pixel column), and the transistors 18a and 18B connected to 2 pixels adjacent to each other, which are adjacent to the 2 pixels in the column direction, are connected to the 2 nd source bus line 14B arranged corresponding to the pixel column (the nth pixel column). The liquid crystal display panel having the TFT substrate 10B2 may be the same as the liquid crystal display panel having the TFT substrate 10B1, except for the electrical connection relationship between the transistor of each pixel and the source bus line. The various voltages used for driving the liquid crystal display panel having the TFT substrate 10B2 may be the same as those used for driving the liquid crystal display panel having the TFT substrate 10B1 shown in fig. 6.
The liquid crystal display panel having the TFT substrate 10B2 has a two-side input driving structure, and thus the charging capability required for each source driver is reduced as compared with the liquid crystal display panel having a one-side input driving structure.
In the liquid crystal display panel having the TFT substrate 10B2, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14B in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel having the TFT substrate 10B2, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14B differ in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation by the source driver is suppressed.
The liquid crystal display panel having the TFT substrate 10B2 exhibits a dot inversion state of 2 rows and 1 columns in each vertical scanning period, and therefore flicker is suppressed. However, as long as the resolution is the same, the dot inversion state of 1 row and 1 column is more preferable than the dot inversion state of 2 row and 1 column from the viewpoint of suppressing the occurrence of flicker.
Referring to fig. 8, still another example of the present embodiment will be described. Fig. 8 is a schematic plan view of the TFT substrate 10B3 used in the liquid crystal display panel of embodiment 2, and is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14a and 14B, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period.
As shown in fig. 8, the liquid crystal display panel having the TFT substrate 10B3 is different from the liquid crystal display panel having the TFT substrate 10B1 in that the liquid crystal display panel exhibits an N row 1 column dot inversion state (N is an integer of 3 or more). That is, in each pixel column (an nth pixel column) of the TFT substrate 10B3, the transistors 18a and 18B connected to N pixels adjacent to each other are connected to the 1 st source bus line 14a arranged corresponding to the pixel column (the nth pixel column), and the transistors 18a and 18B connected to N pixels adjacent to each other and adjacent to the N pixels in the column direction are connected to the 2 nd source bus line 14B arranged corresponding to the pixel column (the nth pixel column). The liquid crystal display panel having the TFT substrate 10B3 may be the same as the liquid crystal display panel having the TFT substrate 10B1, except for the electrical connection relationship between the transistor of each pixel and the source bus line. The various voltages used for driving the liquid crystal display panel having the TFT substrate 10B3 may be the same as those used for driving the liquid crystal display panel having the TFT substrate 10B1 shown in fig. 6.
The liquid crystal display panel having the TFT substrate 10B3 has a two-side input driving structure, and thus the charging capability required for each source driver is reduced as compared with the liquid crystal display panel having a one-side input driving structure.
In the liquid crystal display panel having the TFT substrate 10B3, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14B in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel having the TFT substrate 10B3, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14B differ in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation by the source driver is suppressed.
The liquid crystal display panel having the TFT substrate 10B3 exhibits an N row 1 column dot inversion state in each vertical scanning period, and therefore flicker is suppressed. As long as the resolution is the same, the dot inversion state of 1 row and 1 column is more preferable than the dot inversion state of N row and 1 column from the viewpoint of suppressing the occurrence of flicker. However, in a high-definition display panel having a resolution exceeding FHD (pixel number of 1080 rows × 1920 columns), such as 4K (pixel number of about 2000 rows × about 4000 columns), 8K (pixel number of about 4000 rows × about 8000 columns), there are cases where: even if inversion is performed for each of a plurality of lines, flicker is not visually recognized, and there is almost no problem in display quality. In order to suppress flicker, when the pixel rows of the plurality of pixels defining the display region 10d are m rows, N in the N row-1 column dot inversion state is preferably an integer equal to or less than 2 times the quotient of m divided by 1080, for example.
(embodiment mode 3)
A liquid crystal display panel according to embodiment 3 of the present invention will be described with reference to fig. 9 and 10. Fig. 9 is a schematic plan view of the TFT substrate 10C1 used in the liquid crystal display panel according to embodiment 3 of the present invention, and fig. 10 is a diagram showing waveforms of various voltages used for driving the liquid crystal display panel having the TFT substrate 10C 1.
The liquid crystal display panel of embodiment 3 has a double source structure as in the liquid crystal display panel of embodiment 2, but the electrical connection relationship between the transistors of the respective pixels and the source bus lines 14a and 14b and the polarity of the display signal voltage applied to the respective source bus lines 14a and 14b in the respective vertical scanning periods are different from those of the liquid crystal display panel of embodiment 2.
Fig. 9 is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14a and 14b, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period. As shown in fig. 9, in each pixel row, 2 pixels adjacent to each other in the row direction are each connected to the 1 st source bus line 14a or each connected to the 2 nd source bus line 14 b. In each vertical scanning period, the 1 st display signal voltages supplied to the 21 st source bus lines Sa (n) and Sa (n +1) corresponding to the 2 pixel columns adjacent to each other are opposite to each other, and in each vertical scanning period, the 1 st display signal voltages supplied to the 2 nd source bus lines Sb (n) and Sb (n +1) corresponding to the 2 pixel columns adjacent to each other are opposite to each other. In each vertical scanning period, the 2 nd display signal voltages supplied to the 21 st source bus lines Sa (n) and Sa (n +1) corresponding to the 2 pixel columns adjacent to each other are opposite to each other, and in each vertical scanning period, the 2 nd display signal voltages supplied to the 2 nd source bus lines Sb (n) and Sb (n +1) corresponding to the 2 pixel columns adjacent to each other are opposite to each other.
As shown in fig. 10, in the liquid crystal display panel having the TFT substrate 10C1, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14b in a superimposed manner do not change in each vertical scanning period. As shown in fig. 9, in each vertical scanning period, the polarities of the signal voltages supplied to the pixels adjacent to each other are opposite to each other, and a dot inversion state is exhibited.
In the liquid crystal display panel having the TFT substrate 10C1, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14b differ in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation of the source driver is suppressed.
The liquid crystal display panel having the TFT substrate 10C1 can suppress the occurrence of flicker, and therefore can suppress heat generation of the source driver without degrading the display quality.
The liquid crystal display panel having the TFT substrate 10C1 has a two-side input driving structure, and thus the charging capability required for each source driver is reduced as compared with the liquid crystal display panel having a one-side input driving structure. That is, the liquid crystal display panel having the TFT substrate 10C1 has a higher charging capability than the liquid crystal display panel having the one-side input drive structure.
Fig. 10 shows waveforms of voltages supplied to the 1 st source bus lines sa (n), the 2 nd source bus lines sb (n), and the gate bus lines g (m). Among the display signal voltages supplied to the source bus lines sa (n), sb (n), the 1 st display signal voltage is indicated by a solid line, and the 2 nd display signal voltage is indicated by a broken line. As shown in fig. 9, the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines sa (n), sb (n) are respectively reversed in polarity every 1 vertical scanning period (1V).
In the above example, the liquid crystal display panel having the TFT substrate 10C1 exhibits a dot inversion state (1 row 1 column dot inversion state), but the present embodiment is not limited thereto. As described below, the liquid crystal display panel of the present embodiment may exhibit a dot inversion state of N rows and 1 column (N is an integer of 2 or more). A case where N is 2 will be described with reference to fig. 11, and a case where N is 3 or more will be described with reference to fig. 12.
Another example of the present embodiment will be described with reference to fig. 11. Fig. 11 is a schematic plan view of the TFT substrate 10C2 used in the liquid crystal display panel of embodiment 3, and is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14a and 14b, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period.
As shown in fig. 11, the liquid crystal display panel having the TFT substrate 10C2 exhibits a2 row 1 column dot inversion state, which is different from the liquid crystal display panel having the TFT substrate 10C 1. That is, in each pixel column (an nth pixel column) of the TFT substrate 10C2, the transistors 18a and 18b connected to 2 pixels adjacent to each other are connected to the 1 st source bus line 14a arranged corresponding to the pixel column (the nth pixel column), and the transistors 18a and 18b connected to 2 pixels adjacent to each other, which are adjacent to the 2 pixels in the column direction, are connected to the 2 nd source bus line 14b arranged corresponding to the pixel column (the nth pixel column).
The liquid crystal display panel having the TFT substrate 10C2 may be the same as the liquid crystal display panel having the TFT substrate 10C1, except for the electrical connection relationship between the transistors and the source bus lines of each pixel. The various voltages used for driving the liquid crystal display panel having the TFT substrate 10C2 may be the same as those used for driving the liquid crystal display panel having the TFT substrate 10C1 shown in fig. 10.
The liquid crystal display panel having the TFT substrate 10C2 has a two-side input driving structure, and thus the charging capability required for each source driver is reduced as compared with the liquid crystal display panel having a one-side input driving structure.
In the liquid crystal display panel having the TFT substrate 10C2, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14b in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel having the TFT substrate 10C2, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14b differ in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation of the source driver is suppressed.
The liquid crystal display panel having the TFT substrate 10C2 exhibits a dot inversion state of 2 rows and 1 columns in each vertical scanning period, and therefore flicker is suppressed. However, as long as the resolution is the same, the dot inversion state of 1 row and 1 column is more preferable than the dot inversion state of 2 row and 1 column from the viewpoint of suppressing the occurrence of flicker.
Still another example of the present embodiment will be described with reference to fig. 12. Fig. 12 is a schematic plan view of the TFT substrate 10C3 used in the liquid crystal display panel of embodiment 3, and is a diagram showing the electrical connection relationship between the transistors of each pixel and the gate bus lines 12 and the source bus lines 14a and 14b, and the polarity of the display signal voltage applied to each pixel in a certain vertical scanning period.
As shown in fig. 12, the liquid crystal display panel having the TFT substrate 10C3 is different from the liquid crystal display panel having the TFT substrate 10C1 in that the liquid crystal display panel has an N row 1 column dot inversion state (N is an integer of 3 or more). That is, in each pixel column (an nth pixel column) of the TFT substrate 10B3, the transistors 18a and 18B connected to N pixels adjacent to each other are connected to the 1 st source bus line 14a arranged corresponding to the pixel column (the nth pixel column), and the transistors 18a and 18B connected to N pixels adjacent to each other and adjacent to the N pixels in the column direction are connected to the 2 nd source bus line 14B arranged corresponding to the pixel column (the nth pixel column). The liquid crystal display panel having the TFT substrate 10C3 may be the same as the liquid crystal display panel having the TFT substrate 10C1, except for the electrical connection relationship between the transistors and the source bus lines of each pixel. The various voltages used for driving the liquid crystal display panel having the TFT substrate 10C3 may be the same as those used for driving the liquid crystal display panel having the TFT substrate 10C1 shown in fig. 10.
The liquid crystal display panel having the TFT substrate 10C3 has a two-side input driving structure, and thus the charging capability required for each source driver is reduced as compared with the liquid crystal display panel having a one-side input driving structure.
In the liquid crystal display panel having the TFT substrate 10C3, the polarities of the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14b in a superimposed manner do not change in each vertical scanning period. In the liquid crystal display panel having the TFT substrate 10C3, the frequency at which the 1 st display signal voltage and the 2 nd display signal voltage supplied to the source bus lines 14a and 14b differ in polarity is lower than that of the liquid crystal display panel of comparative example 1, and therefore heat generation of the source driver is suppressed.
The liquid crystal display panel having the TFT substrate 10C3 exhibits an N row 1 column dot inversion state in each vertical scanning period, and therefore flicker is suppressed. As long as the resolution is the same, the dot inversion state of 1 row and 1 column is more preferable than the dot inversion state of N row and 1 column from the viewpoint of suppressing the occurrence of flicker. However, in a high-definition display panel having a resolution exceeding FHD (pixel number of 1080 rows × 1920 columns), such as 4K (pixel number of about 2000 rows × about 4000 columns), 8K (pixel number of about 4000 rows × about 8000 columns), there are cases where: even if inversion is performed for each of a plurality of lines, flicker is not visually recognized, and there is almost no problem in display quality. In order to suppress flicker, when the pixel rows of the plurality of pixels defining the display region 10d are m rows, N in the N row-1 column dot inversion state is preferably an integer equal to or less than 2 times the quotient of m divided by 1080, for example.
(embodiment mode 4)
A liquid crystal display panel 200 and a correction method thereof according to embodiment 4 of the present invention will be described with reference to fig. 13. Fig. 13 is a schematic plan view of a liquid crystal display panel 200 according to embodiment 4 of the present invention. According to the liquid crystal display panel of embodiment 4, in addition to the problem 1 (the problem of excessive heat generation of the source driver), the problem that a dark portion is generated in the display region when the source bus line is disconnected (problem 2) can be solved.
As shown in fig. 13, the liquid crystal display panel 200 further includes a plurality of 1 st buffer circuits 34a provided in the 1 st frame region 20a and a plurality of 2 nd buffer circuits 34b provided in the 2 nd frame region 20 b. Each 1 st buffer circuit 34a of the plurality of 1 st buffer circuits 34a is provided in correspondence with the associated plurality of source bus lines of each 1 st source driver 35a of the plurality of 1 st source drivers 35a and 35a of the plurality of 1 st source drivers 35 a. Each 1 st buffer circuit 34a of the plurality of 1 st buffer circuits 34a includes a plurality of 1 st buffers 33 a. Each of the plurality of 2 nd buffer circuits 34b is provided in correspondence with the associated plurality of source bus lines of each of the plurality of 2 nd source drivers 35b and each of the plurality of 2 nd source drivers 35 b. Each of the 2 nd buffer circuits 34b of the plurality of 2 nd buffer circuits 34b includes a plurality of 2 nd buffers 33 b.
Regarding the 1 st buffer circuit 34a, the arrangement corresponding to the plurality of source bus lines associated with each 1 st source driver 35a of the plurality of 1 st source drivers 35a and each 1 st source driver 35a of the plurality of 1 st source drivers 35a means that the input wiring and the output wiring of the 1 st buffer circuit 34a are arranged so as to be electrically connectable to 1 source bus line arbitrarily selected from the associated plurality of source bus lines. Regarding the 2 nd buffer circuit 34b, the arrangement corresponding to the plurality of source bus lines associated with each of the 2 nd source drivers 35b of the plurality of 2 nd source drivers 35b and each of the 2 nd source drivers 35b of the plurality of 2 nd source drivers 35b means that the input wiring and the output wiring of the 2 nd buffer circuit 34b are arranged so as to be electrically connectable to 1 source bus line arbitrarily selected from the associated plurality of source bus lines.
The liquid crystal display panel 200 is different from the liquid crystal display panel of any one of embodiments 1 to 3 in that it further includes the 1 st buffer circuit 34a and the 2 nd buffer circuit 34 b. For example, the liquid crystal display panel 200 has a single source structure, but the liquid crystal display panel of the present embodiment is not limited thereto, and may have a double source structure. The 1 st buffer circuit 34a and the 2 nd buffer circuit 34b may be collectively referred to as a buffer circuit, and the 1 st buffer and the 2 nd buffer may be collectively referred to as a buffer (buffer amplifier).
As described in patent document 1, in the liquid crystal display panel having the double-side input drive structure, since the display signal voltage is supplied from both sides (for example, up and down) of each source bus line, the display signal voltage can be supplied to each pixel even if the source bus line is disconnected. However, according to the research of the inventors of the present invention, in the liquid crystal display panel having the both-side input driving structure, when the source bus line is disconnected, a dark portion may be generated in the display region of the liquid crystal display panel. This is because, in the source bus line 14s in which the disconnection 14f occurs, the vibration waveform of the display signal voltage supplied to the longer one of the distance from the portion in which the disconnection 14f occurs to the 1 st source driver 35a and the distance from the portion in which the disconnection 14f occurs to the 2 nd source driver 35b is blunted. That is, when the distance is long, the CR product (product of capacitance and resistance) of the source bus line is large, and thus the vibration waveform of the display signal voltage may be blunted. The generation of a dark portion in the display area is remarkable in, for example, a high-definition and/or large-sized liquid crystal display panel. This is because, in a high-definition and/or large-sized liquid crystal display panel, the charging capability required for each source driver is increased.
In the liquid crystal display panel 200 according to embodiment 4, the output from the source driver located farther from the source bus line where the disconnection has occurred is output through the buffer circuit among the outputs to the source bus line where the disconnection has occurred, and thus the voltage drop can be compensated for. According to the liquid crystal display panel 200 or the correction method using the liquid crystal display panel 200, even if a disconnection occurs in the source bus line, a dark portion can be prevented from being generated in the display region.
In the liquid crystal display panel 200, when the disconnection 14f occurs in 1 of the plurality of source bus lines 14s and the distance from the portion where the disconnection 14f occurs to the 1 st source driver 35a is longer than the distance from the portion where the disconnection 14f occurs to the 2 nd source driver 35b, the source bus line 14s where the disconnection 14f occurs is connected to the 1 st buffer 33a of the plurality of 1 st buffers 33 a. When a disconnection 14f occurs in 1 source bus line 14s among the plurality of source bus lines 14s and the distance from the location where the disconnection 14f occurs to the 2 nd source driver 35b is longer than the distance from the location where the disconnection 14f occurs to the 1 st source driver 35a, the source bus line 14s where the disconnection 14f occurs is connected to the 1 nd buffer 33b among the plurality of 2 nd buffers 33 b.
For example, as shown in fig. 13, in the source bus line 14s in which the disconnection 14f (1) occurs, the distance between the 2 nd source driver 35b and the portion in which the disconnection 14f (1) occurs is larger in the 1 st source driver 35a and the 2 nd source driver 35b connected to the source bus line 14 s. Therefore, the source bus line 14s in which the disconnection 14f (1) occurs is connected to the 2 nd buffer 33 b.
The source bus line 14s on which the disconnection 14f (1) occurs and the 2 nd buffer 33b are connected, for example, as follows. The source bus line 14s in which the disconnection 14f (1) has occurred is cut at the cutting point 14 c. The 2 nd buffer circuit 34b includes, for example, a2 nd buffer 33b, an input wiring 37, and an output wiring 38. The source bus line 14s and the input wiring 37 in which the disconnection 14f (1) has occurred are connected to each other by a connection point 14m1 formed by melting the intersection of these lines. The source bus line 14s and the output wiring 38 in which the disconnection 14f (1) has occurred are connected to each other by a connection point 14m2 formed by melting the intersection of these lines. The cutting point 14c and the connection points 14m1 and 14m2 are formed using, for example, a known laser repair device.
As shown in fig. 13, in the source bus line 14s in which the disconnection 14f (2) occurs, the distance from the portion in which the disconnection 14f (2) occurs to the 1 st source driver 35a is equal to the distance from the portion in which the disconnection 14f (2) occurs to the 2 nd source driver 35 b. In this case, neither the 1 st buffer 33a nor the 2 nd buffer 33b may be used. This is because the product of the source bus lines CR of the 1 st source driver 35a and the product of the source bus lines CR of the 2 nd source driver 35b are equal in the source bus lines 14s in which the disconnection 14f (2) occurs. However, for example, when the display of the liquid crystal display panel 200 is confirmed, either the 1 st buffer 33a or the 2 nd buffer 33b may be selected as necessary and connected to the source bus line 14s in which the disconnection 14f (2) occurs, or both the 1 st buffer 33a and the 2 nd buffer 33b may be connected to the source bus line 14s in which the disconnection 14f (2) occurs.
The arrangement of the input wiring 37 and the output wiring 38 of the buffer circuits 34a and 34b will be described with reference to (a) to (c) of fig. 14. Fig. 14 (a) and (b) each show an example of a schematic plan view of the 2 nd buffer circuit 34b, and fig. 14 (c) is an enlarged view of a part of fig. 14 (a). Fig. 14 shows an example of the 2 nd buffer circuit 34b, but the 1 st buffer circuit 34a typically has the same configuration as the 2 nd buffer circuit 34b, and therefore, description thereof is omitted.
As shown in (a) and (b) of fig. 14, the 2 nd buffer circuit 34b has, for example, 2 nd buffers 33b (1), 33b (2). For example, in the 2 nd frame region 20b, a plurality of the 2 nd buffer circuits 34b and the 2 nd source driver 35b are provided as shown in the figure, respectively. In the illustrated example, 2 disconnected source bus lines 14s out of the source bus lines 14s connected to the 2 nd source driver 35b can be corrected at most.
As shown in fig. 14 (c), it is preferable to add an identification symbol (for example, a number, a character, a symbol, or the like) to the source bus line 14s for easily identifying the source bus line 14s to be corrected and the buffer 33b connected to the source bus line 14 s. This can improve correction efficiency. For example, "956" to "960" in fig. 14 (c) are numbers numbering the respective source bus lines 14 s. "B1" and "B2" in fig. 14 (c) are symbols numbering the 2 nd buffer 33B (1) and the 2 nd buffer 33B (2).
As compared with the arrangement shown in fig. 14 (b), as shown in fig. 14 (a), the input wiring 37 and the output wiring 38 connected to the respective 2 nd buffers 33b (1) and 33b (2) are preferably arranged adjacent to each other. In the example of fig. 14 (a), 1 disconnection point 14c and 2 connection points 14m1 and 14m2 are formed to connect the source bus line 14s in which the disconnection 14f occurs and the 2 nd buffer 33b (2). At this time, as shown in (a) and (c) of fig. 14, the identification code for identifying the source bus line 14s in which the disconnection 14f has occurred and the identification code for identifying the 2 nd buffer 33b (2) connected to the source bus line 14s are close to each other to the disconnection point 14c and the connection points 14m1, 14m2, and therefore, the efficiency of the correction operation is improved. The improvement in the efficiency of the correction work also reduces the risk of erroneous disconnection, erroneous connection, and the like. From the viewpoint of improving the efficiency of the correction work, for example, it is preferable that the identifier, the cutting point, and the connection point are in the same field of view of the microscope for checking the correction position. Even if the identifier, the cutting point, and the connection point are not in the same field of view, if they are close to each other, the distance of movement of the field of view for confirming them and the distance of movement of the laser beam for forming the cutting point and the connection point are short, and therefore the efficiency of the correction work is improved.
On the other hand, as shown in fig. 14 (b), when the input wiring 37 connected to the 2 nd buffer 33b (1) and the input wiring 37 connected to the 2 nd buffer 33b (2) are arranged adjacent to each other, and the output wiring 38 connected to the 2 nd buffer 33b (1) and the output wiring 38 connected to the 2 nd buffer 33b (2) are arranged adjacent to each other, the identification symbol for identifying the source bus line 14s in which the disconnection 14f has occurred and the identification symbol for identifying the 2 nd buffer 33b (2) connected to the source bus line 14s are arranged apart from the disconnection point 14c and the connection points 14m1, 14m 2. Any 1 of the 2 cutting points 14c shown in fig. 14 (b) may be formed. In the case of the arrangement shown in fig. 14 (b), the identifier, the cutting point, and the connection point may not be included in the same field of view of the microscope for confirming the corrected position. Further, since the distance of moving the field of view for checking the identification symbol, the cutting point, and the connection point, and the distance of moving the laser beam for forming the cutting point and the connection point are long, the efficiency of the correction work is reduced, and the risk of erroneous cutting, erroneous connection, and the like may increase.
As shown in fig. 13 and 14, the 2 nd buffer circuit 34b further includes an additional wiring 39 connected to a power supply 39p, for example. Fig. 15 (a) also shows an example of a circuit diagram of the 2 nd buffer circuit 34 b. Fig. 15 (b) shows another example of the circuit diagram of the 2 nd buffer circuit 34 b.
As shown in fig. 13 to 14 and (a) of fig. 15, the 2 nd buffer 33b connected to the additional wiring 39 is in a non-operating state. By cutting the additional wiring 39 at the cutting point 39c, the 2 nd buffer 33b is electrically independent from the power supply 39p, and thus the 2 nd buffer 33b can be switched to an operating state. That is, the additional wiring 39 functions as a switching mechanism that controls switching from a state in which the 2 nd buffer 33b does not operate to a state in which the 2 nd buffer 33b operates. If each of the 2 nd buffers 33b has a switching mechanism, only the buffer connected to the source bus line can be selectively brought into an operable state, while the other buffers can be kept in an inoperable state as they are. For example, the plurality of 1 st and 2 nd buffers 33a and 33b included in the 1 st and 2 nd buffer circuits 34a and 34b provided corresponding to the source bus line 14s in which the disconnection 14f does not occur among the plurality of source bus lines 14s are in a non-operating state.
Here, although the switching mechanism included in the 2 nd snubber circuit is described, the 1 st snubber circuit also includes the same switching mechanism. The switching mechanism included in the 1 st snubber circuit is referred to as a1 st switching mechanism, and the switching mechanism included in the 2 nd snubber circuit is referred to as a2 nd switching mechanism.
If the buffer circuit has a switch mechanism, the buffer not in use can be prevented from malfunction. In particular, as shown in fig. 14 (a), it is considered that when the input wiring 37 and the output wiring 38 connected to the 2 nd buffers 33b (1) and 33b (2) are disposed adjacent to each other, malfunction (for example, oscillation of the buffer circuit 34 b) is likely to occur. This is because parasitic capacitance is formed between the input wiring 37 and the output wiring 38, and the input wiring 37 and the output wiring 38 may be coupled by the parasitic capacitance. When the buffer 33b malfunctions, noise and heat are generated. Therefore, in the case where the input wiring and the output wiring connected to the respective buffers are disposed adjacent to each other, it is particularly preferable that each buffer circuit has a switching mechanism.
In a liquid crystal display panel having a one-side input drive structure, there is no motivation to arrange input wirings and output wirings of a buffer circuit adjacent to each other. In the liquid crystal display panel having the one-side input drive structure, even if the input wiring and the output wiring of the buffer circuit are disposed adjacent to each other, the correction efficiency is not improved as described below. Therefore, the problem that the buffer may malfunction may not occur in the liquid crystal display panel having the one-side input driving structure.
In a liquid crystal display panel having a one-side input driving structure, a source driver is provided only in a one-side (e.g., upper) region of a display region. When a disconnection occurs in the source bus line, the display signal voltage from the source driver is supplied directly to one end of the source bus line, and the display signal voltage from the source driver is supplied to the other end of the source bus line via a spare wiring provided outside the display area. In a path supplied through the spare wiring, in order to compensate for a voltage drop caused by the spare wiring, an output from the source driver is output to the source bus line via a buffer circuit. The input wiring and the output wiring of the buffer circuit are connected to the source bus lines on both sides of the display region. That is, 2 connection points formed to connect the source bus line and the buffer are provided on both sides of the display region, for example, in an upper region and a lower region separately. Even if the input wiring and the output wiring of the buffer circuit are disposed adjacent to each other, the 2 connection points are disposed apart from each other, and therefore the improvement of the correction work efficiency is not brought about.
The switch mechanism is not limited to the above example. For example, as shown in fig. 15 (b), the snubber circuit may have a switch 41 as a switching mechanism. The switch 41 may be a switch that physically switches on/off, or may be a switch that receives a signal for controlling on/off from a control board and switches on/off.
(embodiment 5)
Hereinafter, an active matrix substrate (TFT substrate) used for a liquid crystal display panel according to embodiment 5 of the present invention will be described with reference to the drawings. The active matrix substrate of the present embodiment is an active matrix substrate including an oxide semiconductor TFT and a crystalline silicon TFT formed on the same substrate.
The active matrix substrate includes a TFT (pixel TFT) for each pixel. For example, an oxide semiconductor TFT having an In-Ga-Zn-O semiconductor film as an active layer is used as the pixel TFT.
Some or all of the peripheral driver circuits may be integrally formed on the same substrate as the pixel TFTs. Such an active matrix substrate is referred to as a driver-monolithic active matrix substrate. In an active matrix substrate on which a driver is monolithic, a peripheral driver circuit is provided in a region (non-display region or frame region) other than a region (display region) including a plurality of pixels. As a TFT (circuit TFT) constituting the peripheral driver circuit, for example, a crystalline silicon TFT having a polysilicon film as an active layer is used. In this way, when an oxide semiconductor TFT is used as a pixel TFT and a crystalline silicon TFT is used as a circuit TFT, power consumption can be reduced in a display region and a frame region can be reduced.
Next, a more specific configuration of the active matrix substrate of the present embodiment will be described with reference to the drawings.
Fig. 17 is a cross-sectional view showing a cross-sectional structure of a crystalline silicon TFT (hereinafter referred to as a "1 st thin film transistor") 710A and an oxide semiconductor TFT (hereinafter referred to as a "2 nd thin film transistor") 710B in an active matrix substrate (TFT substrate) 700 according to this embodiment.
The active matrix substrate 700 includes a display region 702 including a plurality of pixels and a region (non-display region) other than the display region 702. The non-display region includes a driving circuit forming region 701 in which a driving circuit is disposed. In the drive circuit forming region 701, a part or all of the gate driver circuit included in the gate driver 32 shown in fig. 1 is provided. In the driving circuit forming region 701, a part or all of the source driver circuits included in the 1 st source driver 35a and the 2 nd source driver 35b shown in fig. 1 may be further provided.
As shown in fig. 17, in the active matrix substrate 700, a2 nd thin film transistor 710B as a pixel TFT is formed in each pixel of the display region 702, and a1 st thin film transistor 710A as a circuit TFT is formed in the driver circuit formation region 701.
This embodiment mode can be applied to the liquid crystal panel of any of the foregoing embodiment modes. For example, the 2 nd thin film transistor 710B of the present embodiment can be used as the transistors 18a and 18B described above with reference to fig. 2 to 5, 7 to 9, 11, and 12.
The active matrix substrate 700 includes: a substrate 711; a base film 712 formed over a surface of a substrate 711; a1 st thin film transistor 710A formed over a base film 712; and a2 nd thin film transistor 710B formed over the base film 712. The 1 st thin film transistor 710A is a crystalline silicon TFT having an active region mainly containing crystalline silicon. The 2 nd thin film transistor 710B is an oxide semiconductor TFT having an active region mainly containing an oxide semiconductor. The 1 st thin film transistor 710A and the 2 nd thin film transistor 710B are integrally formed on the substrate 711. The "active region" referred to herein means a region in which a channel is formed in a semiconductor layer which is an active layer of a TFT.
The 1 st thin film transistor 710A has a crystalline silicon semiconductor layer (e.g., a low-temperature polysilicon layer) 713 formed over a base film 712; a1 st insulating layer 714 covering the crystalline silicon semiconductor layer 713; and a gate electrode 715A provided on the 1 st insulating layer 714. A portion of the 1 st insulating layer 714 located between the crystalline silicon semiconductor layer 713 and the gate electrode 715A functions as a gate insulating film of the 1 st thin film transistor 710A. The crystalline silicon semiconductor layer 713 has a region (active region) 713c where a channel is formed and a source region 713s and a drain region 713d which are located on both sides of the active region, respectively. In this example, a portion of the crystalline silicon semiconductor layer 713 which overlaps with the gate electrode 715A with the 1 st insulating layer 714 interposed therebetween is an active region 713 c. The 1 st thin film transistor 710A further has a source electrode 718sA and a drain electrode 718dA connected to the source region 713s and the drain region 713d, respectively. The source electrode 718sA and the drain electrode 718dA may be provided on an interlayer insulating film (here, the 2 nd insulating layer 716) covering the gate electrode 715A and the crystalline silicon semiconductor layer 713, and may be connected to the crystalline silicon semiconductor layer 713 through a contact hole formed in the interlayer insulating film.
The 2 nd thin film transistor 710B has: a gate electrode 715B provided over the base film 712; a2 nd insulating layer 716 covering the gate electrode 715B; and an oxide semiconductor layer 717 disposed on the 2 nd insulating layer 716. As shown in the figure, the 1 st insulating layer 714 which is a gate insulating film of the 1 st thin film transistor 710A may be extended to a region where the 2 nd thin film transistor 710B is to be formed. In this case, the oxide semiconductor layer 717 may be formed over the 1 st insulating layer 714. A portion of the 2 nd insulating layer 716 located between the gate electrode 715B and the oxide semiconductor layer 717 functions as a gate insulating film of the 2 nd thin film transistor 710B. The oxide semiconductor layer 717 has a region (active region) 717c where a channel is formed, and a source contact region 717s and a drain contact region 717d which are located on both sides of the active region, respectively. In this example, a portion of the oxide semiconductor layer 717 which overlaps with the gate electrode 715B with the 2 nd insulating layer 716 interposed therebetween is an active region 717 c. In addition, the 2 nd thin film transistor 710B also has a source electrode 718sB and a drain electrode 718dB connected to the source contact region 717s and the drain contact region 717d, respectively. Further, the base film 712 may not be provided over the substrate 711.
The thin film transistors 710A and 710B are covered with a passivation film 719 and a planarization film 720. In the 2 nd thin film transistor 710B functioning as a pixel TFT, the gate electrode 715B is connected to a gate bus line (not shown), the source electrode 718sB is connected to a source bus line (not shown), and the drain electrode 718dB is connected to the pixel electrode 723. In this example, the drain electrode 718dB is connected to the corresponding pixel electrode 723 in the opening portion formed in the passivation film 719 and the planarization film 720. A video signal is supplied to the source electrode 718sB through a source bus line, and necessary electric charges are written to the pixel electrode 723 based on a gate signal from a gate bus line.
Further, as shown in the figure, a transparent conductive layer 721 which is a common electrode may be formed on the planarization film 720, and a3 rd insulating layer 722 may be formed between the transparent conductive layer (common electrode) 721 and the pixel electrode 723. In this case, a slit-shaped opening may be provided in the pixel electrode 723. Such an active matrix substrate 700 can be applied to, for example, an FFS (fringe field Switching) mode display device.
In the illustrated example, the 1 st thin film transistor 710A has a top gate structure in which a crystalline silicon semiconductor layer 713 is provided between a gate electrode 715A and a substrate 711 (base film 712). On the other hand, the 2 nd thin film transistor 710B has a bottom-gate structure in which a gate electrode 715B is provided between the oxide semiconductor layer 717 and the substrate 711 (base film 712). With this structure, when the two types of thin film transistors 710A and 710B are formed integrally on the same substrate 711, the number of manufacturing steps and the increase in manufacturing cost can be suppressed more effectively.
The TFT structures of the 1 st and 2 nd thin film transistors 710A and 710B are not limited to the above.
Industrial applicability of the invention
The present invention can be widely used as a liquid crystal display panel and a correction method thereof, particularly as a large-sized liquid crystal display panel for a high definition television and a disconnection correction method of a source bus thereof.
Description of the reference numerals
10A 1-10A 3, 10B 1-10B 3, 10C 1- 10C 3, 10X TFT substrate
10d display area
12-gate bus
14a, 14b, 14s source bus lines (1 st, 2 nd source bus lines)
14c cutting point
14f wire breakage
14m1, 14m2 connection point
20a, 20b No. 1 and No. 2 frame area
32 gate driver
33a, 33b No. 1, 2 buffer
34a, 34b No. 1, 2 buffer circuit
35a, 35b 1 st and 2 nd source drivers
37 input wiring
38 output wiring
39 additional wiring
39c cutting point
100. 200 liquid crystal display panel.

Claims (53)

1. A liquid crystal display panel is characterized by comprising:
a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns;
a plurality of transistors connected to any 1 of the plurality of pixels, respectively;
a plurality of gate bus lines extending in a row direction and connected to any one of the plurality of transistors;
a plurality of source bus lines extending in the column direction and connected to any one of the plurality of transistors;
a plurality of 1 st source drivers provided in a1 st frame region above a display region divided by the plurality of pixels, for supplying a1 st display signal voltage to each of the plurality of source bus lines associated therewith; and
a plurality of 2 nd source drivers provided in a2 nd frame region below the display region and configured to supply a2 nd display signal voltage to each of the plurality of source bus lines associated therewith,
in each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines in a superimposed manner, and the polarities of the 1 st display signal voltage and the 2 nd display signal voltage are not changed in each vertical scanning period,
the liquid crystal display panel further includes:
a plurality of 1 st buffer circuits provided in the 1 st frame region, each of the 1 st buffer circuits being provided corresponding to each of the 1 st source drivers and the associated plurality of source buses of each of the 1 st source drivers, and including a plurality of 1 st buffers; and
a plurality of 2 nd buffer circuits provided in the 2 nd frame region, each of the 2 nd buffer circuits being provided corresponding to the associated plurality of source buses of each of the plurality of 2 nd source drivers and including a plurality of 2 nd buffers,
the input wiring and the output wiring connected to each 1 st buffer of the 1 st buffers are disposed adjacent to each other, and the input wiring and the output wiring connected to each 2 nd buffer of the 2 nd buffers are disposed adjacent to each other.
2. The liquid crystal display panel according to claim 1,
the plurality of source bus lines include 1 st source bus lines arranged corresponding to the respective pixel columns, the transistors connected to 2 pixels adjacent to each other in the row direction are connected to the 1 st source bus lines different from each other, and polarities of the 1 st display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period, and polarities of the 2 nd display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period.
3. The liquid crystal display panel according to claim 2,
the transistors connected to 2 pixels adjacent to each other in the column direction are connected to the 1 st source bus lines different from each other.
4. The liquid crystal display panel according to claim 2,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 1 st source bus line arranged corresponding to the pixel column adjacent to the pixel column, where N is 2 or more and an integer of 2 times or less a quotient obtained by dividing m by 1080.
5. The liquid crystal display panel according to claim 1,
the plurality of source bus lines include a1 st source bus line and a2 nd source bus line disposed corresponding to each pixel column, and the 1 st source bus line and the 2 nd source bus line have polarities of the 1 st display signal voltage supplied thereto in each vertical scanning period opposite to each other and have polarities of the 2 nd display signal voltage supplied thereto in each vertical scanning period opposite to each other.
6. The liquid crystal display panel according to claim 5,
in each vertical scanning period, the polarities of the 1 st display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other, and in each vertical scanning period, the polarities of the 2 nd display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other.
7. The liquid crystal display panel according to claim 6,
in each pixel row, one pixel of 2 pixels adjacent to each other in the row direction is connected to the 1 st source bus line, and the other pixel is connected to the 2 nd source bus line.
8. The liquid crystal display panel according to claim 6,
in each pixel row, 2 pixels adjacent to each other in the row direction are each connected to the 1 st source bus line or each connected to the 2 nd source bus line.
9. The liquid crystal display panel according to any one of claims 5 to 8,
in each pixel column, the transistor connected to a certain pixel is connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistor connected to a pixel adjacent to the certain pixel in the column direction is connected to the 2 nd source bus line arranged corresponding to the pixel column.
10. The liquid crystal display panel according to any one of claims 5 to 8,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 2 nd source bus line arranged corresponding to the pixel column, where N is an integer of 2 or more and 2 times or less a quotient of m divided by 1080.
11. The liquid crystal display panel according to any one of claims 1 to 8,
the number of the plurality of rows included in the plurality of pixels exceeds 1080.
12. The liquid crystal display panel according to any one of claims 1 to 8,
the plurality of 1 st buffers and the plurality of 2 nd buffers included in the 1 st buffer circuit and the 2 nd buffer circuit provided corresponding to the source bus line in which the disconnection does not occur among the plurality of source bus lines are in a non-operating state.
13. The liquid crystal display panel according to any one of claims 1 to 8,
each of the 1 st buffers includes a1 st switching mechanism, the 1 st switching mechanism controls switching from a state in which the 1 st buffer is not operated to a state in which the 1 st buffer is operated, and each of the 2 nd buffers includes a2 nd switching mechanism, and the 2 nd switching mechanism controls switching from a state in which the 2 nd buffer is not operated to a state in which the 2 nd buffer is operated.
14. A method of correcting a liquid crystal display panel according to any one of claims 1 to 13, comprising:
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 of the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the disconnected source bus line is connected to the 1 nd buffer from among the plurality of 2 nd buffers.
15. A method of correcting a liquid crystal display panel according to claim 13, comprising:
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the source bus line where the disconnection occurs is connected to 12 nd buffer among the plurality of 2 nd buffers,
the method for correcting the liquid crystal display panel further comprises the following steps:
switching from a state in which the 1 st buffer is not operated to a state in which the 1 st buffer is operated by operating the 1 st switching mechanism of the 1 st buffer connected to the source bus line in which the disconnection has occurred, or,
the state in which the 2 nd buffer is not operated is switched to the state in which the 2 nd buffer is operated by operating the 2 nd switching mechanism of the 2 nd buffer connected to the source bus line in which the disconnection has occurred.
16. A liquid crystal display panel is characterized by comprising:
a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns;
a plurality of transistors connected to any 1 of the plurality of pixels, respectively;
a plurality of gate bus lines extending in a row direction and connected to any one of the plurality of transistors;
a plurality of source bus lines extending in the column direction and connected to any one of the plurality of transistors;
a plurality of 1 st source drivers provided in a1 st frame region above a display region divided by the plurality of pixels, for supplying a1 st display signal voltage to each of the plurality of source bus lines associated therewith; and
a plurality of 2 nd source drivers provided in a2 nd frame region below the display region and configured to supply a2 nd display signal voltage to each of the plurality of source bus lines associated therewith,
in each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines in a superimposed manner, and the polarities of the 1 st display signal voltage and the 2 nd display signal voltage are not changed in each vertical scanning period,
the liquid crystal display panel further includes:
a plurality of 1 st buffer circuits provided in the 1 st frame region, each of the 1 st buffer circuits being provided corresponding to each of the 1 st source drivers and the associated plurality of source buses of each of the 1 st source drivers, and including a plurality of 1 st buffers; and
a plurality of 2 nd buffer circuits provided in the 2 nd frame region, each of the 2 nd buffer circuits being provided corresponding to the associated plurality of source buses of each of the plurality of 2 nd source drivers and including a plurality of 2 nd buffers,
the plurality of 1 st buffers and the plurality of 2 nd buffers included in the 1 st buffer circuit and the 2 nd buffer circuit provided corresponding to the source bus line in which the disconnection does not occur among the plurality of source bus lines are in a non-operating state.
17. The liquid crystal display panel according to claim 16,
the plurality of source bus lines include 1 st source bus lines arranged corresponding to the respective pixel columns, the transistors connected to 2 pixels adjacent to each other in the row direction are connected to the 1 st source bus lines different from each other, and polarities of the 1 st display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period, and polarities of the 2 nd display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period.
18. The liquid crystal display panel according to claim 17,
the transistors connected to 2 pixels adjacent to each other in the column direction are connected to the 1 st source bus lines different from each other.
19. The liquid crystal display panel according to claim 17,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 1 st source bus line arranged corresponding to the pixel column adjacent to the pixel column, where N is 2 or more and an integer of 2 times or less a quotient obtained by dividing m by 1080.
20. The liquid crystal display panel according to claim 16,
the plurality of source bus lines include a1 st source bus line and a2 nd source bus line disposed corresponding to each pixel column, and the 1 st source bus line and the 2 nd source bus line have polarities of the 1 st display signal voltage supplied thereto in each vertical scanning period opposite to each other and have polarities of the 2 nd display signal voltage supplied thereto in each vertical scanning period opposite to each other.
21. The liquid crystal display panel according to claim 20,
in each vertical scanning period, the polarities of the 1 st display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other, and in each vertical scanning period, the polarities of the 2 nd display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other.
22. The liquid crystal display panel according to claim 21,
in each pixel row, one pixel of 2 pixels adjacent to each other in the row direction is connected to the 1 st source bus line, and the other pixel is connected to the 2 nd source bus line.
23. The liquid crystal display panel according to claim 21,
in each pixel row, 2 pixels adjacent to each other in the row direction are each connected to the 1 st source bus line or each connected to the 2 nd source bus line.
24. The liquid crystal display panel according to any one of claims 20 to 23,
in each pixel column, the transistor connected to a certain pixel is connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistor connected to a pixel adjacent to the certain pixel in the column direction is connected to the 2 nd source bus line arranged corresponding to the pixel column.
25. The liquid crystal display panel according to any one of claims 20 to 23,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 2 nd source bus line arranged corresponding to the pixel column, where N is an integer of 2 or more and 2 times or less a quotient of m divided by 1080.
26. The liquid crystal display panel according to any one of claims 16 to 23,
the number of the plurality of rows included in the plurality of pixels exceeds 1080.
27. The liquid crystal display panel according to any one of claims 16 to 23,
each of the 1 st buffers includes a1 st switching mechanism, the 1 st switching mechanism controls switching from a state in which the 1 st buffer is not operated to a state in which the 1 st buffer is operated, and each of the 2 nd buffers includes a2 nd switching mechanism, and the 2 nd switching mechanism controls switching from a state in which the 2 nd buffer is not operated to a state in which the 2 nd buffer is operated.
28. A method of correcting a liquid crystal display panel according to any one of claims 16 to 27, comprising:
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 of the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the disconnected source bus line is connected to the 1 nd buffer from among the plurality of 2 nd buffers.
29. A method of correcting a liquid crystal display panel according to claim 27, comprising:
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the source bus line where the disconnection occurs is connected to 12 nd buffer among the plurality of 2 nd buffers,
the method for correcting the liquid crystal display panel further comprises the following steps:
switching from a state in which the 1 st buffer is not operated to a state in which the 1 st buffer is operated by operating the 1 st switching mechanism of the 1 st buffer connected to the source bus line in which the disconnection has occurred, or,
the state in which the 2 nd buffer is not operated is switched to the state in which the 2 nd buffer is operated by operating the 2 nd switching mechanism of the 2 nd buffer connected to the source bus line in which the disconnection has occurred.
30. A liquid crystal display panel is characterized by comprising:
a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns;
a plurality of transistors connected to any 1 of the plurality of pixels, respectively;
a plurality of gate bus lines extending in a row direction and connected to any one of the plurality of transistors;
a plurality of source bus lines extending in the column direction and connected to any one of the plurality of transistors;
a plurality of 1 st source drivers provided in a1 st frame region above a display region divided by the plurality of pixels, for supplying a1 st display signal voltage to each of the plurality of source bus lines associated therewith; and
a plurality of 2 nd source drivers provided in a2 nd frame region below the display region and configured to supply a2 nd display signal voltage to each of the plurality of source bus lines associated therewith,
in each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines in a superimposed manner, and the polarities of the 1 st display signal voltage and the 2 nd display signal voltage are not changed in each vertical scanning period,
the liquid crystal display panel further includes:
a plurality of 1 st buffer circuits provided in the 1 st frame region, each of the 1 st buffer circuits being provided corresponding to each of the 1 st source drivers and the associated plurality of source buses of each of the 1 st source drivers, and including a plurality of 1 st buffers; and
a plurality of 2 nd buffer circuits provided in the 2 nd frame region, each of the 2 nd buffer circuits being provided corresponding to the associated plurality of source buses of each of the plurality of 2 nd source drivers and including a plurality of 2 nd buffers,
each of the 1 st buffers includes a1 st switching mechanism, the 1 st switching mechanism controls switching from a state in which the 1 st buffer is not operated to a state in which the 1 st buffer is operated, and each of the 2 nd buffers includes a2 nd switching mechanism, and the 2 nd switching mechanism controls switching from a state in which the 2 nd buffer is not operated to a state in which the 2 nd buffer is operated.
31. The liquid crystal display panel according to claim 30,
the plurality of source bus lines include 1 st source bus lines arranged corresponding to the respective pixel columns, the transistors connected to 2 pixels adjacent to each other in the row direction are connected to the 1 st source bus lines different from each other, and polarities of the 1 st display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period, and polarities of the 2 nd display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period.
32. The liquid crystal display panel according to claim 31,
the transistors connected to 2 pixels adjacent to each other in the column direction are connected to the 1 st source bus lines different from each other.
33. The liquid crystal display panel according to claim 31,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 1 st source bus line arranged corresponding to the pixel column adjacent to the pixel column, where N is 2 or more and an integer of 2 times or less a quotient obtained by dividing m by 1080.
34. The liquid crystal display panel according to claim 30,
the plurality of source bus lines include a1 st source bus line and a2 nd source bus line disposed corresponding to each pixel column, and the 1 st source bus line and the 2 nd source bus line have polarities of the 1 st display signal voltage supplied thereto in each vertical scanning period opposite to each other and have polarities of the 2 nd display signal voltage supplied thereto in each vertical scanning period opposite to each other.
35. The liquid crystal display panel of claim 34,
in each vertical scanning period, the polarities of the 1 st display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other, and in each vertical scanning period, the polarities of the 2 nd display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other.
36. The liquid crystal display panel according to claim 35,
in each pixel row, one pixel of 2 pixels adjacent to each other in the row direction is connected to the 1 st source bus line, and the other pixel is connected to the 2 nd source bus line.
37. The liquid crystal display panel according to claim 35,
in each pixel row, 2 pixels adjacent to each other in the row direction are each connected to the 1 st source bus line or each connected to the 2 nd source bus line.
38. The liquid crystal display panel according to any one of claims 34 to 37,
in each pixel column, the transistor connected to a certain pixel is connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistor connected to a pixel adjacent to the certain pixel in the column direction is connected to the 2 nd source bus line arranged corresponding to the pixel column.
39. The liquid crystal display panel according to any one of claims 34 to 37,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 2 nd source bus line arranged corresponding to the pixel column, where N is an integer of 2 or more and 2 times or less a quotient of m divided by 1080.
40. The liquid crystal display panel according to any one of claims 30 to 37,
the number of the plurality of rows included in the plurality of pixels exceeds 1080.
41. A method of correcting a liquid crystal display panel according to any one of claims 30 to 40, comprising:
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 of the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the disconnected source bus line is connected to the 1 nd buffer from among the plurality of 2 nd buffers.
42. A method of correcting a liquid crystal display panel according to any one of claims 30 to 40, comprising:
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the source bus line where the disconnection occurs is connected to 12 nd buffer among the plurality of 2 nd buffers,
the method for correcting the liquid crystal display panel further comprises the following steps:
switching from a state in which the 1 st buffer is not operated to a state in which the 1 st buffer is operated by operating the 1 st switching mechanism of the 1 st buffer connected to the source bus line in which the disconnection has occurred, or,
the state in which the 2 nd buffer is not operated is switched to the state in which the 2 nd buffer is operated by operating the 2 nd switching mechanism of the 2 nd buffer connected to the source bus line in which the disconnection has occurred.
43. A method for correcting a liquid crystal display panel is characterized in that,
the liquid crystal display panel includes:
a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns;
a plurality of transistors connected to any 1 of the plurality of pixels, respectively;
a plurality of gate bus lines extending in a row direction and connected to any one of the plurality of transistors;
a plurality of source bus lines extending in the column direction and connected to any one of the plurality of transistors;
a plurality of 1 st source drivers provided in a1 st frame region above a display region divided by the plurality of pixels, for supplying a1 st display signal voltage to each of the plurality of source bus lines associated therewith; and
a plurality of 2 nd source drivers provided in a2 nd frame region below the display region and configured to supply a2 nd display signal voltage to each of the plurality of source bus lines associated therewith,
in each vertical scanning period, the 1 st display signal voltage and the 2 nd display signal voltage are supplied to each of the plurality of source bus lines in a superimposed manner, and the polarities of the 1 st display signal voltage and the 2 nd display signal voltage are not changed in each vertical scanning period,
the liquid crystal display panel further includes:
a plurality of 1 st buffer circuits provided in the 1 st frame region, each of the 1 st buffer circuits being provided corresponding to each of the 1 st source drivers and the associated plurality of source buses of each of the 1 st source drivers, and including a plurality of 1 st buffers; and
a plurality of 2 nd buffer circuits provided in the 2 nd frame region, each of the 2 nd buffer circuits being provided corresponding to the associated plurality of source buses of each of the plurality of 2 nd source drivers and including a plurality of 2 nd buffers,
the method for correcting the liquid crystal display panel comprises the following steps,
when 1 source bus line among the plurality of source bus lines is disconnected and the distance from the disconnection point to the 1 st source driver is greater than the distance from the disconnection point to the 2 nd source driver, the source bus line in which the disconnection occurs is connected to 1 st buffer among the plurality of 1 st buffers,
when 1 of the plurality of source bus lines is disconnected and the distance from the location where the disconnection occurs to the 2 nd source driver is greater than the distance from the location where the disconnection occurs to the 1 st source driver, the disconnected source bus line is connected to the 1 nd buffer from among the plurality of 2 nd buffers.
44. The correction method of the liquid crystal display panel according to claim 43,
the plurality of source bus lines include 1 st source bus lines arranged corresponding to the respective pixel columns, the transistors connected to 2 pixels adjacent to each other in the row direction are connected to the 1 st source bus lines different from each other, and polarities of the 1 st display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period, and polarities of the 2 nd display signal voltages supplied to the 21 st source bus lines adjacent to each other are opposite to each other in each vertical scanning period.
45. The correction method of the liquid crystal display panel according to claim 44,
the transistors connected to 2 pixels adjacent to each other in the column direction are connected to the 1 st source bus lines different from each other.
46. The correction method of the liquid crystal display panel according to claim 44,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 1 st source bus line arranged corresponding to the pixel column adjacent to the pixel column, where N is 2 or more and an integer of 2 times or less a quotient obtained by dividing m by 1080.
47. The correction method of the liquid crystal display panel according to claim 43,
the plurality of source bus lines include a1 st source bus line and a2 nd source bus line disposed corresponding to each pixel column, and the 1 st source bus line and the 2 nd source bus line have polarities of the 1 st display signal voltage supplied thereto in each vertical scanning period opposite to each other and have polarities of the 2 nd display signal voltage supplied thereto in each vertical scanning period opposite to each other.
48. The correction method of the liquid crystal display panel according to claim 47,
in each vertical scanning period, the polarities of the 1 st display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other, and in each vertical scanning period, the polarities of the 2 nd display signal voltages supplied to the 2 pixels adjacent to each other in the row direction are opposite to each other.
49. The correction method of the liquid crystal display panel according to claim 48,
in each pixel row, one pixel of 2 pixels adjacent to each other in the row direction is connected to the 1 st source bus line, and the other pixel is connected to the 2 nd source bus line.
50. The correction method of the liquid crystal display panel according to claim 48,
in each pixel row, 2 pixels adjacent to each other in the row direction are each connected to the 1 st source bus line or each connected to the 2 nd source bus line.
51. The correction method of the liquid crystal display panel according to any one of claims 47 to 50,
in each pixel column, the transistor connected to a certain pixel is connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistor connected to a pixel adjacent to the certain pixel in the column direction is connected to the 2 nd source bus line arranged corresponding to the pixel column.
52. The correction method of the liquid crystal display panel according to any one of claims 47 to 50,
when the plurality of rows included in the plurality of pixels are m rows, the transistors connected to N pixels adjacent to each other in each pixel column are connected to the 1 st source bus line arranged corresponding to the pixel column, and the transistors connected to N pixels adjacent to each other in the column direction and adjacent to the N pixels are connected to the 2 nd source bus line arranged corresponding to the pixel column, where N is an integer of 2 or more and 2 times or less a quotient of m divided by 1080.
53. The correction method of the liquid crystal display panel according to any one of claims 43 to 50,
the number of the plurality of rows included in the plurality of pixels exceeds 1080.
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