CN108139993B

CN108139993B - Memory device, memory controller, data cache device and computer system

Info

Publication number: CN108139993B
Application number: CN201680058607.2A
Authority: CN
Inventors: 肖世海; 杨伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-08-29
Filing date: 2016-08-29
Publication date: 2020-06-16
Anticipated expiration: 2036-08-29
Also published as: WO2018039855A1; CN108139993A

Abstract

A memory device, memory controller, data caching device and computer system, the memory device (20) comprising: an NVM (24); the NVM controller (22) is connected with the memory controller through a DDR bus, and the NVM controller (22) carries out access operation on the NVM (24) according to the command of the memory controller and carries out data transmission with the memory controller on part of DQS signal lines in the DDR bus. The memory device (20) transmits data by using a part of DQS signal lines in the DDR bus, and the problem that additional data cannot be transmitted between the memory controller and the memory device is solved.

Description

Memory device, memory controller, data cache device and computer system

Technical Field

The present invention relates to the field of computer storage, and in particular, to a memory device, a memory controller, a data cache device, and a computer system.

Background

With the development of technology, non-Volatile Memory (NVM), such as Phase Change Memory (PCM), is widely used. After the system is powered off, the NVM can still store data, and has the advantages of high density, good expandability and the like, so the NVM is considered to be capable of replacing a Dynamic Random Access Memory (DRAM) as a new Memory.

However, there are some gaps in the performance of NVM compared to DRAM, and it is difficult to fully comply with the existing Double Data Rate (DDR) standard. Specifically, the memory controller generally accesses data in the DRAM through the DDR bus, and the data read and write have a certain delay, the read delay and write delay of the DRAM are generally fixed values of about 30ns, while the read delay of the NVM such as PCM is about 100ns, and the write delay is about 500ns, which have a large difference.

In the prior art, in order to solve the timing sequence compatibility problem between the NVM and the DDR bus, the NVM is not directly connected to the DDR bus, but is connected to the DDR bus through the NVM controller, and temporarily stores data read from the NVM or data to be written into the NVM through a buffer space inside the NVM controller, and the structure of the NVM controller may be as shown in fig. 1.

As can be seen from fig. 1, data to be written into the NVM or data read from the NVM needs to be scheduled and buffered inside the NVM controller, which results in unfixed data reading and writing delay. Because the read-write delay is not fixed, the NVM controller and the memory controller need to exchange the information related to the NVM, so as to ensure the accuracy of the data transmission process of the NVM controller and the memory controller. For example, when the NVM controller sends read data to the memory controller, the memory controller needs to be informed of the correspondence between the read data and the read request sent by the memory controller; for another example, when the cache space inside the NVM is full, the NVM controller needs to notify the memory controller that the internal cache space is full, and the data cannot be written continuously.

Therefore, how to transmit additional data (such as NVM-related information) between the NVM controller and the memory controller is a problem to be solved.

Disclosure of Invention

The application provides a memory device, a memory controller, a data cache device and a computer system, which are used for solving the problem that extra data cannot be transmitted between an NVM controller and the memory controller.

In a first aspect, a memory device is provided, which includes: a non-volatile memory NVM; and the NVM controller is connected with the memory controller through a double-rate DDR bus, performs memory access operation on the NVM according to a command of the memory controller, and performs data transmission with the memory controller on part of DQS signal lines in the DDR bus.

With reference to the first aspect, in certain implementations of the first aspect, the DDR bus includes multiple data buses, each of which includes a DQ signal line, a first DQs signal line, and a second DQs signal line, the NVM controller performs data transmission with the memory controller on the DQ signal line and the second DQs signal line in a first data bus group according to a first DQs signal transmitted on the first DQs signal line in the first data bus group, and the first data bus group is any one of the multiple data bus groups.

With reference to the first aspect, in certain implementations of the first aspect, the performing, by the NVM controller, data transmission with the memory controller on the DQ signal lines and the second DQS signal lines in the first set of data buses according to a first DQS signal transmitted on a first DQS signal line in the first set of data buses includes: the NVM controller transmits target data with the memory controller on DQ signal lines in the first set of data buses according to the first DQS signal, wherein the target data comprises at least one of data to be written into the NVM and data read out from the NVM; and in the process of transmitting the target data by the DQ signal lines in the first group of data buses, the NVM controller transmits data with the memory controller on the second DQS signal lines in the first group of data buses according to the first DQS signal.

With reference to the first aspect, in certain implementations of the first aspect, the target data includes first target data read from the NVM, and the NVM controller performs data transmission with the memory controller on a second DQS signal line in the first set of data buses according to the first DQS signal, including: in the process of transmitting the first target data through the DQ signal lines in the first group of data buses, the NVM controller sends first data on second DQs signal lines in the first group of data buses according to the first DQs signal, where the first data includes at least one of an identifier of the first target data and a memory address of the first target data.

With reference to the first aspect, in certain implementations of the first aspect, the first data further includes at least one of the following information: an identification of data that has been written in the NVM; information indicating whether data was successfully written to the NVM; and information indicating a status of a data cache in the NVM controller.

With reference to the first aspect, in certain implementations of the first aspect, the target data includes second target data to be written into the NVM, and the NVM controller performs data transmission with the memory controller on a second DQS signal line in the first set of data buses according to the first DQS signal, including: during the transmission of the second target data on the DQ signal lines in the first set of data buses, the NVM controller receives second data on second DQs signal lines in the first set of data buses according to the first DQs signal, the second data including an identification of the second target data.

With reference to the first aspect, in certain implementations of the first aspect, the NVM includes at least one RANK.

Optionally, check information of the data, such as an Error Correction Code (ECC) of the data, may also be transmitted on the second DQS signal line of the first group of data buses.

In a second aspect, a memory controller is provided, the memory controller comprising: the scheduler is used for receiving the memory access request of the processor; and the memory bus interface is connected with a memory device through a double-rate DDR bus, and sends a command for accessing a nonvolatile memory NVM in the memory device to the memory device according to the memory access request, and performs data transmission with the memory device on part of DQS signal lines in the DDR bus.

With reference to the second aspect, in certain implementations of the second aspect, the DDR bus includes multiple data buses, each of the multiple data buses includes a DQ signal line, a first DQs signal line, and a second DQs signal line, the memory bus interface performs data transmission with the memory device on the DQ signal line and the second DQs signal line in the first data bus according to a first DQs signal transmitted on the first DQs signal line in the first data bus, and the first data bus is any one of the multiple data buses.

With reference to the second aspect, in some implementations of the second aspect, the data transmission between the memory bus interface and the memory device on the DQ signal lines and the second DQS signal lines in the first group of data buses according to the first DQS signal transmitted on the first DQS signal line in the first group of data buses includes: the memory bus interface transmits target data with the memory device on DQ signal lines in the first group of data buses according to the first DQS signal, wherein the target data comprises at least one of data to be written into the NVM and data read from the NVM; and in the process of transmitting the target data through the DQ signal lines in the first group of data buses, the memory bus interface performs data transmission with the memory device on the second DQS signal lines in the first group of data buses according to the first DQS signal.

With reference to the second aspect, in some implementations of the second aspect, the target data includes first target data read from the NVM, and the memory bus interface performs data transmission with the memory device on a second DQS signal line in the first set of data buses according to the first DQS signal, including: in the process of transmitting the first target data through the DQ signal lines in the first group of data buses, the memory bus interface receives first data on second DQs signal lines in the first group of data buses according to the first DQs signal, where the first data includes at least one of an identifier of the first target data and a memory address of the first target data.

With reference to the second aspect, in certain implementations of the second aspect, the first data further includes at least one of the following information: an identification of data that has been written in the NVM; information indicating whether data was successfully written to the NVM; and information indicating a status of a data cache in the NVM controller.

With reference to the second aspect, in some implementations of the second aspect, the target data includes second target data to be written into the NVM, and the memory bus interface performs data transmission with the memory device on a second DQS signal line in the first set of data buses according to the first DQS signal, including: and in the process of transmitting the second target data through the DQ signal lines in the first group of data buses, the memory bus interface sends second data on second DQS signal lines in the first group of data buses according to the first DQS signal, wherein the second data comprises the identifier of the second target data.

Optionally, in a process that the memory controller accesses the memory device, the memory bus interface may determine a type of the storage unit to be accessed, and select the functional interface corresponding to the DRAM to access the DRAM when it is determined that the storage unit to be accessed is the DRAM. And under the condition that the memory unit to be accessed is determined to be the NVM, selecting a functional interface corresponding to the NVM by the memory bus interface to access the NVM. Wherein the functional interface may be a logical interface. In practice, two functional interfaces may share the same set of physical interfaces.

With reference to the second aspect, in certain implementations of the second aspect, the NVM includes at least one RANK. In a third aspect, a data caching apparatus is provided, where the data caching apparatus is located between a memory controller and a memory device, and is connected to the memory controller and the memory device through a double data rate DDR bus, respectively, the memory device includes a non-volatile memory NVM, and the data caching apparatus includes: the memory bus interface receives data transmitted on part of DQS signal lines in the DDR bus in the process that the memory controller sends data to be written into the NVM to the memory device or receives data read from the NVM from the memory device; and the buffer is used for buffering the data received by the memory bus interface.

With reference to the third aspect, in some implementations of the third aspect, the DDR bus includes multiple data bus groups, each data bus group includes a DQ signal line, a first DQs signal line, and a second DQs signal line, the memory bus interface receives data transmitted on the DQ signal line and the second DQs signal line in a first data bus group according to a first DQs signal transmitted on the first DQs signal line in the first data bus group, and the first data bus group is any one of the multiple data bus groups.

In a fourth aspect, a computer system is provided, which includes the memory device according to the first aspect or any implementation manner of the first aspect, and the memory controller according to the second aspect or any implementation manner of the second aspect.

With reference to the fourth aspect, in some implementations of the fourth aspect, the computer system further includes a data caching apparatus as described in the third aspect or any one of the implementations of the third aspect.

In the prior art, the DQS signal on the DQS signal line is used for latching data on the DQ signal line, and the data are transmitted by using part of the DQS signal lines in the DDR bus, so that the problem that additional data cannot be transmitted between a memory controller and a memory device is solved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of the connection between a memory controller and an NVM-based memory device.

Fig. 2 is a schematic structural diagram of a memory device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a DDR bus shared by 4DRAM and 8 DRAM.

FIG. 4 is a timing diagram for reading and writing to a 4 DRAM.

FIG. 5 is a timing diagram for reading and writing to a × 8 DRAM.

FIG. 6 is a diagram of a DDR bus shared by a × 4DRAM and a × 8NVM according to an embodiment of the present invention.

FIG. 7 is a timing diagram for reading and writing of a 8NVM provided in accordance with one embodiment of the present invention.

FIG. 8 is a timing diagram for reading and writing of a 8NVM according to another embodiment of the present invention.

FIG. 9 is a schematic block diagram of a memory controller according to an embodiment of the invention.

Fig. 10 is a schematic configuration diagram of a data cache apparatus according to an embodiment of the present invention.

FIG. 11 is an architecture diagram of a memory including a DRAM and an NVM according to one embodiment of the present invention.

FIG. 12 is a diagram of a memory including a DRAM and an NVM according to another embodiment of the present invention.

FIG. 13 is a diagram of a memory including a DRAM and an NVM according to yet another embodiment of the present invention.

FIG. 14 is a schematic block diagram of a computer system of an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention.

The memory controller and the memory device are generally connected by a DDR bus, and for the sake of understanding, the DDR bus will be briefly described. The DDR bus includes an address bus (address bus), a Command bus (Command bus), and a data bus (data bus). The Data bus in the DDR bus includes Bi-directional Data Strobe (DQS) signal lines and DQ signal lines. In conventional DRAM-based memory devices, a memory controller and the memory device perform data transmission on a DQ signal line based on a DQS signal transmitted on a DQS signal line. Taking write data as an example, the memory controller sends a DQS signal and data to be written to the memory device through a DQS signal line and a DQ signal line, respectively, and the memory device latches (or samples) the data to be written transmitted on the DQ signal line based on the received DQS signal. Similarly, during data reading, the memory device sends the DQS signal and the read data to the memory controller through the DQS signal line and the DQ signal line, respectively, and the memory controller latches the read data transmitted on the DQ signal line based on the DQS signal. In summary, in the prior art, data (also referred to as a DQ signal) is transmitted on a DQ signal line, and a DQs signal transmitted on a DQs signal line is mainly used for realizing clock synchronization between a memory controller and a memory device, and the DQs signal is equivalent to a clock synchronization signal.

It should be noted that a DQS signal line refers to a line that can logically form a DQS signal, and in practice, a DQS signal may be transmitted through a physical DQS line. In this case, one DQS signal line corresponds to one physical DQS line. In another case, when the DQS signal is a differential signal, the DQS signal needs to be transmitted through two physical DQS lines. In this case, one DQS signal line corresponds to two physical DQS lines.

The memory device according to the embodiment of the present invention is described in detail below with reference to fig. 2. Fig. 2 is a diagram of a memory device according to an embodiment of the invention. The memory device 20 includes:

NVM 24, the NVM 24 can include at least one NVM chip, for example, the NVM 24 can be an NVM RANK, or the NVM 24 can be an NVM DIMM.

The NVM controller 22 is connected with the memory controller through the DDR bus, and the NVM controller 22 performs access operation on the NVM 24 according to the command of the memory controller and performs data transmission with the memory controller on part of DQS signal lines in the DDR bus.

It should be noted that the selection of the partial DQS signal lines for transmitting data may be varied, and will be described in detail with reference to specific embodiments.

First, DQS signal lines for transmitting data signals may be selected from a group of data buses of the DDR bus based on a grouping design of the existing DDR bus, and for understanding, the grouping design of the existing DDR bus is described first.

In practice, in order to enable DRAMs with different bit widths to operate on the same DDR bus, the DDR bus is generally designed in groups. Taking DDR buses compatible with x 4 DRAMs (i.e., 4 bits wide of DRAM chips) and x 8 DRAMs (i.e., 8 bits wide of DRAM chips) as an example, in the design of a standard Dual Inline Memory Module (DIMM), a set of DDR data buses usually includes 8 DQ signal lines and 2 DQs signal lines, and these signal lines are designed with equal length on a circuit board, so that the DDR bus can normally operate regardless of whether the DDR data bus is connected to the x 4 DRAMs or the x 8 DRAMs. The operation of the x 4DRAM and x 8DRAM compatible DDR bus is described in detail below in conjunction with fig. 3-5.

FIG. 3 is a schematic diagram of a DDR bus shared by 4DRAM and 8 DRAM. Fig. 3 shows a total of 2 DIMMs, where the DRAM chips inside DIMM 0 are x 4 DRAMs and the DRAM chips inside DIMM1 are x 8 DRAMs. Further, FIG. 3 shows a set of data buses in the DDR bus, which includes 8 DQ signal lines (DQ [ 0: 7] in FIG. 3) and 2 DQS signal lines (DQS [0] and DQS [1] in FIG. 3). It should be understood that fig. 3 shows only one set of data buses in the DDR bus for convenience of description, and in practice, the DDR bus may include multiple sets of data buses, for example, for a DIMM supporting Error Correction Code (ECC), the DDR data bus typically includes 72 DQ signal lines and 18 DQs signal lines, the data buses are divided into 9 sets of data buses, each set of data buses includes 8 DQ signal lines and 2 DQs signal lines; for DIMMs that do not support ECC, the DDR data bus typically includes 64 DQ signal lines and 16 DQs signal lines, which are divided into 8 groups of data buses, each group including 8 DQ signal lines and 2 DQs signal lines.

For DIMM 0, since the internal memory chip is a × 4DRAM, one DQS signal line needs to latch 4 DQ signal lines, therefore DQS [0] and DQS [1] are both used to transmit DQS signals, wherein DQS signal transmitted on DQS [0] is used to latch DQ [ 0: 3, the DQS signal transmitted on DQS [1] is used to latch DQ [ 4: 7], specific read and write timing for a 4DRAM see FIG. 4.

For DIMM1, since the internal memory chip is a × 8DRAM, 8 DQ signal lines need to be latched by one DQS signal line, so any one of DQS [0] and DQS [1] can complete DQ [ 0: 7] the other DQS signal line has no actual signal function. Specific read and write timing for a 8DRAM referring to fig. 5, fig. 5 differs from fig. 4 in that in fig. 5, DQS [0] completes the latching of all DQ lines in a set of DQS data buses, while DQS [1] is responsible for terminating with the TDQS pin of DIMM1 without passing the DQS signal.

As can be seen from FIG. 5, the result of the grouping scheme is that in some cases, some of the DQS signal lines in a group of data buses need not pass the DQS signal, but merely provide a termination function, such as DQS [1] in FIG. 5, which is connected to the TDQS pin of DIMM 1.

It should be noted that, the grouping design manner of the DDR data bus is described above only by taking the DDR bus shared by the × 4DRAM and the × 8DRAM as an example, the embodiments of the present invention are not limited thereto, and the grouping design manner of the DDR bus shared by other DRAMs with different bit widths is similar, and will not be described in detail here. In summary, when DRAMs with different bit widths share the DDR bus, each set of data bus in the DDR bus includes multiple DQS signal lines, and when a higher bit width DRAM of the DRAMs with different bit widths is connected to the DDR bus, a DQS signal line that does not transmit a DQS signal and only provides termination appears among the multiple DQS signal lines.

On the basis of the block design of the DDR bus, the DQS signal line for transmitting data can be selected as follows.

Optionally, as an embodiment, the DDR bus includes multiple data buses, each of which includes a DQ signal line, a first DQs signal line, and a second DQs signal line, and the NVM controller performs data transmission with the memory controller on the DQ signal line and the second DQs signal line in the first data bus according to the first DQs signal transmitted on the first DQs signal line in the first data bus, where the first data bus is any one of the multiple data buses. Further, in some embodiments, each of the plurality of sets of data buses may select the DQS signal lines for transmitting data in the same manner as the first set of data buses.

In the prior art, the DQS signal on the DQS signal line is used for latching the data on the DQ signal line, and the embodiment of the invention utilizes part of the DQS signal lines in the DDR bus to transmit data, thereby solving the problem that additional data cannot be transmitted between a memory controller and a memory device. For example, NVM-related information may be passed between the memory controller and the memory device to ensure the accuracy of information interaction between the NVM controller and the memory controller.

Further, the NVM controller transmits data on the DQ signal lines in the first set of data buses based on the first DQS signal. Assuming that the DDR bus is designed to be compatible with the DRAM with the first bit width and the DRAM with the second bit width, where the second bit width is greater than the first bit width, the embodiment of the present invention is equivalent to simulating the operation mode of the DRAM chip with the second bit width by using the NVM controller, and latching data transmitted on the DQ signal lines in the first group of data buses through one DQS signal line, so that a DQS signal line without transmitting a DQS signal may appear, and this type of DQS signal line may be selected to transmit additional data, thereby providing possibility for exchanging NVM-related information between the NVM controller and the memory controller.

Taking the first bit wide as 4 bits and the second bit wide as 8 bits as an example, the NVM can emulate a × 8DRAM (hereinafter, such NVM is referred to as × 8NVM) through the NVM controller, so that during data exchange between the NVM controller and the memory controller, one DQS signal line that does not need to transmit the DQS signal appears in each data bus in the DDR bus, fig. 6 is a schematic diagram of the × 4DRAM and the × 8NVM sharing the DDR bus, and this DQS signal line that does not need to transmit the DQS signal is DQS1 connected to the TDQS pin in fig. 6.

Assuming that the grouping of the DDR bus is designed to be compatible with the × 4DRAM and the × 8DRAM, in the case of supporting the ECC, the DDR data bus may include 72 DQ signal lines and 18 DQs signal lines, the data buses are divided into 9 groups, each group includes 8 DQ signal lines and 2 DQs signal lines, the first group data bus may be any one of the 9 groups, the first DQs signal line may be any one of the 2 DQs signal lines (the other is the second DQs signal line) in the first group data bus, the first DQs signal line transmits the first DQs signal, and the NVM controller may latch data transmitted on the other 8 DQ signal lines in the first group data bus according to the first DQs signal and latch data transmitted on the second DQs signal line. In other embodiments, where ECC is not supported, the DDR data bus may include 64 DQ signal lines and 16 DQs signal lines, the data buses are divided into 8 groups, each group includes 8 DQ signal lines and 2 DQs signal lines, the first group of data bus may be any one of the 8 groups, the first DQs signal line may be any one of the 2 DQs signal lines in the first group of data buses (another is the second data bus), the first DQs signal line transmits the first DQs signal, and the NVM controller may latch data transmitted on the other 8 DQ signal lines in the first group of data buses and latch data transmitted on the second DQs signal line according to the first DQs signal.

Optionally, as an embodiment, the NVM controller performing data transmission with the memory controller on a DQ signal line and a second DQS signal line in the first set of data buses according to the first DQS signal includes: the NVM controller transmits target data with a memory controller on DQ signal lines in a first group of data buses according to the first DQS signal, wherein the target data comprises at least one of data to be written into the NVM and data read out from the NVM; in the process of transmitting target data through DQ signal lines in the first group of data buses, the NVM controller performs data transmission with the memory controller on second DQS signal lines in the first group of data buses according to the first DQS signal.

In the prior art, the RANK in the memory shares the DDR bus, each RANK performs time division multiplexing on the DDR bus without mutual influence, and when one RANK transmits data, the data buses of other RANKs are in a termination state and do not transmit signals.

The embodiment of the invention utilizes the characteristic of time division multiplexing DDR data buses among RANKs to specify that the second DQS signal line in the first group of data buses transmits data in the process of transmitting target data by the DQ signal line of the first group of data buses. Based on the time division multiplexing characteristic of the DDR data bus, in the process that the DQ signal lines of the first group of data buses transmit target data, the second DQS signal lines are occupied by the NVM, and data transmission on the second DQS signal lines cannot affect data transmission of other memories or other RANKs.

In the following, detailed description will be given by taking a DDR bus capable of connecting a × 4DRAM and a × 8DRAM at the same time as an example, with reference to fig. 7. FIG. 7 shows the flow of the NVM controller emulating a 8DRAM for data read and write. Specifically, in a write scenario, the NVM controller writes data into the cache space of the NVM controller after receiving an Activate Command (ACT) and a write command (WR) with a write latency indicated by the tWL parameter. Before writing data, it is necessary to obtain the DQS signal from DQS [0] and start latching DQ [ 0: 7] and stops latching DQ [ 0: 7] data transmitted over; in a read scenario, after the memory controller sends an activate command and a read command, the data cannot be read according to the timing sequence of the DRAM due to the performance limitation of the NVM medium, after the NVM controller learns that there is data to be read from the NVM to the buffer space of the NVM controller, the NVM controller will notify the memory controller to read the data through some pins, then the memory controller will send a TB command to the NVM controller (the delay between the read command and the TB command is non-fixed delay, which is determined by the characteristics of the NVM medium itself), and after receiving the command, the NVM will put the data into DQ [ 0: 7] after the data is placed in DQ [ 0: before 7], the DQS signal needs to be sent to the memory controller through DQS [0], so that after the memory controller receives the DQS signal, it starts to latch DQ [ 0: 7] and stops latching DQ [ 0: 7] data transmitted over the network. As can be seen from FIG. 7, in latching DQ [0] based on DQS [0 ]: 7] during the process of transferring data on the data bus, the data is transferred on the DQS [1] at the same time, for example, transferring information related to NVM, because each group of data bus includes 8 DQ signal lines and 2 DQS signal lines, each time 64 bytes of data are transferred through the DQ signal lines, the DQS [1] can be used to transfer additional 9 bytes of data, which provides sufficient support for transferring information related to NVM.

It should be noted that, in the embodiment of the present invention, when data is transferred on the second DQS signal line of the first group of data buses, a data signal on the second DQS signal line of the first group of data buses may have the same phase as a DQS signal on the first DQS signal line of the first group of data buses, or may have the same phase as a signal on a DQ signal line of the first group of data buses. Using a × 8NVM as an example, fig. 7 is an example of a data signal on the second DQS signal line of the first set of data buses being in phase with a signal on the DQ signal line of each set of data buses; FIG. 8 is an example of a data signal on a second DQS signal line of the first set of data buses being in phase with a DQS signal on a first DQS signal line of the first set of data buses.

The embodiment of the present invention does not specifically limit the type of data transmitted on the second DQS signal line in the first group of data buses, and in practice, the type of data may be selected according to the type of target data transmitted on the DQ signal line in the first group of data buses, and the following detailed description is given with reference to specific embodiments.

Optionally, in some embodiments, the target data includes first target data read from the NVM, and the NVM controller performs data transmission with the memory controller on a second DQS signal line in the first set of data buses according to the first DQS signal, including: in the process of transmitting the first target data through the DQ signal lines in the first group of data buses, the NVM controller transmits first data on second DQS signal lines in the first group of data buses according to the first DQS signal, wherein the first data comprises at least one of an identifier of the first target data and a memory address of the first target data. The identifier of the first target data can be used for indicating the data corresponding to which read request the first target data is; further, the identification of the first target data may correspond to a read address of a read request of the first target data.

Further, the first data further comprises at least one of the following information: an identification of data written in the NVM; information indicating whether data was successfully written to NVM; and information indicating the status of the data cache in the NVM controller.

Optionally, in some embodiments, the target data includes second target data to be written into the NVM, and the NVM controller performs data transmission with the memory controller on a second DQS signal line in the first set of data buses according to the first DQS signal, including: during the transmission of second target data on the DQ signal lines in the first set of data buses, the NVM controller receives second data on second DQS signal lines in the first set of data buses according to the first DQS signal, the second data including an identification of the second target data. The identifier of the second target data can be used for indicating the data corresponding to which write request the second target data is; further, the identification of the second target data may correspond to a write address of a write request for the second target data.

Further, check information for the data, such as ECC, may also be communicated on the second DQS signal line of the first set of data buses.

In this application, the DQS signal line for transmitting data may be referred to as an NM Bus (i.e., NVM Message Bus), data on the NM Bus may be referred to as an NM packet, and for a write scenario, the NM packet may include an identification wid (writeid) of data to be written. For a Read scenario, an RID (Read ID, i.e. an identifier of the data to be Read) may be set for the data to be Read, and the RID of the Read data may be returned through the NM packet. Alternatively, the RID may not be set for the data to be read, and the address of the read data may be directly returned by the NM packet.

Further, if it is necessary to confirm whether data is written in the NVM (i.e., to make a write completion confirmation), the WID of the data already written in the NVM, and status information of whether the WID is valid, error, etc. may be carried in the NM packet.

Further, the NM packet may contain ECC bits for protecting the correctness of the transferred data in either a read or write scenario.

In DDR4, the DIMM with ECC function of DDR4 has pins connected to 18 DQS signal lines (each DQS signal line includes two differential signal lines), 9 DQS signal lines can be used as NM bus lines, and the correspondence relationship between them is shown in table one:

table one: corresponding relation between DQS signal line and NM bus

For write scenarios, NM [ 0: NVM related information may be carried in the manner shown in Table two.

Table two: NM packet definition for write scenarios

As shown in table two, a clock (clock) may include 2 beats (beat), each of which may transmit different information. For a write scenario, the NM bus may be used to transmit an identification (WID) of data to be written, and may also transmit an ECC field for checking NM packets (NM packets transmitted this time). RFU (reserved For Future use) in Table two is a reserved field.

For the read scenario, NM [ 0: NVM related information may be carried in the manner shown in Table three.

Table three: NM packet definition for read scenarios

In table three, RID is the identifier of the read data, and R-ADDR is the address of the read data, both of which may be transferred simultaneously or only one of them may be transferred. For example, when the memory controller reads data, if the RID of the data to be read is embedded in the read request (or the memory controller and the NVM controller indicate the RID of the data to be read by other means such as synchronous counting), after the NVM controller acquires the data from the NVM, the NM packet may carry the RID of the data, so that the memory controller knows which read request the data corresponds to based on the RID. For another example, when the memory controller reads data, if the NVM cannot obtain the RID corresponding to the read request, after the NVM controller obtains the data from the NVM, the NM packet may carry the memory address of the data, so that the memory controller can know which read request the data corresponds to based on the memory address. Furthermore, in some embodiments, the WID identification of the data written to NVM may be returned by the NM packet, which is equivalent to an acknowledgement of the data written to NVM, Valid in Table three may indicate whether the returned WID is a Valid WID, STAU may occupy 1 or more bits, indicate whether the data was successfully written to NVM, or indicate that an error occurred during the data write process. Further, in some embodiments, a WC/PWC (write credit/persistent write credit) field may be added in table 3 to indicate the remaining capacity (or free capacity) of the write cache space within the NVM controller, etc., based on which the memory controller may determine whether to write new data.

While the memory device according to the embodiment of the present invention is described in detail with reference to fig. 2 to 8, the memory controller according to the embodiment of the present invention is described in detail with reference to fig. 9, it should be understood that the signal processing manner between the memory controller and the memory device is similar, and for brevity, will not be described in detail here.

FIG. 9 is a schematic block diagram of a memory controller according to an embodiment of the invention. The memory controller 90 of fig. 9 includes:

a scheduler 92 for receiving the memory access request of the processor;

and the memory bus interface 94 is connected with the memory device through a double-rate DDR bus, and the memory bus interface 94 sends a command for accessing the nonvolatile memory NVM in the memory device to the memory device according to the memory access request, and performs data transmission with the memory device on a part of DQS signal lines in the DDR bus.

In the prior art, the DQS signal line is used for latching data on the DQ signal line, and the embodiment of the invention utilizes part of DQS signal lines in the DDR bus to transmit data, thereby solving the problem that additional data cannot be transmitted between a memory controller and a memory device. For example, NVM-related information may be passed between the memory controller and the memory device to ensure the accuracy of information interaction between the NVM controller and the memory controller.

Optionally, in some embodiments, the memory bus interface 94 may determine the type of the memory unit to be accessed, where in a case that the memory unit is a DRAM, the memory bus interface 94 selects a functional interface corresponding to the DRAM to access the DRAM, and in a case that the memory unit is an NVM, the memory bus interface 94 selects a functional interface corresponding to the NVM to access the NVM. The storage unit may be RANK, for example.

The Memory bus interface 94 may determine the type of Memory cell to be accessed in a variety of ways, for example, in the DIMM standard, the DIMM has a Serial Presence check electrically Erasable Programmable Read Only Memory (SPD EEPROM), the EEPROM can be accessed through a Serial interface other than the DDR address/data/command bus, the EEPROM can store the type information of the Memory cell (for example, the type information of RANK), and the Memory bus interface 94 can know the type of the Memory cell by accessing the EEPROM.

The memory bus interface 94 may include two functional interfaces: FUNC1 and FUNC 2. It should be understood that the functional interfaces may be logical interfaces, and in practice, two functional interfaces may share the same set of physical interfaces, taking a × 8DRAM as an example, and two functional interfaces may share 8 DQ signal lines and 2 DQs signal lines. The FUNC1 may support the data transmission mode of DRAM, for example, for x 4DRAM, each group of data bus includes 2 DQS signal lines, the DQS signal transmitted on 1 DQS signal line latches the data transmitted on 4 DQ lines; for x 8DRAM, each set of data bus lines includes 2 DQS signal lines, wherein a DQS signal transmitted on 1 DQS signal line can latch data transmitted on 8 DQ signal lines, and the other 1 DQS signal line does not carry signals and provides only termination functions. FUCN2 may be a functional interface that supports data transfer on DQS signal lines, where for x 8NVM, each packet includes 2 DQS signal lines, where a DQS signal transmitted on 1 DQS signal line latches data transmitted on 8 DQ signal lines, and the other 1 DQS signal line is also used to transfer data, e.g., to transfer NVM-related information.

Optionally, in some embodiments, the DDR bus includes multiple data buses, each of which includes a DQ signal line, a first DQs signal line, and a second DQs signal line, and the memory bus interface 94 performs data transmission with the memory device on the DQ signal lines and the second DQs signal lines in the first data bus according to a first DQs signal transmitted on the first DQs signal line in the first data bus.

Optionally, in some embodiments, the data transmission between the memory bus interface 94 and the memory device through the DQ signal lines and the second DQS signal lines in the first group of data buses according to the first DQS signal includes: the memory bus interface 94 transmits target data with the memory device on DQ signal lines in the first set of data buses according to the first DQS signal, where the target data includes at least one of data to be written into the NVM and data read from the NVM; during the transmission of the target data on the DQ signal lines of the first set of data buses, the memory bus interface 94 performs data transmission with the memory device on the second DQs signal line of the first set of data buses according to the first DQs signal.

Optionally, in some embodiments, the target data includes first target data read from the NVM, and the memory bus interface 94 performs data transmission with the memory device on a second DQS signal line in the first set of data buses according to the first DQS signal, including: during the transmission of the first target data on the DQ signal lines of the first set of data buses, the memory bus interface 94 receives first data on a second DQs signal line of the first set of data buses according to the first DQs signal, where the first data includes at least one of an identification of the first target data and a memory address of the first target data.

Optionally, in some embodiments, the first data further comprises at least one of the following information: an identification of data that has been written in the NVM; information indicating whether data was successfully written to the NVM; and information indicating a status of a data cache in the NVM controller.

Optionally, in some embodiments, the target data includes second target data to be written into the NVM, and the memory bus interface 94 performs data transmission with the memory device on a second DQS signal line in the first set of data buses according to the first DQS signal, including: in the process of transmitting the second target data through the DQ signal lines in the first group of data buses, the memory bus interface 94 sends second data on the second DQs signal lines in the first group of data buses according to the first DQs signal, where the second data includes an identifier of the second target data.

Optionally, in some embodiments, the NVM includes at least one RANK.

The memory device and the memory controller according to the embodiments of the present invention are described in detail with reference to fig. 2 to 9, and the data caching device according to the embodiments of the present invention is described in detail with reference to fig. 10, where the data caching device is located between the memory controller and the memory device, and during a data transmission process between the memory controller and the memory device, the data caching device may cache data exchanged between the memory controller and the memory device, perform certain signal processing (for example, amplifying a signal), and then continue to send the signal to an opposite end, so that accuracy of signal transmission may be improved. Therefore, if a data caching device of this type is provided between the memory device and the memory controller, the data caching device also needs to use similar signal processing methods as those of the memory controller and the memory device to support the data transmission on the DQS signal line, and the specific signal processing method can be referred to above and will not be described in detail here.

Fig. 10 is a schematic configuration diagram of a data cache apparatus according to an embodiment of the present invention. The data cache apparatus 100 of fig. 10 is located between a memory controller and a memory device, and is connected to the memory controller and the memory device through a DDR bus, respectively, the memory device includes an NVM,

the data caching apparatus 100 includes:

the memory bus interface 102 is configured to receive data transmitted on a part of DQS signal lines in the DDR bus in a process that the memory controller sends data to be written into the NVM or receives data read from the NVM from the memory device;

the buffer 104 is configured to buffer data received by the memory bus interface 102.

Optionally, as an embodiment, the DDR bus includes multiple data buses, where each data bus includes a DQ signal line, a first DQs signal line, and a second DQs signal line, the memory bus interface 102 receives data transmitted on the DQ signal line and the second DQs signal line in each data bus according to a first DQs signal transmitted on the first DQs signal line in the first data bus, and the first data bus is any one of the multiple data buses.

Some memories include both NVM and DRAM, and the NVM and DRAM may be organized in various manners, and the specific implementation manner of the data caching device (hereinafter referred to as db (data buffer)) may also be different for different types of organizations, which is described in detail below with reference to fig. 11 to 13.

Fig. 11 shows an organization of the NVM controller in the memory and the DRAM and NVM, in fig. 11, the data lines of the NVM controller 110 are connected to the memory controller 113 through the DB111 and the memory slot 112 (in fig. 11, the DDR4 slot is taken as an example). NVM controller 110 is coupled to NVM 114 and DRAM115, DRAM115 is located behind NVM 114, and the data bus of DRAM115 is coupled to NVM controller 110. In this arrangement, since the DB111 needs to buffer the data exchanged between the memory controller 113 and the memory device and needs to latch the data exchanged between the two, the DB111 also needs to support the data transmission of the DQS signal line, and the DB111 signal processing method can refer to fig. 7 or fig. 8.

Fig. 12 shows another organization of the NVM controller and DRAM and NVM, wherein the data buses of DRAM 125 and NVM controller 120 are respectively connected to DB 121, DB 121 is further connected to memory controller 123 through memory slot 122 (for example, DDR4 slot in fig. 12), and NVM 124 is located behind NVM controller 120. With this organization, the function of DB 121 needs to support both the normal data transfer of DRAM 125 and the data transfer of DQS signal lines.

Fig. 13 shows an example of the internal structure of the DB in the organization form shown in fig. 12, and as can be seen from fig. 13, the DB 121 internally includes two functional interfaces: FUNC1 and FUNC 2. It should be understood that the functional interfaces may be logical interfaces, and in practice, two functional interfaces may share the same set of physical interfaces, taking a × 8DRAM as an example, and two functional interfaces may share 8 DQ signal lines and 2 DQs signal lines. The FUNC1 may support the data transmission mode of DRAM, for example, for x 4DRAM, each group of data bus includes 2 DQS signal lines, the DQS signal transmitted on 1 DQS signal line latches the data transmitted on 4 DQ lines; for x 8DRAM, each set of data bus lines includes 2 DQS signal lines, wherein a DQS signal transmitted on 1 DQS signal line can latch data transmitted on 8 DQ signal lines, and the other 1 DQS signal line does not carry signals and provides only termination functions. FUCN2 may be a functional interface that supports data transfer on DQS signal lines, where for x 8NVM, each packet includes 2 DQS signal lines, where a DQS signal transmitted on 1 DQS signal line latches data transmitted on 8 DQ signal lines, and the other 1 DQS signal line is also used to transfer data, e.g., to transfer NVM-related information. In addition, the DB 121 further includes a control interface, and the DB 121 can be switched between the FUNC1 and the FUNC2 by a control command input through the control interface.

FIG. 14 is a schematic block diagram of a computer system of an embodiment of the present invention. The computer system 140 of FIG. 14 includes the memory device 20 described in FIG. 1, and the memory controller 90 described in FIG. 9.

Optionally, in some embodiments, the computer system 140 may further include the data caching apparatus 100 described in fig. 10.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims

1. A memory device, the memory device comprising:

a non-volatile memory NVM;

and the NVM controller is connected with the memory controller through a double-rate DDR bus, performs memory access operation on the NVM according to a command of the memory controller, and performs data transmission with the memory controller on part of DQS signal lines in the DDR bus.

2. The memory device of claim 1, wherein the DDR bus comprises a plurality of sets of data buses, each set of data buses including a DQ signal line, a first DQs signal line, and a second DQs signal line, the NVM controller to perform data transfers with the memory controller on the DQ signal lines and the second DQs signal lines of a first set of data buses according to a first DQs signal transferred on the first DQs signal line of the first set of data buses, the first set of data buses being any one of the plurality of sets of data buses.

3. The memory device of claim 2, wherein the NVM controller is to perform data transfers with the memory controller on the DQ signal lines and the second DQS signal lines in the first set of data buses based on a first DQS signal transferred on a first DQS signal line in the first set of data buses, comprising:

the NVM controller transmits target data with the memory controller on DQ signal lines in the first set of data buses according to the first DQS signal, wherein the target data comprises at least one of data to be written into the NVM and data read out from the NVM;

and in the process of transmitting the target data by the DQ signal lines in the first group of data buses, the NVM controller transmits data with the memory controller on the second DQS signal lines in the first group of data buses according to the first DQS signal.

4. The memory device of claim 3, wherein the target data comprises first target data read from the NVM,

the NVM controller performing data transmission with the memory controller on a second DQS signal line in the first set of data buses according to the first DQS signal, comprising:

in the process of transmitting the first target data through the DQ signal lines in the first group of data buses, the NVM controller sends first data on second DQs signal lines in the first group of data buses according to the first DQs signal, where the first data includes at least one of an identifier of the first target data and a memory address of the first target data.

5. The memory device of claim 4, wherein the first data further comprises at least one of:

an identification of data that has been written in the NVM;

information indicating whether data was successfully written to the NVM; and

information indicating a status of a data cache in the NVM controller.

6. The memory device of any one of claims 3-5, wherein the target data comprises second target data to be written to the NVM,

during the transmission of the second target data on the DQ signal lines in the first set of data buses, the NVM controller receives second data on second DQs signal lines in the first set of data buses according to the first DQs signal, the second data including an identification of the second target data.

7. The memory device of any one of claims 1-5, wherein the NVM comprises at least one RANK.

8. A memory controller, the memory controller comprising:

the scheduler is used for receiving the memory access request of the processor;

and the memory bus interface is connected with a memory device through a double-rate DDR bus, and sends a command for accessing a nonvolatile memory NVM in the memory device to the memory device according to the memory access request, and performs data transmission with the memory device on part of DQS signal lines in the DDR bus.

9. The memory controller of claim 8, wherein the DDR bus comprises a plurality of data buses, wherein each data bus comprises a DQ signal line, a first DQs signal line, and a second DQs signal line, wherein the memory bus interface is to perform data transfers with the memory device on the DQ signal lines and the second DQs signal lines of a first data bus group according to a first DQs signal transmitted on the first DQs signal line of the first data bus group, wherein the first data bus group is any one of the plurality of data bus groups.

10. The memory controller of claim 9, wherein the memory bus interface performs data transfers with the memory device on the DQ signal lines and the second DQS signal lines of the first set of data buses based on the first DQS signal transferred on the first DQS signal line of the first set of data buses, comprising:

the memory bus interface transmits target data with the memory device on DQ signal lines in the first group of data buses according to the first DQS signal, wherein the target data comprises at least one of data to be written into the NVM and data read from the NVM;

and in the process of transmitting the target data through the DQ signal lines in the first group of data buses, the memory bus interface performs data transmission with the memory device on the second DQS signal lines in the first group of data buses according to the first DQS signal.

11. The memory controller of claim 10, in which the target data comprises first target data read from the NVM,

the memory bus interface performs data transmission with the memory device on a second DQS signal line in the first group of data buses according to the first DQS signal, including:

in the process of transmitting the first target data through the DQ signal lines in the first group of data buses, the memory bus interface receives first data on second DQs signal lines in the first group of data buses according to the first DQs signal, where the first data includes at least one of an identifier of the first target data and a memory address of the first target data.

12. The memory controller of claim 11, wherein the first data further comprises at least one of:

an identification of data that has been written in the NVM;

information indicating whether data was successfully written to the NVM; and

information indicating a status of a data cache in the NVM controller.

13. The memory controller of any one of claims 10-12, wherein the target data includes second target data to be written to the NVM,

and in the process of transmitting the second target data through the DQ signal lines in the first group of data buses, the memory bus interface sends second data on second DQS signal lines in the first group of data buses according to the first DQS signal, wherein the second data comprises the identifier of the second target data.

14. The memory controller of any one of claims 8-12, wherein the NVM includes at least one RANK.

15. A data cache device, wherein the data cache device is located between a memory controller and a memory device and is connected with the memory controller and the memory device respectively through a double data rate DDR bus, the memory device comprises a non-volatile memory (NVM),

the data caching device comprises:

the memory bus interface receives data transmitted on part of DQS signal lines in the DDR bus in the process that the memory controller sends data to be written into the NVM to the memory device or receives data read from the NVM from the memory device;

and the buffer is used for buffering the data received by the memory bus interface.

16. The data cache apparatus of claim 15, wherein the DDR bus comprises a plurality of sets of data buses, wherein each set of data buses comprises a DQ signal line, a first DQs signal line, and a second DQs signal line, wherein the memory bus interface receives data transmitted on the DQ signal line and the second DQs signal line in a first set of data buses based on the first DQs signal transmitted on the first DQs signal line in the first set of data buses, and wherein the first set of data buses is any one of the plurality of sets of data buses.

17. A computer system comprising a memory device as claimed in any one of claims 1 to 7 and a memory controller as claimed in any one of claims 8 to 14.

18. A computer system according to claim 17, wherein the computer system further comprises a data caching device according to claim 15 or 16.