CN108123716B

CN108123716B - Crystal frequency calibration system

Info

Publication number: CN108123716B
Application number: CN201711361273.9A
Authority: CN
Inventors: 陆舟; 于华章
Original assignee: Feitian Technologies Co Ltd
Current assignee: Feitian Technologies Co Ltd
Priority date: 2017-12-18
Filing date: 2017-12-18
Publication date: 2021-04-27
Anticipated expiration: 2037-12-18
Also published as: CN108123716A

Abstract

The invention provides a calibration system for crystal frequency, and belongs to the technical field of electronics. The calibration system of the crystal frequency provided by the invention comprises at least one calibration device and at least one writing device; the calibration device comprises a first induction circuit, an amplification filter circuit and a calibration main control circuit. According to the calibration system provided by the invention, the crystal signal is acquired through the first induction circuit, an acquisition probe is not needed, and an acquisition probe point is not needed to be arranged on the PCB, so that the space of the PCB is effectively saved and additional equipment is reduced.

Description

Crystal frequency calibration system

Technical Field

The invention relates to the technical field of electronics, in particular to a crystal frequency calibration system.

Background

Most electronic products have crystals, the frequency of the crystals in the electronic products often deviates from the standard crystal frequency of the electronic products (for example, the standard crystal frequency is 32768Hz in the case of a time-type dynamic token), and in the prior art, errors in the operation of the electronic products are often caused due to the deviation of the crystal frequency, and even the electronic products cannot operate or are scrapped. For example, the time-based dynamic token requires that the time drift does not exceed the preset time each year, and the dynamic password generated by the dynamic token cannot be verified in the background when the time drift exceeds the preset time, i.e. the dynamic token cannot continue to work normally. Therefore, the crystal frequency of the electronic product needs to be measured and calibrated in the process of manufacturing the electronic product.

In the prior art, a calibration method of a crystal frequency involves acquiring a crystal frequency of a product to be tested (i.e., an electronic product) and writing a frequency compensation value, at least two probe points (including an acquisition probe point for acquiring the crystal frequency of the product to be tested and a write probe point for writing the frequency compensation value) need to be arranged on a PCB of the product to be tested in a semi-finished product stage (i.e., before a package of the product to be tested) and at least two probes (an acquisition probe for acquiring the crystal frequency and a write probe for writing the frequency compensation value) need to be connected with a calibration host. The calibration method in the prior art is as follows: the acquisition probe is manually contacted with the acquisition probe on the PCB of the product to be detected to acquire the crystal frequency of the product to be detected, the calibration host calculates the acquired crystal frequency and the standard crystal frequency to obtain a frequency compensation value, then the write-in probe is in alignment contact with the write-in probe on the PCB, and the calculated frequency compensation value is written into a main control chip of the product to be detected through the write-in probe and the write-in probe on the PCB. The calibration method of the crystal frequency in the prior art can only carry out acquisition and writing of frequency compensation values on the crystal frequency of a single product to be tested.

The prior art crystal frequency calibration method has the following defects: a detection point needs to be arranged on a PCB of a product to be detected, so that the limited space of the PCB is wasted; only the crystal of a single tested product can be calibrated during calibration, so that the calibration efficiency is low; since the probes are required to make contact with the probes on the PCB board, calibration of the crystal frequency must be performed before the package is packaged (i.e., semi-finished); when the measured product in the finished product stage needs to recalibrate the crystal frequency, the shell needs to be removed to calibrate the crystal frequency, the measured product needs to be reinstalled after calibration is completed, the rejection rate of the reinstalled measured product is correspondingly improved, and the operation of removing and reinstalling the shell is time-consuming and labor-consuming; the data communication between the calibration host and the tested product needs to be provided with a probe and a connection line between the probe and the calibration host, and additional equipment is added; the calibration process needs manual operation to align and contact the acquisition probe and the acquisition probe point, and align and contact the write-in probe and the write-in probe point, so that two times of alignment operation are performed, once the alignment is not accurate, the write-in failure is caused, the operation needs to be performed again, and the calibration efficiency is low.

Disclosure of Invention

The present invention provides a calibration system for crystal frequency to solve the above technical problems in the prior art.

The invention provides a calibration system for crystal frequency, which comprises at least one calibration device and at least one writing device; the calibration device comprises a first induction circuit, an amplification filter circuit and a calibration main control circuit;

the first induction circuit is connected with the amplifying and filtering circuit and used for acquiring a crystal signal of a detected product and sending the crystal signal to the amplifying and filtering circuit;

the amplification filtering circuit is connected with the first induction circuit and the calibration main control circuit, and is used for receiving the crystal signal from the first induction circuit, amplifying and filtering the crystal signal to obtain an amplification filtering signal, and sending the amplification filtering signal to the calibration main control circuit;

the calibration main control circuit is connected with the amplification filtering circuit, the writing device and the satellite signal receiver and is used for receiving the amplification filtering signal from the amplification filtering circuit and obtaining a first count value of a system clock according to the amplification filtering signal and a preset value; the second counting value is used for receiving a standard second signal from the satellite signal receiver and obtaining a second counting value of a system clock according to the standard second signal; the frequency compensation device is used for obtaining a frequency compensation value according to a first counting value of the system clock and a second counting value of the system clock and sending the frequency compensation value to the writing device;

the writing device is connected with the calibration main control circuit and used for receiving the frequency compensation value from the calibration main control circuit and writing the frequency compensation value into the tested product.

Compared with the prior art, the invention has the beneficial effects that: according to the calibration system provided by the invention, the crystal signal is acquired through the first induction circuit, an acquisition probe is not needed, and an acquisition probe point is not needed to be arranged on the PCB, so that the space of the PCB is effectively saved and additional equipment is reduced.

Drawings

Fig. 1 is a block diagram showing the module components of a crystal frequency calibration system according to embodiment 1 of the present invention;

FIG. 2 is a block diagram of the modules of a system for calibrating crystal frequency according to embodiment 1 of the present invention;

FIG. 3 is a block diagram of the modules of a system for calibrating crystal frequency according to embodiment 1 of the present invention;

FIG. 4 is a block diagram of the modules of a system for calibrating crystal frequency according to embodiment 1 of the present invention;

FIG. 5 is a block diagram of the modules of a system for calibrating crystal frequency according to embodiment 1 of the present invention;

fig. 6 is a schematic circuit diagram of a preamplifier circuit and a first sensing circuit according to embodiment 1 of the present invention;

fig. 7 is a schematic circuit diagram of a first amplification filter circuit according to embodiment 1 of the present invention;

fig. 8 is a schematic circuit diagram of a second amplification filter circuit according to embodiment 1 of the present invention;

fig. 9 is a schematic circuit diagram of a third amplification filter circuit according to embodiment 1 of the present invention;

fig. 10 is a schematic circuit diagram of a shaping circuit according to embodiment 1 of the present invention;

fig. 11 is a schematic circuit diagram of a calibration master circuit according to embodiment 1 of the present invention;

fig. 12 is a schematic circuit diagram of a second sensing circuit according to embodiment 2 of the present invention;

FIG. 13 is a block diagram of the modules of a system for calibrating crystal frequency according to embodiment 1 of the present invention;

fig. 14 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 1 of the present invention;

FIG. 15 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 2 of the present invention;

fig. 16 is a schematic circuit diagram of a first notification circuit according to embodiment 2 of the present invention;

fig. 17 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 2 of the present invention;

fig. 18 is a schematic circuit diagram of a write master circuit according to embodiment 2 of the present invention;

FIG. 19 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 2 of the present invention;

FIG. 20 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 2 of the present invention;

fig. 21 is a schematic circuit diagram of a receiving circuit according to embodiment 2 of the present invention;

fig. 22 is a schematic circuit diagram of a second notification circuit according to embodiment 2 of the present invention;

FIG. 23 is a block diagram of the modules of a system for calibrating crystal frequency according to embodiment 2 of the present invention;

FIG. 24 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 4 of the present invention;

fig. 25 is a schematic circuit diagram of a first master control device according to embodiment 4 of the present invention;

fig. 26 is a schematic circuit diagram of a first shunting device in embodiment 4 of the present invention;

fig. 27 is a schematic circuit diagram of a second master control device according to embodiment 4 of the present invention;

fig. 28 is a schematic circuit diagram of a second shunting device in embodiment 4 of the present invention;

FIG. 29 is a block diagram showing the module components of a system for calibrating crystal frequency according to embodiment 4 of the present invention;

FIG. 30 is a flowchart illustrating a method for calibrating a crystal frequency according to embodiment 5 of the present invention;

FIG. 31 is a flowchart illustrating a method for calibrating a crystal frequency according to embodiment 6 of the present invention;

FIG. 32 is a flowchart illustrating a method for calibrating a crystal frequency according to embodiment 7 of the present invention;

fig. 33 is a flowchart illustrating a calibration method of crystal frequency according to embodiment 8 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

The present embodiment provides a calibration system for crystal frequency, as shown in fig. 1, including a calibration apparatus 1 and a writing apparatus 2; the calibration device 1 comprises a first induction circuit 11, an amplification filter circuit 10 and a calibration main control circuit 17;

the first induction circuit 11 is connected with the amplifying and filtering circuit 10 and used for acquiring a crystal signal of a detected product and sending the crystal signal to the amplifying and filtering circuit 10;

specifically, the first sensing circuit 11 is specifically configured to collect a crystal signal of the product to be tested through electromagnetic induction or mechanical induction, and send the crystal signal to the amplifying and filtering circuit 10.

In this embodiment, the first sensing circuit 11 may be specifically an antenna circuit including a magnetic sensor probe; or, in particular, an antenna circuit including a piezoelectric sensor probe.

For example, the first sensing circuit collects the crystal signal of the product to be tested through its own magnetic sensor probe (i.e. electromagnetic sensing), or collects the crystal signal of the product to be tested through its own piezoelectric sensor probe (i.e. mechanical sensing), and sends the crystal signal to the amplifying and filtering circuit 10.

The amplifying and filtering circuit 10 is connected with the first sensing circuit 11 and the calibration main control circuit 17, and is configured to receive the crystal signal from the first sensing circuit 11, amplify and filter the crystal signal to obtain an amplified and filtered signal, and send the amplified and filtered signal to the calibration main control circuit 17;

the calibration main control circuit 17 is connected with the amplification filter circuit 10, the writing device 2 and the satellite signal receiver, and is used for receiving the amplification filter signal from the amplification filter circuit 10 and obtaining a first count value of the system clock according to the amplification filter signal and a preset value; the second counting value is used for receiving the standard second signal from the satellite signal receiver and obtaining a second counting value of the system clock according to the standard second signal; the frequency compensation device is used for obtaining a frequency compensation value according to a first counting value of the system clock and a second counting value of the system clock, and sending the frequency compensation value to the writing device 2;

specifically, the specific working method of the calibration main control circuit 17 obtaining the first count value of the system clock according to the amplified filtering signal and the preset value is as follows: measuring a count value of a system clock when a signal of a preset value period is obtained from the amplified filtering signal, and taking the count value of the system clock as a first count value of the system clock;

in this embodiment, the preset value is specifically a value of a standard crystal frequency of the product to be measured.

For example, taking a time-type dynamic token as an example, if the standard crystal frequency is 32768Hz, the preset value is 32768 Hz; the calibration main control circuit measures a count value C4 of a system clock when acquiring signals of 32768 cycles from the amplified and filtered signals, and takes the count value C4 of the system clock as a first count value C1 of the system clock;

or, the specific working method of the calibration main control circuit 17 obtaining the first count value of the system clock according to the amplified filtering signal and the preset value is as follows: and measuring a count value of the system clock when the signals with the preset times and a plurality of periods of the preset value are obtained from the amplified and filtered signals, and dividing the count value of the system clock by the preset times to obtain a first count value of the system clock. For example, the preset multiple is 0.5 times, or any of 2 times to 10 times.

For example, taking a time-type dynamic token as an example, if the standard crystal frequency is 32768Hz, the preset value is 32768 Hz; the calibration master circuit measures the count value C3 of the system clock when a signal of 98304(3 times of 32768) cycles is acquired from the amplified and filtered signal, and divides the count value C3 of the system clock by 3 to obtain a first count value C1 of the system clock.

Specifically, the specific working method of the calibration main control circuit 17 obtaining the second count value of the system clock according to the standard second signal is as follows: measuring the count value of the system clock in a standard second signal, and taking the count value of the system clock as a second count value of the system clock;

for example, the calibration master circuit starts counting the system clock when receiving the first rising edge of the standard second signal, stops counting the system clock when receiving the second falling edge of the standard second signal, obtains a count value C5 of the system clock, and takes the count value C5 of the system clock as the second count value C2 of the system clock.

Or, the specific working method of the calibration main control circuit 17 obtaining the second count value of the system clock according to the standard second signal is as follows: and measuring the count value of the system clock in the preset number of standard second signals, and dividing the count value of the system clock by the preset number to obtain a second count value of the system clock.

For example, the preset number is 3, the calibration master circuit starts counting the system clock when receiving the first rising edge of the standard second signal, stops counting the system clock when receiving the fourth rising edge of the standard second signal, obtains a count value C6 of the system clock, and divides the count value C6 of the system clock by 3 to obtain a second count value C2 of the system clock.

Specifically, the specific working method of the calibration main control circuit 17 obtaining the frequency compensation value according to the first count value of the system clock and the second count value of the system clock is as follows: and subtracting the first count value of the system clock from the second count value of the system clock to obtain a system clock count difference value, dividing the system clock count difference value by the first count value of the system clock to obtain a quotient value, and multiplying the quotient value by a preset value to obtain a frequency compensation value.

For example, in the case of a time-based dynamic token, the preset value is 10⁶The calibration master circuit subtracts the second count value C2 of the system clock from the first count value C1 of the system clock to obtain a system clock count difference value C2-C1, and divides the system clock count difference value C2-C1 by the first count value C1 of the system clock to obtain a quotient value

Will quotient value

Multiplied by a predetermined value 10⁶Obtaining a frequency compensation value

And the writing device 2 is connected with the calibration main control circuit 17 and is used for receiving the frequency compensation value from the calibration main control circuit 17 and writing the frequency compensation value into a tested product.

Specifically, the writing device 2 is specifically configured to receive the frequency compensation value from the calibration main control circuit 17, and write the frequency compensation value into the product to be tested in any one of an electromagnetic induction manner and a light induction manner.

Further specifically, the writing means 2 comprises a second sensing circuit; and the second sensing circuit is connected with the calibration main control circuit 17 and used for receiving the frequency compensation value from the calibration main control circuit 17 and writing the frequency compensation value into a tested product. For example, the second sensing circuit may be a light sensing circuit, and the frequency compensation value is written into the tested product in a light sensing manner; or the second induction circuit can be an electromagnetic induction circuit, and the frequency compensation value is written into the tested product in an electromagnetic induction mode.

In this embodiment, when the writing device 2 writes the frequency compensation value into the tested product in a contact manner, the writing device may be a writing probe connected to the calibration main control circuit 17, and the writing probe writes the frequency compensation value into the tested product through a writing probe point on the PCB of the tested product.

Optionally, as shown in fig. 2, the amplification filter circuit 10 specifically includes a pre-amplification circuit 12 and a first amplification filter circuit 13;

the pre-amplification circuit 12 is connected with the first induction circuit 11 and the first amplification filter circuit 13, and is used for receiving the crystal signal from the first induction circuit 11, pre-amplifying the crystal signal to obtain a pre-amplification signal, and sending the pre-amplification signal to the first amplification filter circuit 13;

the first amplification filter circuit 13 is connected with the pre-amplification circuit 12 and the calibration main control circuit 17, and is configured to receive the pre-amplification signal from the pre-amplification circuit 12, amplify and filter the pre-amplification signal to obtain an amplified filter signal, and send the amplified filter signal to the calibration main control circuit 17;

the calibration master circuit 17 is specifically connected to the first amplification filter circuit 13.

Alternatively, as shown in fig. 3, the amplifying and filtering circuit 10 specifically includes a pre-amplifying circuit 12, a first amplifying and filtering circuit 13, and a second amplifying and filtering circuit 14;

the first amplifying and filtering circuit 13 is connected with the pre-amplifying circuit 12 and the second filtering and amplifying circuit 14, and is configured to receive the pre-amplified signal from the pre-amplifying circuit 12, amplify and filter the pre-amplified signal to obtain a first amplified and filtered signal, and send the first amplified and filtered signal to the second amplifying and filtering circuit 14;

the second amplification filter circuit 14 is connected with the first amplification filter circuit 13 and the calibration main control circuit 17, and is configured to receive the first amplification filter signal from the first amplification filter circuit 13, amplify and filter the first amplification filter signal to obtain an amplification filter signal, and send the amplification filter signal to the calibration main control circuit 17;

the calibration master circuit 17 is specifically connected to the second amplification and filtering circuit 14.

Alternatively, as shown in fig. 4, the amplifying and filtering circuit 10 specifically includes a pre-amplifying circuit 12, a first amplifying and filtering circuit 13, a second amplifying and filtering circuit 14, and a third amplifying and filtering circuit 15;

the first amplifying and filtering circuit 13 is connected to the pre-amplifying circuit 12 and the second amplifying and filtering circuit 14, and is configured to receive the pre-amplified signal from the pre-amplifying circuit 12, amplify and filter the pre-amplified signal to obtain a first amplified and filtered signal, and send the first amplified and filtered signal to the second amplifying and filtering circuit 14;

the second amplifying and filtering circuit 14 is connected to the first amplifying and filtering circuit 13 and the third amplifying and filtering circuit 15, and is configured to receive the first amplifying and filtering signal from the first amplifying and filtering circuit 13, amplify and filter the first amplifying and filtering signal to obtain a second amplifying and filtering signal, and send the second amplifying and filtering signal to the third amplifying and filtering circuit 15;

the third amplification and filtering circuit 15 is connected to the second amplification and filtering circuit 14 and the calibration main control circuit 17, and is configured to receive the second amplification and filtering signal from the second amplification and filtering circuit 14, amplify and filter the second amplification and filtering signal to obtain an amplification and filtering signal, and send the amplification and filtering signal to the calibration main control circuit 17;

the calibration master circuit 17 is specifically connected to the third amplification and filtering circuit 15.

Optionally, the calibration device 1 further includes a shaping circuit;

the amplifying and filtering circuit 10 is specifically connected with the calibration main control circuit 17 through a shaping circuit;

and the shaping circuit is connected with the amplification filter circuit 10 and the calibration main control circuit 17 and is used for receiving the amplification filter signals from the amplification filter circuit 10, shaping the amplification filter signals to obtain shaped amplification filter signals, and sending the shaped amplification filter signals to the calibration main control circuit 17.

In this embodiment, when the amplifying and filtering circuit 10 includes the pre-amplifying circuit 12 and the first amplifying and filtering circuit 13, the shaping circuit is specifically connected to the first amplifying and filtering circuit 13; when the amplifying and filtering circuit 10 comprises the pre-amplifying circuit 12, the first amplifying and filtering circuit 13 and the second amplifying and filtering circuit 14, the shaping circuit is specifically connected with the second amplifying and filtering circuit 14; as shown in fig. 5, when the amplification filter circuit 10 includes the pre-amplification circuit 12, the first amplification filter circuit 13, the second amplification filter circuit 14, and the third amplification filter circuit 15, the shaping circuit 16 is specifically connected to the third amplification filter circuit 15.

Specifically, the shaping circuit is specifically configured to receive the amplified filtered signal from the amplified filtering circuit 10, convert the amplified filtered signal into a square wave signal to obtain a shaped amplified filtered signal, and send the shaped amplified filtered signal to the calibration main control circuit 17.

In this embodiment, a schematic diagram of the first sensing circuit 11 and the preamplifier circuit 12 is shown in fig. 6, and the preamplifier circuit 12 is a circuit including an electronic component such as a J-fet Q1, a triode Q2, a capacitor, and a resistor;

the schematic diagram of the first amplification filter circuit 13 is shown in fig. 7, and includes a first amplification sub-circuit 131 and a first filter sub-circuit 132, where the first amplification sub-circuit 131 is a circuit including electronic components such as a non-inverting amplifier U1, a resistor, and a capacitor; the first filter sub-circuit 132 is a circuit including electronic components such as a crystal X1, a resistor, and a capacitor. The OUT0 terminal in fig. 7 is connected to the OUT0 terminal in fig. 6.

Specifically, the specific working method of the first amplification filter circuit 13 is as follows: the first amplifying sub-circuit 131 receives the pre-amplified signal from the pre-amplifying circuit 12, performs a first-stage in-phase amplification on the pre-amplified signal to obtain a first-stage amplified signal, and sends the first-stage amplified signal to the first filtering sub-circuit 132, and the first filtering sub-circuit 132 filters the first-stage amplified signal to obtain a first amplified filtered signal, and sends the first amplified filtered signal to the second amplifying and filtering circuit 14.

The circuit schematic diagram of the second amplification and filtering circuit 14 is shown in fig. 8, and includes a second amplification sub-circuit 141 and a second filtering sub-circuit 142, where the second amplification sub-circuit 141 is a circuit including electronic components such as a non-inverting amplifier U2A, a resistor, and a capacitor; the second filter sub-circuit 142 is a circuit including electronic components such as a crystal X2, a resistor, and a capacitor. The OUT1 terminal in fig. 8 is connected to the OUT1 terminal in fig. 7.

Specifically, the specific working method of the second amplification filter circuit 14 is as follows: the second amplifying sub-circuit 141 receives the first amplified and filtered signal from the first amplifying and filtering circuit 13, performs second-stage in-phase amplification on the first amplified and filtered signal to obtain a second-stage amplified signal, and sends the second-stage amplified signal to the second filtering sub-circuit 142, and the second filtering sub-circuit 142 filters the second-stage amplified signal to obtain a second amplified and filtered signal, and sends the second amplified and filtered signal to the third amplifying and filtering circuit 15.

The circuit schematic diagram of the third amplification and filtering circuit 15 is shown in fig. 9, the third amplification and filtering circuit 15 includes a third amplification sub-circuit 151 and a third filtering sub-circuit 152, and the third amplification sub-circuit 151 is a circuit including electronic components such as a non-inverting amplifier U2B, a resistor, and a capacitor; the third filter sub-circuit 152 is a circuit including electronic components such as a crystal X3, a resistor, and a capacitor. The OUT2 terminal in fig. 9 is connected to the OUT2 terminal in fig. 8.

Specifically, the third amplification filter circuit 15 specifically operates as follows: the third amplifying sub-circuit 151 receives the second amplified and filtered information from the second amplifying and filtering circuit 14, performs third-stage in-phase amplification on the second amplified and filtered signal to obtain a third-stage amplified signal, and sends the third-stage amplified signal to the third filtering sub-circuit 152, where the third filtering sub-circuit 152 filters the third-stage amplified signal to obtain an amplified and filtered signal, and sends the amplified and filtered signal to the shaping circuit 16.

Optionally, in this embodiment, as shown in fig. 10, the shaping circuit 16 includes a shaping sub-circuit 161 and a prompt sub-circuit 162. Further, the shaping circuit 16 operates as follows: the shaping sub-circuit 161 receives the amplified and filtered signal from the third amplified and filtered circuit 15, converts the amplified and filtered signal into a square wave signal to obtain a shaped amplified and filtered signal, sends the shaped amplified and filtered signal to the calibration main control circuit 17, and controls the prompting sub-circuit 162 to prompt the user that the shaped amplified and filtered signal is output.

The shaping sub-circuit 161 is specifically a circuit including a chip U3 and electronic components such as a resistor and a capacitor; the cue sub-circuit 162 is a circuit including electronic components such as a transistor Q3, a diode, a resistor, and a capacitor. The OUT3 terminal in fig. 10 is connected to the OUT3 terminal in fig. 9. When the chip U3 in the shaping sub-circuit 161 outputs the shaped amplified filter signal, the chip U3 controls the LED0 in the prompt sub-circuit 162 to emit light, and when the chip U3 in the shaping sub-circuit 161 does not output the shaped amplified filter signal, the chip U3 controls the LED0 in the prompt sub-circuit 162 to emit no light.

The schematic circuit diagram of the calibration main control circuit 17 is shown in fig. 11, and specifically includes a chip U2, electronic components such as a resistor and a capacitor, and an active crystal sub-circuit, where the active crystal sub-circuit includes an active crystal W1 and a capacitor electronic component. The INP pin of the chip U2 in fig. 11 is connected to the OTP4 terminal in the shaping circuit 16 for receiving the shaped amplified filtered signal from the shaping circuit 16; the CLK pin of the chip U2 is connected to the satellite signal receiver for receiving the standard second signal from the satellite signal receiver. The satellite signal receiver may be embodied as a GPS receiver, for example.

In this embodiment, when the writing device 2 includes the second sensing circuit 21 and the second sensing circuit 21 is an electromagnetic induction circuit, as shown in fig. 12, the second sensing circuit 21 is specifically a circuit including an active crystal oscillator subcircuit, an and subcircuit, and an inductor subcircuit, where the active crystal oscillator subcircuit is a circuit including an active crystal oscillator Y1 component, the and subcircuit is a circuit including an electronic component such as a logic and gate Y7 and a capacitor, the inductor subcircuit is a circuit including an electronic component such as an induction antenna L1, a resistor, a capacitor, and a MOS transistor Q1, the active crystal oscillator subcircuit is connected to the and subcircuit, and the and subcircuit is connected to the inductor subcircuit; the OTP _ DAT terminal of FIG. 12 is connected to the TXD pin of chip U2 of FIG. 11.

Optionally, the calibration system of the present embodiment further includes a switching device, as shown in fig. 13, the switching device 3 includes a first switching circuit 31;

the first switch circuit 31 is connected to the calibration main control circuit 17, and is configured to send a calibration notification to the calibration main control circuit 17 when receiving the calibration notification from the user;

for example, the first switch circuit 31 is a key switch circuit, and when a user presses a key in the key switch circuit, a calibration notification is received from the user.

The calibration master circuit 17 is also connected to the first switch circuit 31, and starts operating when receiving a calibration notification from the first switch circuit.

In the present invention, the terminals V1, V2, V3 and V4 in the schematic diagram are connected to a power supply.

As shown in fig. 14, the calibration system of the present embodiment may include at least two calibration devices 1 and at least two writing devices 2, and the calibration devices and the writing devices connected to each other correspond to the same product under test.

An application scenario of the present embodiment is as follows: after the calibration device 1 is aligned with the product to be tested, the circuits of the calibration device 1 except the calibration main control circuit 17 start to work, when the user presses the key of the first switch circuit 31, the calibration main control circuit 17 starts to work, and after obtaining the frequency compensation value, the frequency compensation value is sent to the writing device 2, and the writing device 2 writes the frequency compensation value into the product to be tested in a non-contact electromagnetic induction mode, a light induction mode or a contact mode.

Compared with the prior art, the technical scheme provided by the invention has the beneficial effects that: according to the calibration system provided by the invention, the crystal signal is acquired through the first induction circuit, an acquisition probe is not needed, and an acquisition probe point is not needed to be arranged on the PCB, so that the space of the PCB is effectively saved and additional equipment is reduced.

In addition, the scheme provided by the invention can realize automatic calibration without manual participation, thereby saving labor force and improving calibration efficiency; when the write-in device writes the frequency compensation value into the tested product in an induction mode, the calibration system provided by the invention can acquire crystal signals through a first induction circuit non-contact induction method, and writes the frequency compensation value into the tested product through a second induction circuit non-contact induction mode without arranging a detection point on a PCB of the tested product, so that the PCB space of the tested product is further saved, the calibration system is suitable for a semi-finished product stage and a finished product stage of the tested product, and when the crystal frequency of the tested product in the finished product stage is calibrated, a shell of the tested product does not need to be detached, the rejection rate can be reduced, and the operation is convenient. Finally, the scheme disclosed by the invention can calibrate the crystal frequency of a plurality of tested products at one time, and improves the working efficiency.

Example 2

As shown in fig. 15, in this embodiment, on the basis of the calibration system provided in embodiment 1, the calibration apparatus 1 further includes a first notification circuit 18; the switching device 3 further comprises a second switching circuit 32;

the calibration main control circuit 17 is further connected to the first notification circuit 18, and is configured to control the first notification circuit 18 to notify the user of obtaining the frequency compensation value after obtaining the frequency compensation value;

a first notification circuit 18, connected to the calibration main control circuit 17, for notifying a user of obtaining a frequency compensation value under the control of the calibration main control circuit 17;

for example, the first notification circuit 18 may be embodied as one or more of a sound, an indicator light, and a display screen notification circuit.

As shown in fig. 16, the first notification circuit 18 is an indicator light prompting circuit, and includes a light emitting diode D1 and a resistor R4. When the calibration master circuit 17 obtains the frequency compensation value, the first notification circuit 18 is controlled to emit light to notify the user of the obtained frequency compensation value.

A second switch circuit 32 connected to the calibration main control circuit 17, and configured to send a write notification to the calibration main control circuit 17 when receiving the write notification from the user;

for example, the second switch circuit 32 is a key switch circuit, and receives a write notification from a user when the user presses a key in the key switch circuit.

The calibration master circuit 17 is further connected to the second switch circuit 32, and is specifically configured to send the frequency compensation value to the writing device 2 when receiving the write notification from the second switch circuit 32.

Optionally, as shown in fig. 17, in this embodiment, the writing device 2 specifically includes a writing master control circuit 22 and a second sensing circuit 21;

the calibration main control circuit 17 is further connected to the write-in main control circuit 22, and is specifically configured to send the frequency compensation value to the write-in main control circuit 22 when receiving a write-in notification from the second switch circuit 32;

the writing main control circuit 22 is connected with the calibration main control circuit 17 and the second sensing circuit 21, and is used for receiving the frequency compensation value from the calibration main control circuit 17 and sending the frequency compensation value to the second sensing circuit 21;

as shown in fig. 18, the write master circuit 22 is a circuit including a chip U4, a resistor, and a capacitor.

And the second sensing circuit 21 is connected with the write-in main control circuit 22, and is used for receiving the frequency compensation value from the write-in main control circuit 22 and writing the frequency compensation value into the tested product.

For example, the connection relationship among the calibration main control circuit 17, the write main control circuit 22, and the second sensing circuit 21 is as follows: the RXD pin of the chip U4 in the write master circuit 22 is connected to the TXD pin of the chip U2 of the calibration master circuit 17 in FIG. 11, and the OTP _ DAT pin of the chip U4 is connected to the OTP _ DAT terminal in the second sensing circuit 21 shown in FIG. 12.

Alternatively, as shown in fig. 19, in this embodiment, on the basis of the calibration system provided in embodiment 1, the writing device 2 includes a writing master circuit 22 and a second sensing circuit 21; the calibration device 1 further comprises a first notification circuit 18, the switching device 3 further comprises a second switching circuit 32;

a second switch circuit 32 connected to the write master control circuit 22, and configured to send a write notification to the write master control circuit 22 when receiving the write notification from the user;

the calibration main control circuit 17 is further connected to the write-in main control circuit 22, and is specifically configured to send the frequency compensation value to the write-in main control circuit 22 when receiving a write-in notification from the write-in main control circuit 22;

the write-in main control circuit 22 is connected with the second switch circuit 32, the second sensing circuit 21 and the calibration main control circuit 17, and is configured to send a write-in notification to the calibration main control circuit 17 when receiving the write-in notification from the second switch circuit 32, receive the frequency compensation value from the calibration main control circuit 17, and send the frequency compensation value to the second sensing circuit 21;

Further, as shown in fig. 20, the writing apparatus 2 further includes a receiving circuit 23 and a second notification circuit 24;

the receiving circuit 23 is connected to the write-in main control circuit 22, and is configured to receive response information from a product to be tested, and send the received response information to the write-in main control circuit 22;

as shown in fig. 21, the receiving circuit 23 is a circuit including electronic components such as a diode, a resistor, a capacitor, a signal amplifier, and a signal shaper; when the second sensing circuit is an electromagnetic induction circuit, the DATA _ IN _ TEXP terminal of the receiving circuit 23 is connected to the DATA _ IN _ TEXP terminal of the second sensing circuit 21 IN fig. 12 of embodiment 1, and the DATA _ IN terminal of the receiving circuit 23 is connected to the DATA _ IN pin of the chip U4 IN fig. 18.

The writing master control circuit 22 is further connected to the receiving circuit 23 and the second notification circuit 24, and is further configured to control the second notification circuit 24 to notify the user of completion of writing when receiving the response information from the receiving circuit 23;

and a second notification circuit 24 connected to the write master circuit 22 for notifying the user of the completion of writing under the control of the write master circuit 22.

For example, the second notification circuit 24 may be embodied by one or more of a sound, an indicator light, and a display notification circuit.

As shown in fig. 22, the second notification circuit 24 is an indicator light notification circuit, and includes a light emitting diode D4 and a resistor R16, and a terminal 26 of the second notification circuit is connected to a pin 26 of U4 of the write master circuit 22. When the write master circuit 22 receives the response information from the receiving circuit 23, it controls the D4 in the second notification circuit 24 to emit light to notify the user of the completion of writing.

In this embodiment, the connection between the second switch circuit 32 and the write master circuit 22 in fig. 20 may be replaced by: the second switch circuit 32 is connected to the calibration master circuit 17, and when receiving a write notification from a user, the second switch circuit 32 transmits the write notification to the calibration master circuit 17, as shown in fig. 23.

The calibration device 1 and the writing device 2 in this embodiment are two separate devices.

An application scenario of the present embodiment is as follows: after the calibration device is aligned with the tested product, the circuits except the calibration main control circuit 17 in the calibration device 1 start to work, when the user presses the key in the first switch circuit 31, the calibration main control circuit 17 starts to work to obtain the frequency compensation value and then controls the first notification circuit 18 to notify the user to finish writing, the user aligns the tested product with the writing device 2, when the user presses the key in the second switch circuit 32, the writing main control circuit 22 starts to work, the second induction circuit 21 writes the frequency compensation value into the tested product in a non-connection induction mode, and when the writing main control circuit 22 receives the response information of the receiving circuit 23, the writing main control circuit 24 controls the second notification circuit 24 to notify the user to finish writing.

Example 3

In this embodiment, on the basis of the calibration system provided in embodiment 1, the writing device 2 includes a second sensing circuit 21, a receiving circuit 23, and a second notification circuit 24;

the calibration main control circuit 17 is specifically connected with the second sensing circuit 21, and is specifically configured to send the frequency compensation value to the second sensing circuit 21;

the second sensing circuit 21 is connected with the calibration main control circuit 17 and is used for receiving the frequency compensation value from the calibration main control circuit 17 and writing the frequency compensation value into a tested product;

the receiving circuit 23 is connected with the calibration main control circuit 17 and is used for receiving the response information from the tested product and sending the received response information to the calibration main control circuit 17;

the receiving circuit 23 in this embodiment is the same as the receiving circuit 23 in embodiment 2, and is not described again here. Note that, IN the present embodiment, the DATA _ IN terminal of the receiving circuit 23 is connected to the C2D pin of the chip U2 IN fig. 11.

The calibration main control circuit 17 is further connected to the receiving circuit 23 and the second notification circuit 24, and is configured to control the second notification circuit 24 to notify the user of completing the writing when receiving the response information from the receiving circuit 23;

and a second notification circuit 24 connected to the calibration master circuit 17, for notifying the user of the completion of the writing under the control of the calibration master circuit 17.

The second notification circuit 24 in this embodiment is the same as the second notification circuit 24 in embodiment 2, and is not described again here. In this embodiment, the terminal 26 of the second notification circuit 24 shown in fig. 22 is connected to the pin of the LED2 of the chip U2 in fig. 11.

The calibration device 1 and the writing device 2 in embodiment 1 and embodiment 3 are integrated into one device.

An application scenario of the present embodiment is as follows: after the calibration device 1 is aligned with the tested product, the circuits except the calibration main control circuit 17 in the calibration device 1 start to work, when a user presses a key in the first switch circuit 31, the calibration main control circuit 17 starts to work to obtain a frequency compensation value, the frequency compensation value is sent to the second induction circuit 21, the second induction circuit 21 writes the frequency compensation value into the tested product in a non-contact induction mode, and when the calibration main control circuit 17 receives response information from the receiving circuit 23, the second notification circuit 24 is controlled to notify the user of completing the writing.

Example 4

As shown in fig. 24, this embodiment provides a calibration system for a crystal frequency, and further includes, on the basis of the calibration system provided in embodiment 1, a first master control device 4, a second master control device 5, a first splitter device 6 including at least one input address port and one output port, a second splitter device 7 including at least one output address port and one input port, and a switch device 3 including a second switch circuit 32; the calibration device 1 further comprises a first notification circuit 18; the input address port in the first shunting device 6 and the output address port in the second shunting device 7 have a corresponding relationship, and the calibration main control circuit 17 and the writing device 2, which are connected with the input address port and the output address port having the corresponding relationship, correspond to the same tested product;

the calibration main control circuit 17 is further connected to one input address port of the first shunting device 6, and is specifically configured to send the frequency compensation value to the first shunting device 6;

each input address port of the first branch device 6 is connected with one calibration main control circuit 17, is connected with the first main control device 4 through an output port, and is used for receiving the frequency compensation value from each calibration main control circuit 17, sending the received frequency compensation value to the first main control device 4, and sending the notification of completing the reception to the corresponding calibration main control circuit 17 when receiving the notification of completing the reception from the first main control device 4;

a calibration master circuit 17, further connected to the first notification circuit 18, and configured to control the first notification circuit 18 to notify the user that writing is available when receiving a notification of completion of reception from the first shunt device 6;

a first notification circuit 18 connected to the calibration master circuit 17, for notifying a user that writing is possible under the control of the calibration master circuit 17;

a second switch circuit 32 connected to the first master control apparatus 4, and configured to send a write notification to the first master control apparatus 4 when receiving the write notification from the user;

the first main control device 4 is connected with the second switch circuit 32, the output port of the first shunt device 6 and the second main control device 5, and is used for receiving the frequency compensation value from the first shunt device 6, storing the received frequency compensation value and sending a notification of completing the receiving to the first shunt device; for transmitting the stored frequency compensation value to the second main control device 5 when receiving the write notification from the second switch circuit 32;

fig. 25 shows a schematic circuit diagram of the first master control device 4, which is specifically a circuit including a first master control chip U5A, resistors, capacitors, crystals and other electronic components; fig. 26 shows a schematic circuit diagram of the first shunting device 6, which is specifically a circuit including a first shunting chip U81, and electronic components such as a resistor and a capacitor; as shown in fig. 25 and 26, the READER _ RX pin in chip U81 is connected to the READER _ TX pin in chip U5A in fig. 25; the RX1_1 pin-RX 1_8 pin of the chip U81 is connected to the corresponding TXD pin of the chip U2 in the calibration master circuit 17 shown in FIG. 11.

The second main control device 5 is connected with the input ports of the first main control device 4 and the second branch device 7, and is used for receiving the frequency compensation value from the first main control device 4 and sending the received frequency compensation value to the second branch device 7;

the second branch device 7 is connected with the second main control device 5 through an input port of the second branch device, and each output address port is connected with one writing device 2 and used for receiving the frequency compensation value from the second main control device 5 and sending the received frequency compensation value to the corresponding writing device 2;

a schematic circuit diagram of the second master control device 5 is shown in fig. 27, and specifically is a circuit including electronic elements such as a second master control chip U6A, resistors, capacitors, and crystals; fig. 28 shows a schematic circuit diagram of the second shunting device 7, which is specifically a circuit including electronic components such as a second shunting chip U82, a resistor, a capacitor, and the like; as shown in fig. 28 and 27, the READER _ RX pin in chip U82 is connected to the READER _ TX pin in chip U6A; the RX1_1 pin-RX 1-8 pin of the chip U82 is connected to a writing device 2, for example, the RX1_1 pin of the chip U82 is connected to the RXD pin of the chip U4 in the writing master control circuit 22 shown in fig. 18.

The ISP _ TX pin of the second master chip U6A is connected to the ISP _ RX pin of the first master chip U5A.

And the writing device 2 is connected with one output address port in the second shunt device 7 and is used for receiving the frequency compensation value from the second shunt device 7 and writing the received frequency compensation value into a corresponding tested product.

For example, two calibration master circuits 17 are respectively connected to the RX1_1 pin and the RX1_2 pin of the first splitter 6, wherein the input address port numbers of the RX1_1 pin and the RX1_2 pin are 001 and 002, respectively; the two write devices are respectively connected with an RX1_1 pin and an RX1_1 pin in the second shunting device 7, wherein the output address port numbers of the RX1_1 pin and the RX1_2 pin are 001 and 002 respectively; the tested product corresponding to the writing device 2 connected with the RX1_1 pin of the second shunting device 7 is the same as the tested product corresponding to the calibration main control circuit 17 connected with the RX1_1 pin of the first shunting device 6; the tested product corresponding to the writing device 2 connected with the RX1_2 pin of the second splitter 7 and the tested product corresponding to the calibration main control circuit 17 connected with the RX1_2 pin of the first splitter 6 are the same;

when receiving the frequency compensation value from the RX1_1 pin, the first router 6 transmits the input address port number 001 and the frequency compensation value corresponding to the RX1_1 pin to the first master control device 4, and when receiving a notification of completion of reception including the input address port number 001 of the first master control device 4, transmits the notification of completion of reception to the calibration master control circuit through the RX1_1 pin corresponding to the input address port number 001;

when receiving the frequency compensation value from the RX1_2 pin, the first router 6 transmits the input address port No. 002 and the frequency compensation value corresponding to the RX1_2 pin to the first master control device 4, and when receiving the notification of completion of reception including the input address port No. 002 of the first master control device 4, transmits the notification of completion of reception to the calibration master control circuit through the RX1_2 pin corresponding to the input address port No. 002;

when receiving the input address port number 001 and the corresponding frequency compensation value, the first master control device 4 correspondingly stores the input address port number 001 and the frequency compensation value, and sends a notification including the completion of the reception of the input address port number 001 to the first router device 6; when receiving the input address port number 002 and the corresponding frequency compensation value, correspondingly storing the input address port number 002 and the frequency compensation value, and sending a notification of completion of reception including the input address port number 002 to the first router 6; when receiving the write notification from the second switch circuit 32, the second master control apparatus 5 transmits the stored input address port number 001 and the corresponding frequency offset value, and the stored input address port number 002 and the corresponding frequency offset value;

when receiving the input address port number 001 and the corresponding frequency compensation value, the second master control device 5 sends the input address port number 001 and the frequency compensation value to the second branch device 7, the second branch device 7 finds the output address port number 001 according to the input address port number 001, finds the pin RX1_1 according to the output address port number 001, and sends the frequency compensation value to the write device 1 connected to the pin RX1_ 1;

when receiving the input address port number 002 and the corresponding frequency compensation value, the second master control device 5 sends the input address port number 002 and the frequency compensation value to the second branch device 7, the second branch device 7 finds the output address port number 002 according to the input address port number 002, finds the pin RX1_2 according to the output address port number 002, and sends the frequency compensation value to the write device 1 connected with the pin RX1_ 2.

The second switch circuit 32 in this embodiment is the same as the second switch circuit 32 in embodiment 2, and is different from embodiment 2 in that the second switch circuit 32 in this embodiment is connected to the first main control device 4; the first notification circuit 18 in this embodiment is the same as the first notification circuit 18 in embodiment 2, and is not described herein again.

Alternatively, as shown in fig. 29, this embodiment further includes, on the basis of the calibration system provided in embodiment 1, a first master control device 4, a second master control device 5, a first splitter device 6 including at least one input address port and one output port, a second splitter device 7 including at least one output address port and one input port, and a switch device 3 including a second switch circuit 32; the calibration device 1 further comprises a first notification circuit 18; the input address port in the first shunting device 6 and the output address port in the second shunting device 7 have a corresponding relationship, and the calibration main control circuit 17 and the writing device 2, which are connected with the input address port and the output address port having the corresponding relationship, correspond to the same tested product;

each input address port of the first shunt device 6 is connected with one calibration main control circuit 17, is connected with the first main control device 4 through an output port, and is used for receiving the frequency compensation value from the calibration main control circuit 17, sending the received frequency compensation value to the first main control device 4, and sending a notification of completing reception to the corresponding calibration main control circuit when receiving the notification of completing reception from the first main control device;

the first main control device 4 is connected with the output port of the first branching device 6, and is used for receiving the frequency compensation value from the first branching device 6, storing the received frequency compensation value, and sending a notification of completing the receiving to the first branching device 6;

a second switch circuit 32 connected to the second master control apparatus 5, and configured to send a write notification to the second master control apparatus 5 when receiving the write notification from the user;

a second master control device 5 connected to the input ports of the second switch circuit 32, the first master control device 4, and the second branching device 7, and configured to transmit a write notification to the first master control device 4 when receiving the write notification from the second switch circuit 32; the frequency compensation device is used for receiving the frequency compensation value from the first main control device 4 and sending the received frequency compensation value to the second branch device 7;

the first main control device 4 is further connected with the second main control device 5, and is configured to send the stored frequency compensation value to the second main control device 5 when receiving a write notification from the second main control device 5;

The first branching device 6 and the second branching device 7 in the present embodiment refer to fig. 26 and 28.

when receiving the frequency compensation value from the RX12 pin, the first router 6 transmits the input address port No. 002 and the frequency compensation value corresponding to the RX1_2 pin to the first master control device 4, and when receiving the notification of completion of reception including the input address port No. 002 of the first master control device 4, transmits the notification of completion of reception to the calibration master control circuit through the RX1_2 pin corresponding to the input address port No. 002;

when receiving the input address port number 001 and the corresponding frequency compensation value, the first master control device 4 correspondingly stores the input address port number 001 and the frequency compensation value, and sends a notification including the completion of the reception of the input address port number 001 to the first router device 6; when receiving the input address port number 002 and the corresponding frequency compensation value, correspondingly storing the input address port number 002 and the frequency compensation value, and sending a notification of completion of reception including the input address port number 002 to the first router 6; when receiving the write notification from the second master control apparatus 5, transmitting the stored input address port number 001 and the corresponding frequency offset value, and the stored input address port number 002 and the corresponding frequency offset value to the second master control apparatus 5;

a second master controller 5 that transmits a write notification to the first master controller 4 when receiving the write notification from the second switch circuit 32, and that transmits an input address port number 001 and a frequency compensation value to the second splitter 7 when receiving the input address port number 001 and the frequency compensation value corresponding thereto, the second splitter 7 finding an output address port number 001 from the input address port number 001, finding a pin RX1_1 from the output address port number 001, and transmitting the frequency compensation value to the writer 1 connected to the RX1_1 pin;

The second switch circuit 32 in this embodiment is the same as the second switch circuit 32 in embodiment 2, and is different from embodiment 2 in that the second switch circuit 32 in this embodiment is connected to the second main control device 5; the first notification circuit 18 in this embodiment is the same as the first notification circuit 18 in embodiment 2, and is not described herein again.

Or, this embodiment further includes, on the basis of the calibration system provided in embodiment 1, a third master control device, a first splitter device including at least one input address port and one output port, a second splitter device including at least one output address port and one input port, and a switch device including a second switch circuit; the calibration device further comprises a first notification circuit; the input address port in the first shunting device 6 and the output address port in the second shunting device 7 have a corresponding relationship, and the calibration main control circuit 17 and the writing device 2, which are connected with the input address port and the output address port having the corresponding relationship, correspond to the same tested product;

the calibration main control circuit 17 is further connected to an input address port of the first shunting device, and is specifically configured to send the frequency compensation value to the first shunting device;

each input address port of the first branch device is connected with one calibration main control circuit 17, is connected with a third main control device through an output port, and is used for receiving the frequency compensation value from the calibration main control circuit 17, sending the received frequency compensation value to the third main control device, and sending the notification of completing the receiving to the corresponding calibration main control circuit 17 when receiving the notification of completing the receiving from the third main control device;

a calibration master circuit 17, further connected to the first notification circuit, and configured to control the first notification circuit 18 to notify the user that writing is possible when receiving a notification of completion of reception from the first branching device 6;

a first notification circuit, connected to the calibration main control circuit 17, for notifying a user that writing is possible under the control of the calibration main control circuit 17;

the second switch circuit is connected with the third main control device and used for sending a write-in notice to the third main control device when receiving the write-in notice from a user;

the third main control device is connected with the second switch circuit, the output port of the first shunt device and the input port of the second shunt device, and is used for receiving the frequency compensation value from the first shunt device and storing the received frequency compensation value; for transmitting the stored frequency compensation value to the second branch means when receiving a write notification from the second switch circuit;

the second branch device is connected with the third main control device through an input port of the second branch device, and each output address port is connected with one writing device 2 and used for receiving the frequency compensation value from the third main control device and sending the received frequency compensation value to the corresponding writing device 2;

and the writing device 2 is connected with one output address port in the second shunt device and is used for receiving the frequency compensation value from the second shunt device and writing the received frequency compensation value into a corresponding tested product.

For example, two calibration master circuits 17 are respectively connected to the RX1_1 pin and the RX1_2 pin of the first splitter 6, wherein the input address port numbers of the RX1_1 pin and the RX1_2 pin of the first splitter 6 are 001 and 002 respectively; the two write devices are respectively connected with an RX1_1 pin and an RX1_1 pin in the second shunting device 7, wherein the output address port numbers of the RX1_1 pin and the RX1_2 pin of the second shunting device 7 are respectively 001 and 002; the tested product corresponding to the writing device 2 connected with the RX1_1 pin of the second shunting device 7 is the same as the tested product corresponding to the calibration main control circuit 17 connected with the RX1_1 pin of the first shunting device 6; the tested product corresponding to the writing device 2 connected with the RX1_2 pin of the second splitter 7 and the tested product corresponding to the calibration main control circuit 17 connected with the RX1_2 pin of the first splitter 6 are the same;

when receiving the frequency compensation value from the RX1_1 pin, the first router 6 transmits the input address port number 001 and the frequency compensation value corresponding to the RX1_1 pin to the third master control device 4, and when receiving a notification of completion of reception including the input address port number 001 from the third master control device, transmits the notification of completion of reception to the calibration master control circuit through the RX1_1 pipe corresponding to the input address port number 001;

when receiving the frequency compensation value from the RX1_2 pin, the first router 6 transmits the input address port number 002 and the frequency compensation value corresponding to the RX1_2 pin to the third master control device 5, and when receiving the notification of completion of reception including the input address port number 002 from the third master control device, transmits the notification of completion of reception to the calibration master control circuit through the RX1_2 pipe corresponding to the input address port number 002;

when the third master control device receives the input address port number 001 and the corresponding frequency compensation value, the third master control device correspondingly stores the input address port number 001 and the frequency compensation value, and sends a notification including the completion of the reception of the input address port number 001 to the first router device 6; when receiving the input address port number 002 and the corresponding frequency compensation value, correspondingly storing the input address port number 002 and the frequency compensation value, and sending a notification of completion of reception including the input address port number 002 to the first router 6; when receiving a write notification from the second switch circuit, the second router 7 transmits the stored address port number 001 and the corresponding frequency compensation value, and the second router 7 transmits the stored address port number 002 and the corresponding frequency compensation value;

when receiving the input address port number 001 and the corresponding frequency compensation value, the second shunting device 7 finds the output address port number 001 according to the input address port number 001, finds the RX1_1 pin according to the output address port number 001, and sends the frequency compensation value to the writing device 1 connected with the RX1_1 pin; when receiving the input address port 002 and the corresponding frequency compensation value, the second shunting device 7 finds the output address port number 002 according to the input address port number 002, finds the RX1_2 pin according to the output address port number, and sends the frequency compensation value to the writing device 1 connected with the RX1_2 pin.

The second switch circuit 32 in this embodiment is the same as the second switch circuit 32 in embodiment 2, and is different from embodiment 2 in that the second switch circuit 32 in this embodiment is connected to a third master control device; the first notification circuit 18 in this embodiment is the same as the first notification circuit 18 in embodiment 2, and is not described herein again.

Or, this embodiment further includes, on the basis of the calibration system provided in embodiment 1, a fourth master control device, a first splitter device including at least one input address port and one output port, and a second splitter device including at least one output address port and one input port; the input address port in the first branch device and the output address port in the second branch device have a corresponding relation, and the calibration device and the writing device which are connected with the input address port and the output address port having the corresponding relation correspond to the same tested product;

the calibration main control circuit is also connected with one input address port of the first shunt device and is specifically used for sending the frequency compensation value to the first shunt device;

each input address port of the first shunt device is connected with one calibration main control circuit, is connected with the fourth main control device through an output port and is used for receiving the frequency compensation value from the calibration main control circuit and sending the received frequency compensation value to the fourth main control device;

the fourth master control device is connected with the output port of the first shunt device and the input port of the second shunt device and is used for sending the received frequency compensation value to the second shunt device when receiving the frequency compensation value from the first shunt device;

the second branch device is connected with the fourth main control device through an input port of the second branch device, and each output address port is connected with one writing device and used for receiving the frequency compensation value from the fourth main control device and sending the received frequency compensation value to the corresponding writing device;

and the writing device is connected with one output address port in the second shunt device and is used for receiving the frequency compensation value from the second shunt device and writing the received frequency compensation value into the corresponding tested product.

For example, two calibration master circuits 17 are respectively connected to the RX1_1 pin and the RX1_2 pin of the first splitter 6, wherein the input address port numbers of the RX1_1 pin and the RX1_2 pin are 001 and 002, respectively; the two write devices are respectively connected with an RX1_1 pin and an RX1_1 pin in the second shunting device 7, wherein the output address port numbers of the RX1_1 pin and the RX1_2 pin in the second shunting device 7 are respectively 001 and 002; the tested product corresponding to the writing device 2 connected with the RX1_1 pin in the second shunting device 7 is the same as the tested product corresponding to the calibration main control circuit 17 connected with the RX1_1 pin in the first shunting device 6; the tested product corresponding to the writing device 2 connected with the RX1_2 pin in the second shunting device 7 is the same as the tested product corresponding to the calibration main control circuit 17 connected with the RX1_2 pin in the first shunting device 6;

when receiving the frequency compensation value from the RX1_1 pin, the first shunting device 6 sends the input address port number 001 and the frequency compensation value corresponding to the RX1_1 pin to the fourth master control device; when receiving the frequency compensation value from the RX1_2 pin, sending the input address port number 002 and the frequency compensation value corresponding to the RX1_2 pin to the fourth master control device;

when the fourth master control device receives the input address port number 001 and the corresponding frequency compensation value, the fourth master control device sends the input address port number 001 and the frequency compensation value to the second branch device 7; when receiving the input address port number 002 and the corresponding frequency compensation value, the input address port number 002 and the frequency compensation value are sent to the second router 7;

Example 5

The embodiment provides a calibration method of crystal frequency, which is applied to a system comprising a calibration device and a writing device; the calibration device comprises a first induction circuit, a pre-amplification circuit, a first amplification filter circuit, a second amplification filter circuit, a third amplification filter circuit, a shaping circuit and a calibration main control circuit, and as shown in fig. 30, the calibration device comprises the following steps:

step 101: the pre-amplification circuit acquires a crystal signal of a product to be detected through the first induction circuit, pre-amplifies the crystal signal to obtain a pre-amplified signal, and sends the pre-amplified signal to the first amplification filter circuit;

specifically, the preamplifier circuit obtains a crystal signal of a detected product through the first sensing circuit, specifically: the first induction circuit collects crystal signals of a detected product through electromagnetic induction or mechanical induction and sends the crystal signals to the preamplifier circuit.

In this embodiment, the first sensing circuit includes a magnetic sensor probe, wherein the magnetic sensor probe includes a sensing antenna; alternatively, the first sensing circuit comprises a piezoelectric sensor probe.

For example, the first sensing circuit collects the crystal signal of the product to be detected through its own magnetic sensor probe (i.e. electromagnetic induction), or collects the crystal signal of the product to be detected through its own piezoelectric sensor probe (i.e. mechanical induction), and sends the crystal signal to the pre-amplification circuit.

Step 102: the first amplification filtering circuit amplifies and filters the pre-amplified signal to obtain a first amplification filtering signal, and the first amplification filtering signal is sent to the second amplification filtering circuit;

in this embodiment, the first amplifying and filtering circuit includes a first amplifying sub-circuit and a first filtering sub-circuit; correspondingly, step 102 specifically includes: the first amplifying sub-circuit performs first-stage in-phase amplification on the pre-amplified signal to obtain a first-stage amplified signal, the first-stage amplified signal is sent to the first filtering sub-circuit, the first filtering sub-circuit performs filtering on the first-stage amplified signal to obtain a first amplified and filtered signal, and the first amplified and filtered signal is sent to the second amplifying and filtering circuit.

Step 103: the second amplifying and filtering circuit amplifies and filters the first amplifying and filtering signal to obtain a second amplifying and filtering signal, and the second amplifying and filtering signal is sent to a third amplifying and filtering circuit;

in this embodiment, the second amplifying and filtering circuit includes a second amplifying sub-circuit and a second filtering sub-circuit, and accordingly, step 103 specifically includes: the second amplifying sub-circuit performs second-stage in-phase amplification on the first amplifying and filtering signal to obtain a second-stage amplifying signal, the second-stage amplifying signal is sent to the second filtering sub-circuit, the second filtering sub-circuit performs filtering on the second-stage amplifying signal to obtain a second amplifying and filtering signal, and the second amplifying and filtering signal is sent to the third amplifying and filtering circuit.

Step 104: the third amplifying and filtering circuit amplifies and filters the second amplifying and filtering signal to obtain an amplifying and filtering signal, and the amplifying and filtering signal is sent to the shaping circuit;

in this embodiment, the third amplifying and filtering circuit includes a third amplifying sub-circuit and a third filtering sub-circuit; correspondingly, step 104 specifically includes: the third amplifying sub-circuit performs third-stage in-phase amplification on the second amplified and filtered signal to obtain a third-stage amplified signal, the third-stage amplified signal is sent to the third filtering sub-circuit, the third filtering sub-circuit performs filtering on the third-stage amplified signal to obtain an amplified and filtered signal, and the amplified and filtered signal is sent to the shaping circuit.

Step 105: the shaping circuit shapes the amplified filtering signal to obtain a shaped amplified filtering signal, and the shaped amplified filtering signal is sent to the calibration main control circuit;

specifically, the shaping circuit shapes the amplified filtered signal to obtain a shaped amplified filtered signal, and specifically includes: the shaping circuit converts the amplified filtering signal into a square wave signal to obtain a shaped amplified filtering signal.

Step 106: the calibration main control circuit obtains a first count value of the system clock according to the shaped amplified filtering signal and a preset value;

specifically, the calibration main control circuit obtains a first count value of the system clock according to the shaped amplified filtering signal and a preset value, and specifically includes: measuring a count value of a system clock when a signal of a preset value period is obtained from the shaped amplified filtering signal, and taking the count value of the system clock as a first count value of the system clock;

For example, taking a time-type dynamic token as an example, if the standard crystal frequency is 32768Hz, the preset value is 32768 Hz; the calibration main control circuit measures a count value C4 of a system clock when signals of 32768 periods are acquired from the shaped amplified and filtered signals, and takes the count value C4 of the system clock as a first count value C1 of the system clock;

or, specifically: and measuring the count value of the system clock when the signals of a preset multiple of the preset value and a plurality of cycles are obtained from the shaped amplified filtering signals, and dividing the count value of the system clock by the preset multiple to obtain a first count value of the system clock. For example, the preset multiple is 0.5 times, or any of 2 times to 10 times.

For example, taking a time-type dynamic token as an example, if the standard crystal frequency is 32768Hz, the preset value is 32768 Hz; the calibration master circuit measures a count value C3 of the system clock when a signal of 98304(3 times of 32768) cycles is acquired from the shaped amplified and filtered signal, and divides the count value C3 of the system clock by 3 to obtain a first count value C1 of the system clock.

Step 107: the calibration main control circuit acquires a standard second signal and obtains a second count value of the system clock according to the standard second signal;

specifically, the calibration master control circuit collects standard second signals, specifically: the calibration main control circuit collects standard second signals through a GPS satellite signal receiver.

Specifically, the calibration main control circuit obtains a second count value of the system clock according to the standard second signal, specifically: the calibration main control circuit measures the count value of the system clock in a standard second signal, and the count value of the system clock is used as a second count value of the system clock;

Or, specifically: the calibration main control circuit measures the count value of the system clock in the preset number of standard second signals, and divides the count value of the system clock by the preset number to obtain a second count value of the system clock.

In this embodiment, the order of step 106 and step 107 may be reversed.

Step 108: the calibration main control circuit obtains a frequency compensation value according to a first counting value of the system clock and a second counting value of the system clock;

specifically, step 108 specifically includes: the calibration main control circuit subtracts the first count value of the system clock from the second count value of the system clock to obtain a system clock count difference value, divides the system clock count difference value by the first count value of the system clock to obtain a quotient, and multiplies the quotient by a preset value to obtain a frequency compensation value.

Will quotient value

Step 109: and the calibration main control circuit writes the frequency compensation value into the tested product through a second induction circuit in the writing device.

Specifically, step 109 specifically includes: the calibration main control circuit sends the frequency compensation value to the writing device, and a second induction circuit in the writing device writes the frequency compensation value into a main control chip of a tested product in an electromagnetic induction mode.

Optionally, the method further includes: the calibration master waits to receive an acquisition notification from the user, and when an acquisition notification is received from the user, step 106 is executed or step 107 is executed. Before step 106 or step 107 is executed, the calibration master circuit does not work, and step 106 or step 107 is executed only when the acquisition notice of the user is received.

For example, the calibration device is provided with an acquisition switch connected to the calibration main control circuit, and when the user turns on the acquisition switch, the calibration main control circuit receives an acquisition notification from the user, and executes step 106 or step 107.

Optionally, step 108 is followed by: the calibration main control circuit informs a user of completing writing; alternatively, the writing means notifies the user of the completion of the writing.

For example, the calibration master control circuit prompts the user to complete the writing by at least one of sound, a display screen, and an indicator light.

Specifically, the calibration main control circuit notifies the user of completing writing, specifically: after the writing device receives the response information from the tested product through the receiving unit, the calibration main control circuit is informed to complete writing, and the calibration main control circuit informs a user to complete writing through the informing unit.

An application scenario of the present embodiment is as follows: after the calibration device is aligned with the product to be tested, step 101-step 105 are started to be executed, when the user opens the acquisition switch on the calibration main control circuit, the calibration main control circuit receives the acquisition notification, step 106-step 109 are started to be executed, and after the calibration main control circuit finishes step 109, the user is notified to finish writing.

According to the invention, the crystal signal of the tested product is acquired through the first sensing circuit, the frequency compensation value is written into the main control chip of the tested product through the writing device, and in the processes of acquiring the crystal signal of the tested product and writing the frequency compensation value into the main control chip of the tested product, a jack does not need to be arranged on the shell of the tested product, and a detection point does not need to be arranged on the PCB of the tested product, so that the space of the PCB is saved.

The beneficial effect of this embodiment is: in the process of calibrating the crystal frequency of a tested product, automatic calibration can be realized, manual participation is not needed, labor force is saved, and calibration efficiency is improved. Meanwhile, the technical scheme provided by the embodiment does not need to set a detection point on the PCB of the tested product, and the space of the PCB is effectively saved.

Example 6

The embodiment provides a calibration method of crystal frequency, which is applied to a system comprising a calibration device and a writing device, wherein the calibration device comprises a first induction circuit, a pre-amplification circuit, a first amplification filter circuit, a second amplification filter circuit, a third amplification filter circuit, a shaping circuit and a calibration main control circuit; the writing device comprises a second sensing circuit; as shown in fig. 31, the method includes the following steps:

step 301: the pre-amplification circuit acquires a crystal signal of a product to be detected through the first induction circuit, pre-amplifies the crystal signal to obtain a pre-amplified signal, and sends the pre-amplified signal to the first amplification filter circuit;

step 301 of this embodiment is the same as step 101 of embodiment 5, and will not be described again here.

Step 302: the first amplification filtering circuit amplifies and filters the pre-amplified signal to obtain a first amplification filtering signal, and the first amplification filtering signal is sent to the second amplification filtering circuit;

step 303: the second amplifying and filtering circuit amplifies and filters the first amplifying and filtering signal to obtain a second amplifying and filtering signal, and the second amplifying and filtering signal is sent to a third amplifying and filtering circuit;

step 304: the third amplifying and filtering circuit amplifies and filters the second amplifying and filtering signal to obtain an amplifying and filtering signal, and the amplifying and filtering signal is sent to the shaping circuit;

step 305: the shaping circuit shapes the amplified filtering signal to obtain a shaped amplified filtering signal, and the shaped amplified filtering signal is sent to the calibration main control circuit;

Step 306: the calibration main control circuit obtains a first count value of the system clock according to the shaped amplified filtering signal and a preset value;

specifically, step 306 specifically refers to step 106 in embodiment 5, and is not described herein again.

Step 307: the calibration main control circuit acquires a standard second signal and obtains a second count value of the system clock according to the standard second signal;

specifically, step 307 specifically refers to step 107 in embodiment 5, and is not described herein again.

In this embodiment, the order of step 306 and step 307 may be exchanged.

Step 308: the calibration main control circuit obtains a frequency compensation value according to a first counting value of the system clock and a second counting value of the system clock, and informs a user of obtaining the frequency compensation value.

In this embodiment, the calibration apparatus obtains the frequency compensation value according to the first count value of the system clock and the second count value of the system clock in step 308, which is specifically referred to step 108 in embodiment 5 and is not described herein again.

In step 308, the step of informing the user of the frequency compensation value by the calibration main control circuit is specifically as follows: the calibration main control circuit informs a user of obtaining the frequency compensation value through at least one of sound, a display screen and an indicator lamp.

Step 309: the calibration main control circuit waits for receiving a writing notification from a user, and sends a frequency compensation value to a writing device when receiving the writing notification from the user;

the difference between the calibration device in this embodiment and the calibration device in embodiment 5 is: the calibration device in this embodiment has a first notification circuit connected to the calibration main control circuit, and the calibration main control circuit notifies a user of obtaining the frequency compensation value by controlling the first notification circuit after obtaining the frequency compensation value.

For example, the first notification circuit of the calibration device is embodied as at least one of an indicator light notification circuit, a sound notification circuit, and a display screen notification circuit.

Step 310: the writing device writes the frequency compensation value into the tested product through the second induction circuit.

Specifically, the second sensing circuit is an electromagnetic sensing circuit or a light sensing circuit. The writing device in step 310 may also be a writing probe connected to the calibration device, and the frequency compensation value is written into the product under test through the contact between the writing probe and the PCB of the product under test.

Specifically, the writing device writes the frequency compensation value into a main control chip of the tested product.

Specifically, step 310 specifically refers to step 109 in embodiment 5, and is not described herein again.

The writing apparatus in this embodiment is the same as the writing apparatus in embodiment 5, and the difference from embodiment 5 is: the calibration device and the writing device are two separate devices in this example, and the writing device and the calibration device are integrated into one device in example 5.

The present embodiment is also different from embodiment 5 in that: the calibration device or the write-in device is provided with a write-in switch, and when a user turns on the write-in switch, the calibration main control circuit receives a write-in notice from the user and sends the frequency compensation value to the write-in device.

Optionally, before the step 306, the method further includes: the calibration master waits to receive an acquisition notification from the user, and when an acquisition notification is received from the user, either step 306 is executed or step 307 is executed.

For example, the calibration device is provided with an acquisition switch connected with the calibration main control circuit, and when a user turns on the acquisition switch, the calibration main control circuit receives an acquisition notice from the user.

Optionally, the step 310 further includes: the writing device informs the user of completing writing; or after the step 310, the method further includes: the writing device informs the calibration device of completing writing, and the calibration device informs the user of completing writing.

For example, the calibration device informs the user of the completion of the writing, specifically, prompts the user to complete the writing through at least one of sound, a display screen, and an indicator light. The writing device informs the user of completing writing, and specifically prompts the user to complete writing through at least one of sound, a display screen and an indicator lamp.

In this embodiment, when the calibration device notifies the user of the completion of writing, the calibration device notifies the user of the frequency offset value and notifies the user of the completion of writing in such a manner that the user can distinguish which information is notified. For example, the calibration device notifies the user by displaying a yellow indicator light when the user obtains the frequency compensation value, and notifies the user by displaying a red indicator light when the writing is completed.

An application scenario of the present embodiment is as follows: after the calibration device is aligned with the tested product, step 301-step 305 are executed, when the user turns on the acquisition switch on the calibration device, the calibration main control circuit receives the acquisition notification, and step 306-step 309 are started, when the calibration device notifies the user to obtain the frequency compensation value in step 308, the user aligns the tested product with the writing device, the writing switch on the calibration device or the writing device is turned on, the calibration main control circuit sends the frequency compensation value to the writing device after receiving the writing notification, the writing device notifies the user to complete writing after writing the frequency compensation value into the main control chip of the tested product, or notifies the calibration device to complete writing, and the calibration device notifies the user to complete writing.

According to the invention, the crystal signal of the tested product is acquired through the first sensing circuit, and when the frequency compensation value is written into the main control chip of the tested product in an electromagnetic induction or light induction mode, a jack does not need to be arranged on the shell of the tested product in the processes of acquiring the crystal signal of the tested product and writing the frequency compensation value into the main control chip of the tested product, and a detection point does not need to be arranged on the PCB of the tested product, so that the space of the PCB is saved.

The beneficial effect of this embodiment is: in the process of calibrating the crystal frequency of a tested product, automatic calibration can be realized, manual participation is not needed, labor force is saved, and calibration efficiency is improved. When the write-in device in this embodiment adopts the response mode to write in the frequency compensation value into the product under test, need not to set up the probe point on the PCB board of product under test, effectively saves the space of PCB board.

Example 7

The embodiment provides a calibration method of crystal frequency, which is applied to a calibration system comprising at least two calibration devices and at least two writing devices, wherein each calibration device comprises a preamplifier circuit, a first amplification filter circuit, a second amplification filter circuit, a third amplification filter circuit, a shaping circuit and a calibration main control circuit; each write device includes a second sensing circuit; as shown in fig. 32, the method includes the following steps:

step 401: each pre-amplification circuit obtains a crystal signal of a product to be detected through a first induction circuit, pre-amplifies the crystal signal to obtain a pre-amplification signal, and sends the pre-amplification signal to a corresponding first amplification filter circuit;

specifically, each preamplifier circuit obtains a crystal signal of a detected product through a first sensing circuit, specifically: each first induction circuit collects crystal signals of a detected product through electromagnetic induction or mechanical induction and sends the crystal signals to the preamplifier circuit.

Step 402: each first amplifying and filtering circuit amplifies and filters the received pre-amplifying signal to obtain a first amplifying and filtering signal, and sends the first amplifying and filtering signal to a corresponding second amplifying and filtering circuit;

step 403: each second amplification filtering circuit amplifies and filters the received first amplification filtering signal to obtain a second amplification filtering signal, and sends the second amplification filtering signal to a corresponding third amplification filtering circuit;

step 404: each third amplifying and filtering circuit amplifies and filters the received second amplifying and filtering signal to obtain an amplifying and filtering signal, and sends the amplifying and filtering signal to a corresponding shaping circuit;

step 405: each shaping circuit shapes the received amplified filtering signal to obtain a shaped amplified filtering signal, and sends the shaped amplified filtering signal to a corresponding calibration main control circuit;

specifically, each shaping circuit shapes the received amplified filtered signal to obtain a shaped amplified filtered signal, and specifically, the shaping circuit includes: each shaping circuit converts the received amplified and filtered signal into a square wave signal to obtain a shaped amplified and filtered signal.

Step 406: each calibration main control circuit obtains a first count value of the system clock according to the shaped amplified filtering signal and a preset value;

specifically, the operation of each calibration master circuit in step 406 specifically refers to the operation of the calibration master circuit in step 106 in embodiment 5, and is not repeated herein.

Step 407: each calibration master control circuit acquires a standard second signal and obtains a second count value of the system clock according to the standard second signal;

specifically, the operation of each calibration main control circuit in step 407 specifically refers to the operation of the calibration main control circuit in step 107 in embodiment 5, and is not repeated herein.

In this embodiment, the order of executing step 406 and step 407 by each calibration master circuit may be changed.

Step 408: and each calibration main control circuit obtains a frequency compensation value according to the first counting value of the system clock and the second counting value of the system clock.

In this embodiment, the operation of each calibration main control circuit in step 408 specifically refers to the operation of the calibration main control circuit in step 108 in embodiment 5, and is not described herein again.

Step 409: and each calibration main control circuit writes the obtained frequency compensation value into a corresponding tested product through a corresponding writing device.

Specifically, step 409 specifically includes: and each calibration main control circuit writes the obtained frequency compensation value into a main control chip of a corresponding tested product through a corresponding writing device.

Optionally, step 406 is preceded by: each calibration master circuit waits for receiving an acquisition notification from a user, and executes step 406 or step 407 when receiving the acquisition notification from the user;

in this embodiment, when the crystal frequencies of a plurality of products to be tested need to be calibrated, there are a plurality of corresponding calibration devices and writing devices, and each product to be tested has one corresponding calibration device and writing device, and after each calibration device is aligned with the corresponding product to be tested, the user turns on the acquisition switch, and each calibration device receives the acquisition notification at the same time.

In this embodiment, the calibration master control circuit in each calibration device is connected to the acquisition switch, and when the acquisition switch is turned on by a user, each calibration device receives an acquisition notification at the same time; or in this embodiment, the calibration master control circuit of each calibration device is connected to the master control device, and when the user turns on the acquisition switch, the master control device receives the acquisition notification, and then the master control device notifies each calibration master control circuit at the same time.

Optionally, the step 409 further includes: each calibration main control circuit informs a user of completing writing;

in this embodiment, when the calibration master control circuit of each calibration device is connected to the master control device, the step 409 further includes: each calibration main control circuit informs the main control device of completing writing, and when the main control device receives the notification of completing writing of the calibration device, the main control device informs a user of completing writing;

specifically, the main control device notifies the user of completing writing, specifically: after receiving the write-in notification of all the calibration devices, the main control device notifies a user of completing the write-in;

for example, after receiving the write-in completion notification of all the calibration devices, the main control device notifies the user of completion of write-in through at least one of sound, a display screen and an indicator light; each calibration master circuit notifies the user of completing the writing specifically may be: each calibration main control circuit informs a user of completing writing in at least one mode of sound, a display screen and an indicator lamp.

Or, specifically, the main control device notifies the user of completing writing, specifically: after the master control device receives a calibration device write completion notification, the master control device notifies a user that the calibration device completes writing; for example, when the master control device receives a writing completion notification of a calibration device, the master control device notifies a user that the calibration device completes writing through at least one of sound, a display screen and an indicator lamp.

An application scenario of the present embodiment is as follows: each calibration device is connected with the main control device, steps 401-405 are executed after each calibration device is aligned with the corresponding tested product, when a user turns on the acquisition switch, the main control device receives the acquisition notice and notifies all the calibration devices connected with the main control device, after the calibration main control circuit of each calibration device receives the acquisition notice, the steps 406-409 are started, after the main control device completes the step 409, the main control device is notified to complete writing, and when the main control device receives the completion of writing, the user is notified to complete the writing.

Another application scenario of the present embodiment is as follows: and each calibration device is connected with the acquisition switch, the steps 401 to 405 are executed after each calibration device is aligned with the corresponding tested product, the steps 406 to 409 are started after the acquisition switch is turned on by a user and the calibration main control circuit of each calibration device receives an acquisition notice, and the user is informed of completing writing after each calibration device executes the step 409.

According to the invention, the crystal signal of the tested product is acquired through the first induction circuit, and when the frequency compensation value is written into the main control chip of the tested product in an electromagnetic induction mode or a light induction mode, a jack does not need to be arranged on the shell of the tested product in the processes of acquiring the crystal signal of the tested product and writing the frequency compensation value into the main control chip of the tested product, and a detection point does not need to be arranged on the PCB of the tested product, so that the space of the PCB is saved.

The beneficial effect of this embodiment is: in the process of calibrating the crystal frequency of a tested product, automatic calibration can be realized, manual participation is not needed, labor force is saved, and calibration efficiency is improved. Meanwhile, when the frequency compensation value is written into the tested product in an induction mode, a detection point does not need to be arranged on a PCB of the tested product, and the space of the PCB is effectively saved; the embodiment can calibrate the crystals of a plurality of tested products at the same time, and further improves the detection efficiency.

Example 8

The embodiment provides a calibration method of a crystal frequency, which is applied to a calibration system comprising at least two calibration devices, a first master control device, a second master control device, and at least two write-in devices, wherein each calibration device comprises a preamplifier circuit, a first amplifier filter circuit, a second amplifier filter circuit, a third amplifier filter circuit, a shaping circuit, and a calibration master control circuit, and the calibration devices, the write-in devices, and a product to be tested are in one-to-one correspondence, as shown in fig. 33, the calibration method comprises the following steps:

step 501: each pre-amplification circuit acquires a crystal signal of a detected product through a corresponding first induction circuit, pre-amplifies the crystal signal to obtain a pre-amplification signal, and sends the pre-amplification signal to a corresponding first amplification filter circuit;

Step 501 in this embodiment is specifically the same as step 401 in embodiment 7, and is not described herein again.

Step 502: each first amplifying and filtering circuit amplifies and filters the received pre-amplifying signal to obtain a first amplifying and filtering signal, and sends the first amplifying and filtering signal to a corresponding second amplifying and filtering circuit;

step 503: each second amplification filtering circuit amplifies and filters the received first amplification filtering signal to obtain a second amplification filtering signal, and sends the second amplification filtering signal to a corresponding third amplification filtering circuit;

step 504: each third amplifying and filtering circuit amplifies and filters the received second amplifying and filtering signal to obtain an amplifying and filtering signal, and sends the amplifying and filtering signal to a corresponding shaping circuit;

step 505: each shaping circuit shapes the received amplified filtering signal to obtain a shaped amplified filtering signal, and sends the shaped amplified filtering signal to a corresponding calibration main control circuit;

specifically, each shaping circuit shapes a received amplified and filtered signal to obtain a shaped signal, specifically: each shaping circuit converts the received amplified and filtered signal into a square wave signal to obtain a shaped amplified and filtered signal.

Step 506: each calibration main control circuit obtains a first count value of the system clock according to the shaped amplified filtering signal and a preset value;

specifically, the operation of each calibration main control circuit in step 506 specifically refers to the operation of the calibration main control circuit in step 106 in embodiment 5, and is not described herein again.

Step 507: each calibration master control circuit acquires a standard second signal and obtains a second count value of the system clock according to the standard second signal;

specifically, the operation of each calibration main control circuit in step 507 refers to the operation of the calibration main control circuit in step 107 in embodiment 5, and is not repeated herein.

In this embodiment, the order of executing step 506 and step 507 by each calibration master circuit may be changed.

Step 508: each calibration main control circuit obtains a frequency compensation value according to a first counting value of a system clock and a second counting value of the system clock, sends the frequency compensation value to the first main control device, controls the corresponding first notification circuit to notify a user of obtaining the frequency compensation value when receiving a notification that the first main control device finishes receiving, and notifies the user of writing.

In this embodiment, each calibration master control circuit in step 508 obtains a frequency compensation value according to the first count value of the system clock and the second count value of the system clock, which refers to the operation of the calibration master control circuit in step 108 in embodiment 5, and is not described herein again.

Step 509: the first master control device receives and stores the frequency compensation value of the calibration master control circuit.

In this embodiment, when each calibration master control circuit sends the frequency compensation value to the first master control device, the number corresponding to the calibration master control circuit is also sent to the first master control device. And when the first main control device receives the frequency compensation value, correspondingly storing the number corresponding to the calibration main control circuit and the frequency compensation value.

Step 510: the first main control device waits for receiving a writing notification from a user, and when the writing notification from the user is received, the stored frequency compensation value is sent to the second main control device;

and when the first main control device sends the stored frequency compensation value to the second main control device, the first main control device also sends the serial number corresponding to the calibration main control circuit to the second main control device.

Step 511: the second master control device sends the received frequency compensation value to the corresponding writing device;

and when receiving the frequency compensation value, the second main control device sends the frequency compensation value to the writing device corresponding to the number corresponding to the calibration main control circuit.

Step 512: and each writing device writes the received frequency compensation value into the corresponding tested product.

Specifically, each writing device writes the received frequency compensation value into the main control chip of the corresponding product to be tested.

Each writing device in this embodiment is the same as the writing device in embodiment 5, and the difference from embodiment 5 is: in this embodiment, each calibration device and the corresponding writing device are two independent devices, and in embodiment 5, the writing device and the calibration device are integrated into one device.

Optionally, step 506 is preceded by: each calibration master control circuit waits for receiving an acquisition notification from a user, and executes step 506 or step 507 when receiving the acquisition notification from the user;

in this embodiment, when the crystal frequencies of a plurality of products to be tested need to be calibrated, there are a plurality of corresponding calibration devices and writing devices, each product to be tested has one corresponding calibration device and writing device, and after each calibration device is aligned with a corresponding product to be tested, a user turns on the acquisition switch, and the calibration master control circuit in each calibration device receives the acquisition notification at the same time.

In this embodiment, when the user turns on the acquisition switch, each calibration device receives an acquisition notification at the same time; or when the user turns on the acquisition switch, the first main control device receives the acquisition notice, and then the first main control device simultaneously notifies each calibration device.

Optionally, after the step 512, the method further includes: and each writing device informs the second main control device of completing writing, and the second main control device informs the user of completing writing when receiving the notification of completing writing of the writing device. Specifically, when the second master control device receives the notification of completing writing of the writing device, the second master control device notifies the user of completing writing, specifically: and when the second master control device receives the notification of completing the writing of each writing device, notifying a user that the writing device completes the writing.

For example, when the second master control device receives a writing completion notification from a writing device, the second master control device notifies the user that the writing is completed by the writing device through at least one of sound, a display screen, and an indicator light.

Or, specifically, when receiving the notification of completing writing by the writing device, the second master control device notifies the user of completing writing, specifically: and after receiving the write-in completion notification of all the write-in devices, the second master control device uniformly notifies the user of completing the write-in.

For example, after receiving the write completion notification of all the calibration devices, the second master control device notifies the user of the completion of the write through at least one of sound, a display screen, and an indicator light.

An application scenario of the present embodiment is as follows: each calibration device is connected with a first main control device, each writing device is connected with a second main control device, the first main control device is connected with the second main control device, after a user aligns each calibration device with a corresponding tested product, the calibration device starts to execute the step 501-the step 505, when the user opens an acquisition switch, the first main control device receives an acquisition notice and notifies all the calibration devices connected with the first main control device, after each calibration device receives the acquisition notice, the step 506-the step 508 are started to be executed, after all the calibration main control circuits in the step 508 notify the user that the user can write, the user aligns the tested product with the corresponding writing device, the user opens the writing switch, the first main control device receives the writing notice from the user and sends a frequency compensation value to the second main control device, the second main control device sends the corresponding frequency compensation value to the corresponding writing device, and when each writing device receives the corresponding frequency compensation value of the second main control device, writing the corresponding frequency compensation value into the main control chip of the corresponding tested product, informing the second main control device when each writing device finishes the writing operation, and informing a user that the writing device finishes the writing operation.

In this embodiment, the position relationship among each writing device, each calibration device, and each product to be tested corresponds to one another.

According to the invention, the crystal signal of the tested product is acquired through electromagnetic induction or mechanical induction, the frequency compensation value is written into the main control chip of the tested product through an electromagnetic induction mode or a light induction mode, and in the processes of acquiring the crystal signal of the tested product and writing the frequency compensation value into the main control chip of the tested product, a jack does not need to be arranged on the shell of the tested product, and a detection point does not need to be arranged on the PCB of the tested product, so that the space of the PCB is saved.

The beneficial effect of this embodiment is: in the process of calibrating the crystal frequency of a tested product, automatic calibration can be realized, manual participation is not needed, labor force is saved, and calibration efficiency is improved. Meanwhile, the technical scheme provided by the embodiment does not need to arrange a probe point on the PCB of the tested product, so that the space of the PCB is effectively saved; the embodiment can calibrate the crystals of a plurality of tested products at the same time, and further improves the detection efficiency.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A system for calibrating crystal frequency, comprising at least one calibration means and at least one writing means; the calibration device comprises a first induction circuit, an amplification filter circuit and a calibration main control circuit;

the writing device is connected with the calibration main control circuit and used for receiving the frequency compensation value from the calibration main control circuit and writing the frequency compensation value into the tested product;

the calibration system further comprises a switching device comprising a first switching circuit;

the first switch circuit is connected with the calibration main control circuit and used for sending a calibration notice to the calibration main control circuit when receiving the calibration notice from a user;

the calibration main control circuit is also connected with the first switch circuit and starts to work when receiving a calibration notice from the first switch circuit;

the writing device comprises a writing main control circuit and a second sensing circuit; the calibration device further comprises a first notification circuit, and the switching device further comprises a second switching circuit;

the calibration main control circuit is further connected with the first notification circuit and is used for controlling the first notification circuit to notify a user of obtaining the frequency compensation value after obtaining the frequency compensation value;

the first notification circuit is connected with the calibration main control circuit and used for notifying a user of obtaining the frequency compensation value under the control of the calibration main control circuit;

the second switch circuit is connected with the write-in main control circuit and used for sending the write-in notification to the write-in main control circuit when receiving the write-in notification of a user;

the calibration main control circuit is further connected with the write-in main control circuit, and is specifically configured to send the frequency compensation value to the write-in main control circuit when receiving a write-in notification from the write-in main control circuit;

the write-in main control circuit is connected with the second switch circuit, the second sensing circuit and the calibration main control circuit, and is configured to send a write-in notification to the calibration main control circuit when receiving the write-in notification from the second switch circuit, receive the frequency compensation value from the calibration main control circuit, and send the frequency compensation value to the second sensing circuit;

the second sensing circuit is connected with the write-in main control circuit and used for receiving the frequency compensation value from the write-in main control circuit and writing the frequency compensation value into the tested product.

2. The system of claim 1, wherein the amplification filter circuit comprises a pre-amplification circuit and a first amplification filter circuit;

the pre-amplification circuit is connected with the first induction circuit and the first amplification filter circuit, and is used for receiving the crystal signal from the first induction circuit, pre-amplifying the crystal signal to obtain a pre-amplification signal, and sending the pre-amplification signal to the first amplification filter circuit;

the first amplification filter circuit is connected with the pre-amplification circuit and the calibration main control circuit, and is used for receiving the pre-amplification signal from the pre-amplification circuit, amplifying and filtering the pre-amplification signal to obtain the amplification filter signal, and sending the amplification filter signal to the calibration main control circuit.

3. The system of claim 1, wherein the amplification filter circuit comprises a pre-amplification circuit, a first amplification filter circuit, and a second amplification filter circuit;

the first amplification filter circuit is connected with the pre-amplification circuit and the second amplification filter circuit, and is used for receiving the pre-amplification signal from the pre-amplification circuit, amplifying and filtering the pre-amplification signal to obtain a first amplification filter signal, and sending the first amplification filter signal to the second amplification filter circuit;

the second amplification filter circuit is connected with the first amplification filter circuit and the calibration main control circuit, and is used for receiving the first amplification filter signal from the first amplification filter circuit, amplifying and filtering the first amplification filter signal to obtain the amplification filter signal, and sending the amplification filter signal to the calibration main control circuit.

4. The system of claim 1, wherein the amplification filter circuit comprises a pre-amplification circuit, a first amplification filter circuit, a second amplification filter circuit, and a third amplification filter circuit;

the second amplifying and filtering circuit is connected with the first amplifying and filtering circuit and the third amplifying and filtering circuit, and is configured to receive the first amplifying and filtering signal from the first amplifying and filtering circuit, amplify and filter the first amplifying and filtering signal to obtain a second amplifying and filtering signal, and send the second amplifying and filtering signal to the third amplifying and filtering circuit;

the third amplifying and filtering circuit is connected with the second amplifying and filtering circuit and the calibration main control circuit, and is configured to receive the second amplifying and filtering signal from the second amplifying and filtering circuit, amplify and filter the second amplifying and filtering signal to obtain the amplifying and filtering signal, and send the amplifying and filtering signal to the calibration main control circuit.

5. The system of any of claims 1-4, wherein the calibration device further comprises a shaping circuit;

the amplifying and filtering circuit is connected with the calibration main control circuit through the shaping circuit;

the shaping circuit is connected with the amplifying and filtering circuit and the calibration main control circuit and is used for receiving the amplifying and filtering signals from the amplifying and filtering circuit, shaping the amplifying and filtering signals to obtain shaped amplifying and filtering signals, and sending the shaped amplifying and filtering signals to the calibration main control circuit.

6. The system according to claim 5, wherein the shaping circuit is configured to receive the amplified filtered signal from the amplified filtering circuit, convert the amplified filtered signal into a square wave signal to obtain the shaped amplified filtered signal, and send the shaped amplified filtered signal to the calibration master circuit.

7. The system according to claim 1, characterized in that the first sensing circuit is configured to collect the crystal signal of the product under test by electromagnetic induction or mechanical induction, and to send the crystal signal to the amplification and filtering circuit.

8. The system according to claim 1, wherein the calibration master control circuit is specifically configured to measure a count value of a system clock when the signal of the preset number of cycles is obtained from the amplified filtered signal, and use the count value of the system clock as a first count value of the system clock;

or measuring a count value of a system clock when the amplified and filtered signal is obtained as a signal with a preset multiple of the preset value and a plurality of cycles, and dividing the count value of the system clock by the preset multiple to obtain a first count value of the system clock.

9. The system according to claim 1, wherein the calibration master circuit is configured to measure a count value of a system clock within one of the standard second signals, and use the count value of the system clock as a second count value of the system clock;

or measuring the count value of the system clock in the preset number of standard second signals, and dividing the count value of the system clock by the preset number to obtain a second count value of the system clock.

10. The system according to claim 1, wherein the calibration master control circuit is specifically configured to subtract the first count value of the system clock from the second count value of the system clock to obtain a system clock count difference value, divide the system clock count difference value by the first count value of the system clock to obtain a quotient, and multiply the quotient by a preset value to obtain the frequency compensation value.

11. The system according to claim 1, wherein the writing device is specifically configured to receive the frequency compensation value from the calibration master control circuit, and write the frequency compensation value into the product under test by any one of an electromagnetic induction method, an optical induction method, and a contact method.

12. The system of claim 1, wherein the calibration device further comprises a first notification circuit; the switching device further comprises a second switching circuit;

the second switch circuit is connected with the calibration main control circuit and used for sending a write-in notice to the calibration main control circuit when receiving the write-in notice of a user;

the calibration main control circuit is further connected to the second switch circuit, and is specifically configured to send the frequency compensation value to the write device when receiving a write notification from the second switch circuit.

13. The system of claim 1, wherein the writing means further comprises a receiving circuit and a second notification circuit;

the receiving circuit is connected with the write-in main control circuit and used for receiving response information from the tested product and sending the received response information to the write-in main control circuit;

the writing master control circuit is also connected with the receiving circuit and the second notification circuit, and is used for controlling the second notification circuit to notify a user of completing writing when receiving the response information from the receiving circuit;

and the second notification circuit is connected with the writing main control circuit and used for notifying a user of completing writing under the control of the writing main control circuit.

14. The system of claim 1, wherein the writing means comprises a second sensing circuit, a receiving circuit, and a second notification circuit;

the calibration main control circuit is specifically connected with the second sensing circuit and specifically used for sending the frequency compensation value to the second sensing circuit;

the second sensing circuit is connected with the calibration main control circuit and used for receiving the frequency compensation value from the calibration main control circuit and writing the frequency compensation value into the tested product;

the receiving circuit is connected with the calibration main control circuit and used for receiving response information from the tested product and sending the received response information to the calibration main control circuit;

the calibration main control circuit is also connected with the receiving circuit and the second notification circuit and is used for controlling the second notification circuit to inform a user of completing writing when response information from the receiving circuit is received;

and the second notification circuit is connected with the calibration main control circuit and used for notifying a user of completing writing under the control of the calibration main control circuit.

15. The system of claim 1, further comprising a first master control device, a second master control device, a first splitter device comprising at least one input address port and one output port, a second splitter device comprising at least one output address port and one input port, a switch device comprising a second switch circuit; the calibration device further comprises a first notification circuit; the input address port in the first branch device and the output address port in the second branch device have a corresponding relation, and the calibration device and the writing device which are connected with the input address port and the output address port having the corresponding relation correspond to the same tested product;

the calibration main control circuit is further connected to an input address port of the first shunting device, and is specifically configured to send the frequency compensation value to the first shunting device;

each input address port of the first shunt device is connected with one calibration main control circuit, is connected with the first main control device through an output port, and is used for receiving the frequency compensation value from the calibration main control circuit, sending the received frequency compensation value to the first main control device, and sending a notification of completing reception to the corresponding calibration main control circuit when receiving the notification of completing reception from the first main control device;

the calibration main control circuit is further connected to the first notification circuit, and is further configured to control the first notification circuit to notify a user that writing is possible when receiving a notification of completion of reception from the first splitter device;

the first notification circuit is connected with the calibration main control circuit and used for notifying a user that writing can be performed under the control of the calibration main control circuit;

the second switch circuit is connected with the first main control device and used for sending the writing notification to the first main control device when receiving the writing notification from a user;

the first master control device is connected to the second switch circuit, the output port of the first shunt device, and the second master control device, and is configured to receive the frequency compensation value from the first shunt device, store the received frequency compensation value, and send a notification of completion of reception to the first shunt device; the frequency compensation circuit is used for sending the stored frequency compensation value to the second main control device when receiving a write-in notice from the second switch circuit;

the second master control device is connected with the input ports of the first master control device and the second branch device, and is used for receiving the frequency compensation value from the first master control device and sending the received frequency compensation value to the second branch device;

the second branch device is connected with the second main control device through an input port of the second branch device, and each output address port is connected with one writing device and used for receiving the frequency compensation value from the second main control device and sending the received frequency compensation value to the corresponding writing device;

and the writing device is connected with one output address port in the second shunt device and is used for receiving the frequency compensation value from the second shunt device and writing the received frequency compensation value into a corresponding tested product.

16. The system of claim 1, further comprising a first master control device, a second master control device, a first splitter device comprising at least one input address port and one output port, a second splitter device comprising at least one output address port and one input port, a switch device comprising a second switch circuit; the calibration device further comprises a first notification circuit; the input address port in the first branch device and the output address port in the second branch device have a corresponding relation, and the calibration device and the writing device which are connected with the input address port and the output address port having the corresponding relation correspond to the same tested product;

each input address port of the first shunting device is connected with one calibration main control circuit, is connected with the first main control device through the output port, and is used for receiving the frequency compensation value from the calibration main control circuit, sending the received frequency compensation value to the first main control device, and sending a notification of completing reception to the corresponding calibration main control circuit when receiving the notification of completing reception from the first main control device;

the first master control device is connected with an output port of the first shunt device, and is configured to receive the frequency compensation value from the first shunt device, store the received frequency compensation value, and send a notification of completing reception to the first shunt device;

the second switch circuit is connected with the second main control device and used for sending a write-in notification to the second main control device when receiving the write-in notification from a user;

the second master control device is connected with the second switch circuit, the first master control device and the input port of the second shunt device, and is configured to send a write notification to the first master control device when receiving the write notification from the second switch circuit; the frequency compensation device is used for receiving the frequency compensation value from the first main control device and sending the received frequency compensation value to the second branch device;

the first main control device is also connected with the second main control device and is used for sending the stored frequency compensation value to the second main control device when receiving a write-in notification from the second main control device;

17. The system of claim 1, further comprising a third master device, a first splitter device including at least one input address port and one output port, a second splitter device including at least one output address port and one input port, a switch device including a second switch circuit; the calibration device further comprises a first notification circuit; the input address port in the first branch device and the output address port in the second branch device have a corresponding relation, and the calibration device and the writing device which are connected with the input address port and the output address port having the corresponding relation correspond to the same tested product;

each input address port of the first branch device is connected with one calibration main control circuit, is connected with the third main control device through an output port, and is used for receiving the frequency compensation value from the calibration main control circuit, sending the received frequency compensation value to the third main control device, and sending a notification of completing reception to the corresponding calibration main control circuit when receiving the notification of completing reception from the third main control device;

the second switch circuit is connected with the third main control device and used for sending the writing notification to the third main control device when receiving the writing notification from a user;

the third master control device is connected with the second switch circuit, the output port of the first shunt device and the input port of the second shunt device, and is configured to receive the frequency compensation value from the first shunt device and store the received frequency compensation value; the second shunt device is used for sending the stored frequency compensation value to the second shunt device when receiving the write-in notice from the second switch circuit;

the second branch device is connected with the third main control device through an input port of the second branch device, and each output address port is connected with one writing device and used for receiving the frequency compensation value from the third main control device and sending the received frequency compensation value to the corresponding writing device;

18. The system of claim 1, further comprising a fourth master, a first splitter comprising at least one input address port and one output port, a second splitter comprising at least one output address port and one input port; the input address port in the first branch device and the output address port in the second branch device have a corresponding relation, and the calibration device and the writing device which are connected with the input address port and the output address port having the corresponding relation correspond to the same tested product;

each input address port of the first shunting device is connected with one calibration main control circuit, is connected with the fourth main control device through an output port, and is used for receiving the frequency compensation value from the calibration main control circuit and sending the received frequency compensation value to the fourth main control device;

the fourth master control device is connected to the output port of the first splitter device and the input port of the second splitter device, and configured to send the received frequency compensation value to the second splitter device when receiving the frequency compensation value from the first splitter device;

the second branch device is connected with the fourth master control device through an input port of the second branch device, and each output address port is connected with one writing device and used for receiving the frequency compensation value from the fourth master control device and sending the received frequency compensation value to the corresponding writing device;