CN108122731A - 用于电子组件的图案结构及其制造方法 - Google Patents
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- 238000000059 patterning Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000011469 building brick Substances 0.000 title claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 106
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 15
- 239000011810 insulating material Substances 0.000 claims description 12
- 238000007641 inkjet printing Methods 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 description 7
- 239000007788 liquid Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明涉及一种用于电子组件的图案结构及其制造方法。图案结构包括图案层、阻挡结构、悬臂结构以及连接结构。图案层配置于基底上。阻挡结构配置于图案层的一侧的基底上,其中阻挡结构的厚度小于图案层的厚度。悬臂结构连接于图案层与阻挡结构之间。连接结构连接于图案层与其一侧的基底之间,且位于悬臂结构与阻挡结构上。本技术方案具有较佳的阶梯覆盖性。
Description
技术领域
本发明涉及一种图案结构,且尤其涉及一种具有大的阶梯高度的用于电子组件的图案结构及其制造方法。
背景技术
利用打印制程来形成电子组件具有许多优点,包括制程简单且快速。具体而言,可通过对准、打印以及固化的简单步骤将墨水印刷成任意图案,而可避免进行微影制程所需的繁琐步骤。此外,打印制程所使用的设备少、材料使用率高且制程周期短,故可降低电子组件的制造成本。
特别来说,打印制程包括喷墨打印(inkjet printing)。在喷墨打印中,若阶梯高度(step height)过大(例如是大于200nm),则可能造成后续所形成的膜层在阶梯的侧壁处发生不连续的问题。
发明内容
本发明提供一种图案结构,具有较佳的阶梯覆盖性(step coverage)。
本发明提供一种图案结构的制造方法,可避免膜层在阶梯的侧壁上发生不连续的问题。
在本发明的一实施例中,图案结构用于电子组件。图案结构包括图案层、阻挡结构、悬臂结构以及连接结构。图案层配置于基底上。阻挡结构配置于图案层的一侧的基底上,其中阻挡结构的厚度小于图案层的厚度。悬臂结构连接于图案层与阻挡结构之间。连接结构连接于图案层与其一侧的基底之间,且位于悬臂结构与阻挡结构上。
在本发明的一实施例中,上述的图案结构中,图案层的厚度可大于200nm。
在本发明的一实施例中,上述的图案结构中,阻挡结构的厚度与图案层的厚度的比例范围可在1:2至3:20之间。
在本发明的一实施例中,上述的图案结构中,阻挡结构与图案层之间的间距与图案层的厚度的比例范围可在3:5至7:4之间。
在本发明的一实施例中,上述的图案结构中,阻挡结构可环绕图案层。
在本发明的一实施例中,上述的图案结构中,悬臂结构的顶面可为斜面,其较高的一侧连接于图案层而其较低的一侧连接于阻挡结构。
在本发明的一实施例中,上述的图案结构中,悬臂结构的材料可不同于挡结构的材料。
在本发明的一实施例中,上述的图案结构中,连接结构的材料可包括导体材料以及绝缘材料。
在本发明的一实施例中,图案结构用于电子组件。图案结构包括图案层、阻挡结构、悬臂结构以及连接结构。图案层配置于基底上。阻挡结构配置于图案层的一侧的基底上,其中阻挡结构的厚度小于图案层的厚度。悬臂结构连接于图案层与阻挡结构之间。连接结构配置于图案层、悬臂结构以及阻挡结构上,其中阻挡结构的材料与连接结构的材料均包括导体材料。
本发明的图案结构的制造方法用于电子组件。图案结构的制造方法包括下列步骤。于基底上形成图案层。形成阻挡结构,其经形成于图案层的一侧的基底上,其中阻挡结构的厚度小于图案层的厚度。形成悬臂结构,其经形成以连接于图案层与阻挡结构之间。形成连接结构,其经形成以连接于图案层与其一侧的基底之间,且经形成于悬臂结构与阻挡结构上。
在本发明的一实施例中,上述的图案结构的制造方法中,形成阻挡结构、悬臂结构以及连接结构的方法可包括喷墨打印。
基于上述,通过在图案层的一侧设置阻挡结构与悬臂结构,可降低图案层与其一侧的基底之间的坡度,或可降低图案层一侧的高度差。因此,在形成连接于图案层与其一侧的基底之间的连接结构时,可避免连接结构在图案层的侧壁上发生不连续的现象,进而可提高连接结构的阶梯覆盖性。另外,可通过调整阻挡结构的厚度、悬臂结构的厚度以及阻挡结构与图案层的间距,而可简单地调整悬臂结构的尺寸。换言之,可简单地调整上述的坡度或高度差。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1A至图1C是依照本发明一实施例的图案结构的制造流程的剖面示意图。
图2是依照本发明一实施例的图案结构的剖面示意图。
图3是依照本发明一实施例的图案结构的剖面示意图。
具体实施方式
图1A至图1C是依照本发明一实施例的图案结构的制造流程的剖面示意图。
请参照图1A,本实施例的图案结构的制造方法用于电子组件,其包括下列步骤。首先,于基底100上形成图案层102。在一实施例中,基底100可包括半导体基底、玻璃基底或软性基底。图案层102可为任意材料所构成的薄膜,且图案层102也可为半导体组件或晶粒(die)。本发明并不以基底100与图案层102的种类为限。图案层102的厚度h1可大于200nm。若以喷墨打印的方式直接在此图案层102上形成膜层(layer),则可能因图案层102与其一侧的基底100之间的高度差(step height)过大,而造成此膜层在图案层102的侧壁上发生不连续的问题。举例而言,上述的膜层可为连接于图案层102与其一侧的基底100之间的连接结构。
接着,于图案层102的一侧的基底100上形成阻挡结构104。在本实施例中,阻挡结构104的材料可为绝缘材料。举例而言,绝缘材料可包括如环氧树脂(epoxy)的高分子材料、氧化物或氮氧化物。在其他实施例中,阻挡结构104的材料也可为导体材料。举例而言,导体材料可包括金属材料或金属氮化物。在一实施例中,形成阻挡结构104的方法可包括点胶(dispensing)制程或喷墨打印(inkjet printing)制程。首先,将包含阻挡结构104的材料的墨液形成于图案层102的一侧的基底100上。接着,进行固化制程以去除墨液中的溶剂,而形成阻挡结构104。阻挡结构104经形成以使其厚度h2小于图案层102的厚度h1。在一实施例中,阻挡结构104的厚度h2与图案层102的厚度h1的比例范围可在1:2至3:20之间。阻挡结构104与图案层102之间的间距d1与图案层102的厚度h1的比例范围可在3:5至7:4之间。在一实施例中,用以形成阻挡结构104的墨液的黏滞系数可大于1mPa·s,也就是大于水的黏滞系数。据此,可利于控制阻挡结构104的厚度h2,以及利于控制阻挡结构104与图案层102之间的间距d1。
在其他实施例中,形成阻挡结构104的方法也可为其他适合的涂布制程,且阻挡结构104的剖面形状不限于如图1A所示的半球状。在一实施例中,阻挡结构104可经形成以环绕图案层102,而形成封闭的图案。在其他实施例中,阻挡结构104可部分地环绕图案层102。
请参照图1B,接着,形成悬臂结构106。悬臂结构106经形成以连接于图案层102与阻挡结构104之间。在一实施例中,形成悬臂结构106的方法可包括喷墨打印制程,其包括在基底100上形成墨液以及进行固化制程的步骤。通过设置阻挡结构104,可使得用以形成悬臂结构106的墨液的扩散范围被局限在阻挡结构104与图案层102之间。据此,可通过调整阻挡结构104的厚度h2以及阻挡结构104与图案层102的间距d1,而可简单地调整悬臂结构106的尺寸。另外,由于可局限用以形成悬臂结构106的墨液的扩散范围,故可选用黏滞系数较低的墨水,以使其可快速地在阻挡结构104与图案层102之间扩散,而经固化后形成悬臂结构106。因此,可提高形成悬臂结构106的速度。在一实施例中,用以形成悬臂结构106的墨水的黏滞系数可小于用以形成阻挡结构104的墨水的黏滞系数。举例而言,用以形成悬臂结构106的墨水的黏滞系数可小于1mPa·s。
在一实施例中,悬臂结构106的顶面可为斜面,其较高的一侧连接于图案层102,而其较低的一侧连接于阻挡结构104。特别来说,此斜面可连接于图案层102的侧壁的顶部与阻挡结构104的顶部之间。因此,可降低图案层102的一侧与基底100之间的坡度。另外,可通过调整阻挡结构104的厚度h2、图案层102的厚度h1以及阻挡结构104与图案层102之间的间距d1,以简单地改变上述坡度。举例而言,可通过调整用以形成阻挡结构104的墨水的黏滞系数,而可调整阻挡结构104的厚度。更具体地说,用以形成阻挡结构104的墨水的黏滞系数愈高,则此墨水愈不易往四周扩散,故愈容易形成厚度较大的阻挡结构104。
在其他实施例中,悬臂结构106的顶面可为平面、斜面、曲面或其组合,且悬臂结构106经形成以使图案层102与悬臂结构106的顶面之间的高度差小于200nm,据此,可降低图案层102一侧的高度差。另外,可调整阻挡结构104与悬臂结构106的厚度,以简单地改变图案层102与悬臂结构106的顶面的高度差。
在一实施例中,悬臂结构106的材料可不同于阻挡结构104的材料。举例而言,悬臂结构106的材料可为绝缘材料,而阻挡结构104的材料可为导体材料。反之,悬臂结构106的材料可为导体材料,而阻挡结构104的材料可为绝缘材料。在其他实施例中,悬臂结构106与阻挡结构104的材料可同时为绝缘材料或导体材料。
请参考图1C,接着形成连接结构108,而完成图案结构110的制造。连接结构108经形成以连接于图案层102与其一侧的基底100之间,且位于悬臂结构106与阻挡结构104上或覆盖悬臂结构106与阻挡结构104。形成连接结构108的方法可包括喷墨打印制程。连接结构108的材料可包括导体材料或绝缘材料。在本实施例中,连接结构108的材料可与阻挡结构104的材料相异。举例而言,连接结构108的材料可为导体材料,而阻挡结构104的材料可为绝缘材料。另外,在一实施例中,连接结构108的材料可与悬臂结构106可同时为绝缘材料或导体材料,故可在同一步骤中形成悬臂结构106与连接结构108,而可进一步地简化制程。
通过设置阻挡结构104与悬臂结构106,可降低图案层102的一侧与基底100之间的坡度,或使得图案层102与悬臂结构106的顶面之间的高度差小于200nm。因此,在形成连接结构108时,可避免连接结构108在图案层102的侧壁上发生不连续的现象,进而提高连接结构108的阶梯覆盖性。另外,通过调整阻挡结构104的厚度h2、图案层102的厚度h1以及间距d1,可改变悬臂结构106的顶面的坡度或图案层102与悬臂结构106的顶面的高度差。因此,可间接地调整位于悬臂结构106与阻挡结构104上的连接结构108的长度,故可简单地调整连接结构108的电阻以及图案结构110整体的面积。
以下,将以图1C说明本发明的图案结构110。图案结构110包括图案层102、阻挡结构104、悬臂结构106以及连接结构108。图案层102配置于基底100上。阻挡结构104配置于图案层102的一侧的基底100上,其中阻挡结构104的厚度h2小于图案层102的厚度h1。悬臂结构106连接于图案层102与阻挡结构104之间。连接结构108连接于图案层102与其一侧的基底100之间,且位于悬臂结构106与阻挡结构104上或覆盖悬臂结构106与阻挡结构104。图案层102的厚度h1可大于200nm。阻挡结构104的厚度h2与图案层102的厚度h1的比例范围可在1:2至3:20之间。阻挡结构104与图案层102之间的间距d1与图案层102的厚度h1的比例范围可在3:5至7:4之间。阻挡结构104可环绕图案层102。悬臂结构106的顶面可为斜面,其较高的一侧连接于图案层102而其较低的一侧连接于阻挡结构104。阻挡结构104的材料、悬臂结构106的材料以及连接结构108的材料可分别包括导体材料或绝缘材料。在本实施例中,阻挡结构104的材料可不同于连接结构108的材料。举例而言,阻挡结构104的材料可为绝缘材料,而连接结构108的材料可为导体材料。另外,悬臂结构106的材料可不同于阻挡结构104的材料。举例而言,悬臂结构106的材料与阻挡结构104的材料可为彼此相异的绝缘材料。
图2是依照本发明一实施例的图案结构的剖面示意图。图2的图案结构220与图1C的图案结构110类似,差异处将详细说明如下,相同处则不再赘述。
请参照图2,图案结构220的阻挡结构204配置于图案层102、悬臂结构106与阻挡结构204上。阻挡结构204的材料与连接结构208的材料均包括导体材料。在一实施例中,连接结构208可为电子组件的内联机(interconnection)。由于连接结构208可通过阻挡结构204与基底100电性连接,故连接结构208不需跨越阻挡结构204以与基底100接触。因此,可加强连接结构208的机械强度,进而提高电子组件的可靠度。
图3是依照本发明一实施例的图案结构的剖面示意图。图3的图案结构330与图1C的图案结构110类似,差异处将详细说明如下,相同处则不再赘述。
请参照图3,图案结构330可为双层结构。具体而言,图案结构330还包括图案层302、阻挡结构304以及悬臂结构306,其配置于图案层102上。另外,连接结构308可经形成以连接图案层302、图案层102与基底100。连接结构308位于悬臂结构306、阻挡结构304、悬臂结构106以及阻挡结构104上,或可覆盖悬臂结构306、阻挡结构304、悬臂结构106以及阻挡结构104。在一实施例中,连接结构308可覆盖悬臂结构306、阻挡结构304、图案层102以及基底100。此外,在其他实施例中,图案结构还可为三层结构、四层结构等等,本发明并不以图案结构的层数为限。
综上所述,通过在图案层的一侧设置阻挡结构与悬臂结构,可降低图案层与其一侧的基底之间的坡度,或可降低图案层一侧的高度差。因此,在图案层上形成连接结构时,可避免连接结构在图案层的侧壁上发生不连续的现象,进而可提高连接结构的阶梯覆盖性。另外,可通过调整阻挡结构的厚度、悬臂结构的厚度以及阻挡结构与图案层的间距,而可简单地调整悬臂结构的尺寸。换言之,可简单地调整上述坡度或高度差。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (11)
1.一种图案结构,用于电子组件,其特征在于,所述图案结构包括:
图案层,配置于基底上;
阻挡结构,配置于所述图案层的一侧的所述基底上,其中所述阻挡结构的厚度小于所述图案层的厚度;
悬臂结构,连接于所述图案层与所述阻挡结构之间;以及
连接结构,连接于所述图案层与其一侧的所述基底之间,且位于所述悬臂结构与所述阻挡结构上。
2.根据权利要求1所述的图案结构,其特征在于,所述图案层的厚度大于200nm。
3.根据权利要求1所述的图案结构,其特征在于,所述阻挡结构的厚度与所述图案层的厚度的比例范围在1:2至3:20之间。
4.根据权利要求1所述的图案结构,其特征在于,所述阻挡结构与所述图案层之间的间距与所述图案层的厚度的比例范围在3:5至7:4之间。
5.根据权利要求1所述的图案结构,其特征在于,所述阻挡结构环绕所述图案层。
6.根据权利要求1所述的图案结构,其特征在于,所述悬臂结构的顶面为斜面,其较高的一侧连接于所述图案层而其较低的一侧连接于所述阻挡结构。
7.根据权利要求1所述的图案结构,其特征在于,所述悬臂结构的材料不同于所述阻挡结构的材料。
8.根据权利要求1所述的图案结构,其特征在于,所述连接结构的材料包括导体材料以及绝缘材料。
9.一种图案结构,用于电子组件,其特征在于,所述图案结构包括:
图案层,配置于基底上;
阻挡结构,配置于所述图案层的一侧的所述基底上,其中所述阻挡结构的厚度小于所述图案层的厚度;
悬臂结构,连接于所述图案层与所述阻挡结构之间;以及
连接结构,配置于所述图案层、所述悬臂结构与所述阻挡结构上,其中所述阻挡结构的材料与所述连接结构的材料均包括导体材料。
10.一种图案结构的制造方法,用于电子组件,其特征在于,所述图案结构的制造方法包括:
于基底上形成图案层;
形成阻挡结构,所述阻挡结构经形成于所述图案层的一侧的所述基底上,其中所述阻挡结构的厚度小于所述图案层的厚度;
形成悬臂结构,所述悬臂结构经形成以连接于所述图案层与所述阻挡结构之间;以及
形成连接结构,所述连接结构经形成以连接于所述图案层与其一侧的所述基底之间,且经形成于所述悬臂结构与所述阻挡结构上。
11.根据权利要求10所述的图案结构的制造方法,其特征在于,形成所述阻挡结构、所述悬臂结构以及所述连接结构的方法包括喷墨打印。
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