CN108121412A - Backboard equipment, signal interconnection method and device - Google Patents
Backboard equipment, signal interconnection method and device Download PDFInfo
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- CN108121412A CN108121412A CN201611088931.7A CN201611088931A CN108121412A CN 108121412 A CN108121412 A CN 108121412A CN 201611088931 A CN201611088931 A CN 201611088931A CN 108121412 A CN108121412 A CN 108121412A
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- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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Abstract
The present invention provides a kind of backboard equipment, signal interconnection method and device, wherein, backboard equipment, including：Backboard；Board is inserted in the card slot of the backboard；Back panel connector is connected between the backboard and the board, for the signal interconnection between the backboard and the board；Signal conversion unit, it is connected between the connector and the board after the parallel signal from the board is converted to serial signal, the backboard is sent to by the connector or is sent to the board after the serial signal from the backboard is converted to corresponding parallel signal.It by the present invention, solves the problems, such as that the interface unit in correlation technique between board and backboard is excessive and influences backboard heat dissipation, while realizes the dynamic modification to system configuration.
Description
Technical field
The present invention relates to field of computer technology, in particular to a kind of backboard equipment, signal interconnection method and dress
It puts.
Background technology
In multipath server back board system design in the related art, there are following several structure types：Fig. 1 is the present invention
Single side plate back board structure schematic diagram in correlation technique, as shown in Figure 1, single side plate back board structure；Fig. 2 is of the invention related
It is two-sided to putting back board structure schematic diagram in slotting plate in technology, as shown in Fig. 2, two-sided put back board structure to inserting in plate；Fig. 3
It is to put back board structure schematic diagram in the two-sided orthogonal plate in correlation technique of the present invention, as shown in figure 3, being put in two-sided orthogonal plate
Back board structure.Existing rack server mainly using cross ventilation heat-removal modalities, regardless of structure type, is required for carrying on the back
Perforate ventilation and heat on plate.
In multipath server design in correlation technique, generally it is made of backboard and board.Board includes processor plate, IO
Plate, control panel, management board etc..May there are 1 or 2 or 4 processors on processor plate.There is PCIE (bus and to connect in I O board
Mouthful) equipment and other I/O devices.Control panel has the units such as common clock.There are PCH (Platform Controller on management board
Hub, platform courses bridge joint) chip, BMC (Baseboard Management Controller, baseboard management controller) core
Piece.Backboard is the critical component for realizing each board signal interconnection.Polylith processor plate, polylith I O board, 1 piece of control panel and 2 pieces
Management board is inserted in channeling server on backboard simultaneously.Between these boards, substantial amounts of signal needs to carry out by backboard
Interconnection.
Chip (or other circuits) needs on usual board and the signal of other boards interconnection is all directly to board
On back panel connector, in order to be interconnected by backboard.Specifically, Fig. 4 is the board backplane signal in correlation technique of the present invention
Schematic diagram is realized in interconnection, as shown in figure 4, having several main chips and other circuits on board 1', also has back panel connector 3'.Core
Piece (or other circuits) needs several signal wire 2' with the interconnection of other boards to be directly connected on the back panel connector 3' of board.
The flow direction of these signals can be from chip (or other circuits) to back panel connector, can be from back panel connector to chip
(or other circuits) or in chip (or other circuits) two-way flow between back panel connector.
These need the signal of upper backboard to use substantial amounts of back panel connector, bring cost increase.Backboard connection simultaneously
Device and substantial amounts of backplane signal line need to occupy backboard PCB (printed circuit board) area, reduce available for perforate heat dissipation
Area influences heat dissipation performance.
Multiple processors are needed by specific Topology connection in multipath server, some configurations of each processor in topological
Pin has different configurations, such as SOCKET_ID (processor sequence number mark), LEGACY_SKT (processor 0 configures signal).
Such signal is sent to backboard on general processor plate, the such signal of the processor plate of different slots position does different upper on backboard
Drop-down helps processor to be configured.This implementation method brings the configuration of slot position not change flexibly.
For the above problem present in correlation technique, at present it is not yet found that the solution of effect.
The content of the invention
An embodiment of the present invention provides a kind of backboard equipment, signal interconnection method and device, at least to solve correlation technique
Interface unit between middle board and backboard is excessive and influences the problem of backboard radiates.
According to one embodiment of present invention, a kind of backboard equipment is provided, including：Backboard；Board is inserted in the backboard
Card slot in；Back panel connector is connected between the backboard and the board, between the backboard and the board
Signal interconnects；Signal conversion unit is connected between the connector and the board for will be from the parallel of the board
After signal is converted to serial signal, the backboard is sent to or by the serial signal from the backboard by the connector
The board is sent to after being converted to corresponding parallel signal.
Optionally, the signal conversion unit includes：Configuration register is supplied to baseboard management controller BMC to described
Processor on processor plate carries out system configuration.
Optionally, the signal conversion unit is complex programmable logic device (CPLD) chip.
Optionally, the board includes：Processor plate, input and output I O board, control panel, management board.
Optionally, the back panel connector further includes：Two null modem cables, are connected to the signal conversion unit and institute
Between stating board, transmission uplink signal and downlink signal are respectively used to.
According to another embodiment of the invention, a kind of signal interconnection method is provided, is applied in multipath server backboard
On, including：First parallel signal of the first board is converted into the first serial signal；By first serial signal via backboard
Connector is sent to the second board.
Optionally, the method further includes：Receive the second string that second board is sent via the back panel connector
Row signal；Decode second serial signal obtain the second parallel signal and on give first board.
Optionally, the first parallel signal of the first board is converted to the first serial signal includes：From first board
Obtain the first parallel signal in board；First parallel signal is serialized by preset order；To first after serialization
Parallel signal calculates cyclic redundancy check (CRC) check code, and the cyclic redundancy check is attached to the first parallel letter after serialization
Overall data is obtained after number；Affix synchronizing frame head obtains first serial signal before the frame of the overall data.
Optionally, decoding second serial signal, which obtains the second parallel signal, includes：Detect second serial signal
Synchronizing frame head；Receive the serial data in second serial signal；To serial data calculating cyclic redundancy check, and with
The additional cyclic redundancy check of data frame is compared；When cyclic redundancy check verification is correct, serial data frame is decoded
To obtain second parallel signal.
Optionally, first parallel signal includes：It is acquired from the chip and/or circuit pin of first board
Parallel signal and/or, the content of registers obtained out of first board transmission configuration register.
Optionally, second parallel signal includes：It is sent to the chip pin and/or circuitron of first board
The signal of foot and/or, configure signal, wherein, it is described configuration signal be used for configuration processor configuration pin.
Optionally, first board and second board are arranged on same backboard.
According to still another embodiment of the invention, a kind of signal interconnect device is provided, is applied in multipath server backboard
On, including：First modular converter, for the first parallel signal of the first board to be converted to the first serial signal；First sends
Module, for first serial signal to be sent to the second board via back panel connector.
Optionally, described device further includes：Second modular converter connects for receiving second board via the backboard
Connect the second serial signal of device transmission；Second sending module obtains the second parallel signal for decoding second serial signal
First board is given on and.
Optionally, first parallel signal includes：It is acquired from the chip and/or circuit pin of first board
Parallel signal and/or, the content of registers obtained out of first board transmission configuration register.
Optionally, second parallel signal includes：It is sent to the chip pin and/or circuitron of first board
The signal of foot and/or, configure signal, wherein, it is described configuration signal be used for configuration processor configuration pin.
By the present invention backboard equipment, including：Backboard；Board is inserted in the card slot of the backboard；Back panel connector,
It is connected between the backboard and the board, for the signal interconnection between the backboard and the board；Signal conversion is single
Member is connected between the connector and the board and is used to the parallel signal from the board being converted to serial signal
Afterwards, the backboard is sent to by the connector or the serial signal from the backboard is converted into corresponding parallel letter
The board is sent to after number, is converted to the multi-path parallel signal transmitted between board and backboard by signal conversion unit
Serial signal solves the problems, such as that the interface unit in correlation technique between board and backboard is excessive and influences backboard heat dissipation, subtracts
Lack board to the number of signals of backboard, reduction connector quantity reduces cost, while can also increase backboard ventilation perforated area,
Lifting system heat dissipation performance, while realize the dynamic modification to system configuration.
Description of the drawings
Attached drawing described herein is used for providing a further understanding of the present invention, forms the part of the application, this hair
Bright schematic description and description does not constitute improper limitations of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is the single side plate back board structure schematic diagram in correlation technique of the present invention；
Fig. 2 is two-sided to putting back board structure schematic diagram in slotting plate in correlation technique of the present invention；
Fig. 3 is to put back board structure schematic diagram in the two-sided orthogonal plate in correlation technique of the present invention；
Fig. 4 is that schematic diagram is realized in the board backplane signal interconnection in correlation technique of the present invention；
Fig. 5 is the structure chart of backboard equipment according to embodiments of the present invention；
Fig. 6 is the flow chart of signal interconnection method according to embodiments of the present invention；
Fig. 7 is the structure diagram of signal interconnect device according to embodiments of the present invention；
Fig. 8 is that schematic diagram is realized in a kind of board backplane signal interconnection of the embodiment of the present invention；
Fig. 9 is a kind of backboard serial signal frame format schematic diagram of the embodiment of the present invention；
Figure 10 is that schematic diagram is realized in a kind of backplane signal interconnection of specific embodiment of the embodiment of the present invention；
Figure 11 is 8 road server of one kind, the 8 tunnel configuration processor topology schematic diagram of the embodiment of the present invention；
Figure 12 is the double 4 tunnel configuration processor topology schematic diagrames of 8 road server of one kind of the embodiment of the present invention.
Specific embodiment
Come that the present invention will be described in detail below with reference to attached drawing and in conjunction with the embodiments.It should be noted that do not conflicting
In the case of, the feature in embodiment and embodiment in the application can be mutually combined.
It should be noted that term " first " in description and claims of this specification and above-mentioned attached drawing, "
Two " etc. be the object for distinguishing similar, without being used to describe specific order or precedence.
Embodiment 1
A kind of backboard equipment is provided in the present embodiment, and Fig. 5 is the structure of backboard equipment according to embodiments of the present invention
Figure, as shown in figure 5, including：Backboard 50；Board 52, is inserted in the card slot of backboard；Back panel connector 54, is connected to backboard and plate
Between card, for the signal interconnection between backboard and board；Signal conversion unit 56 is connected between connector and board and is used for
After parallel signal from board is converted to serial signal, backboard is sent to by connector or will be from the serial of backboard
Signal is sent to board after being converted to corresponding parallel signal.
Backboard equipment through this embodiment, signal conversion unit believe the multidiameter delay transmitted between board and backboard
Number serial signal is converted to, it is excessive and influence backboard heat dissipation to solve the interface unit in correlation technique between board and backboard
Problem reduces board to the number of signals of backboard, reduces connector quantity, reduce cost, while can also increase backboard ventilation and open
Hole area, lifting system heat dissipation performance, while realize the dynamic modification to system configuration.
Optionally, signal conversion unit includes：Configuration register, for carrying out system configuration to the processor on board.
Optionally, signal conversion unit is complex programmable logic device (CPLD) chip.
The board of the present embodiment includes：Processor plate, input and output I O board, control panel, management board.
Optionally, back panel connector further includes：Two null modem cables, are connected between signal conversion unit and board,
It is respectively used to transmission uplink signal and downlink signal.
A kind of signal interconnection method is provided in the present embodiment, and Fig. 6 is signal interconnection side according to embodiments of the present invention
The flow chart of method, as shown in fig. 6, including：
First parallel signal of the first board is converted to the first serial signal by S602；
First serial signal is sent to the second board by S604 via back panel connector.
Optionally, method further includes：
S11 receives the second serial signal that the second board is sent via back panel connector；
S12, decoding the second serial signal obtain the second parallel signal and on give the first board.
Optionally, the first parallel signal of the first board is converted to the first serial signal to specifically include：From the first board
Obtain the first parallel signal in board；First parallel signal is serialized by preset order；It is parallel to first after serialization
Signal calculates cyclic redundancy check (CRC) check code, and is obtained after the first parallel signal that cyclic redundancy check is attached to after serialization
To overall data；Affix synchronizing frame head obtains the first serial signal before the frame of overall data.
Optionally, the second serial signal of decoding obtains the second parallel signal and specifically includes：Detect the same of the second serial signal
Step-frame head；
Receive the serial data in the second serial signal；
Cyclic redundancy check is calculated to serial data, and is compared with the additional cyclic redundancy check of data frame；
When cyclic redundancy check verification is correct, serial data frame is decoded to obtain the second parallel signal.
Optionally, the first parallel signal includes：The parallel signal that is acquired from the pin of the first board and/or, from
The content of registers obtained in the transmission configuration register of one board.
Optionally, second parallel signal includes：The second parallel signal for being decoded from the second serial signal and/or,
The configuration signal decoded.It configures signal and is used for configuration processor configuration pin.Optionally, the first board and the second board are set
On same backboard.
Through the above description of the embodiments, those skilled in the art can be understood that according to above-mentioned implementation
Example method can be realized by Complex Programmable Logic Devices, naturally it is also possible to by other hardware, but in many cases before
Person is more preferably embodiment.
Embodiment 2
A kind of signal interconnect device is additionally provided in the present embodiment, which is used to implement above-described embodiment and preferred reality
Mode is applied, had carried out repeating no more for explanation.As used below, term " module " can realize answering for predetermined function
The combination of miscellaneous programmable logic device and/or special chip and circuit.Although the described device of following embodiment preferably with
Complex Programmable Logic Devices is realized, but the realization of other special chips and/or circuit is also what may and be contemplated.
Fig. 7 is the structure diagram of signal interconnect device according to embodiments of the present invention, is applied on multipath server backboard,
As shown in fig. 7, the device includes：
First modular converter 70, for the first parallel signal of the first board to be converted to the first serial signal；
First sending module 72, for the first serial signal to be sent to the second board via back panel connector.
Optionally, device further includes：Second modular converter, for receive that the second board is sent via back panel connector the
Two serial signals；Second sending module, for decode the second serial signal obtain the second parallel signal and on give the first board.
Optionally, the first parallel signal includes：The parallel signal that is acquired from the pin of the first board and/or, from
The content of registers obtained in the transmission configuration register of one board.
Optionally, second parallel signal includes：It is sent to the chip pin and/or circuitron of first board
The signal of foot and/or, configure signal, wherein, it is described configuration signal be used for configuration processor configuration pin, second send mould
The configuration register content that block decodes is used for the specific configuration pin signal of configuration processor, to realize the dynamic of system configuration
State configures.
It should be noted that above-mentioned modules can be realized by digital circuit, but not limited to this：Complexity can
Programmed logic device；Alternatively, other special chips and circuit.
Embodiment 3
A kind of backplane signal interconnected method of multipath server is present embodiments provided, reduces board to the signal number of backboard
Amount reduces connector usage amount, reduces cost.Connector can be also reduced simultaneously to accumulate with the backboard PCB surface that signal lead occupies, it can
For increasing perforate of divulging information, heat radiation performance.The flexible configuration of realization system.
The technical solution of embodiment is as follows：
Chip (or other circuits) adds in a signal serioparallel exchange transmission-receiving function between back panel connector on board
Originally the signal of a large amount of parallel interconnection to back panel connectors is transformed to the few serial signal of quantity, serves backboard biography by unit
It is defeated.
There are piece of CPLD (Complex Programmable Logic Device complicated programmable logic devices on board
Part) chip, can realize signal serioparallel exchange transmitting-receiving function, while CPLD inside realize configuration register, be supplied to BMC into
Row system configuration.Realize serioparallel exchange transmission-receiving function component be not limited in CPLD, can also be other special chips or
Circuit.
The backplane signal interconnected method of the multipath server of the present embodiment is described as follows：
Chip (or other circuits) requires connect to the signal of backboard on board, is all connected to piece of CPLD chip.This
A little signals and configuration register complete conversion of the parallel signal to serial signal in CPLD chip internals.CPLD chips go out to send
Transformed serial signal is sent to another piece of board to be interconnected by signal to the back panel connector of board.CPLD chips go out
Signal is received to back panel connector, the serial signal that other boards bring is received from backboard.Serial letter is completed inside CPLD
Number decoding, be converted to corresponding parallel signal, be then sent through the corresponding signal pin of chip on board (or other circuits).It is carrying on the back
On plate, only need to be connected with 2 serial signal lines between the board that two scripts are interconnected using parallel signal.
By the embodiment of the present invention, original CPLD on board in shared multipath server, on the increased basis of cost free
On, board is reduced to the number of signals of backboard, is reduced connector quantity, is reduced cost, support the flexible configuration of system.Simultaneously also
Backboard ventilation perforated area, lifting system heat dissipation performance can be increased.
It is described in detail below in conjunction with the accompanying drawings：
Fig. 8 is that schematic diagram, multichannel clothes provided by the invention are realized in a kind of board backplane signal interconnection of the embodiment of the present invention
A kind of board backplane signal interconnection of business device backplane signal interconnected method realizes that hardware is formed as shown in figure 8, being wrapped on board 11'
It includes：Multiple main chips, other circuits, back panel connector 13', CPLD chip 14', chip (or other circuits) are between CPLD
Interconnection parallel signal line 12', CPLD and back panel connector between interconnection serial signal line 15'.Wherein interconnect parallel signal
Line 12' can have transmission, reception, transmitting-receiving bidirectional type.Wherein serial signal line 15' can have a transmission, a piece-root grafting to receive.
It needs on the board of polylith other boards interconnection, multigroup serial signal line can be gone out, every group is connected to not respectively by backboard
Other same boards.
According to the parallel signal line 12' quantity that backboard is required connect on board, selection meets number of pin requirement
CPLD chips 14'.
Parallel signal line 12' is connected to CPLD chips.Serial signal line 15' is connected to board upper backboard from CPLD to connect
Connect device.
Inside CPLD, the parallel signal line 12' of input is converted, a hair is converted to from multiple parallel signals
Direction serial signal is sent, if there is configuration register, conversion together is incorporated into sending direction serial signal.Transformed serial signal
It is exported from CPLD, upper backboard is transmitted by the interconnection serial signal line 15' between CPLD and back panel connector.
Meanwhile serially signal passes through serial signal line 15' quilts to the recipient sent on backboard from other boards
CPLD is received.The serial signal received is decoded inside CPLD, and reduction becomes one-to-one with parallel signal line 12'
Parallel signal if there is configuration register, is decoded as configuring signal (being included in parallel signal line 12') accordingly together, then
It is sent through CPLD to corresponding chip (or other circuits).
The board of opposite end completes above-mentioned same transmitting-receiving process, you can realizes the backplane signal interconnection of two boards card.
A kind of following flow of serioparallel exchange transmission-receiving function implementation method inside the CPLD of the present embodiment：
Sending direction：
CPLD obtains parallel signal in board from the pin being connected with parallel signal line 12', if there is sending configuration deposit
Content of registers is merged into parallel signal by device.Parallel signal is serialized in order.The data after serialization are calculated again
CRC (Cyclic Redundancy Check, cyclic redundancy check) check code, is attached to after serial data.Again in serial number
According to front affix synchronizing frame head, a complete serial data frame is formed.Fig. 9 is that a kind of backboard of the embodiment of the present invention is serial
Signal frame form schematic diagram, data frame format are as shown in Figure 9.
The data frame built is sent to the transceiver module in CPLD.Transceiver module uses a state machine, and control was received and dispatched
Journey is sent to after receiving sending direction data frame on serial signal line 15'.Transmission process Xun Huan carries out.
Receive direction：
CPLD is serially sent into transceiver module from recipient after signal wire 15' receives serial signal.Inside transceiver module
Start to receive serial data after detecting synchronizing frame head, transceiver module calculates CRC to the serial data received after harvesting data
Check code, and be compared with the additional cyclic redundancy check of data frame, it is ensured that the serial data received is complete and correct.
Such as CRC check mistake, then wrong frame count accordingly increases, and the mistake frame is not resumed and sent backward.Such as CRC check just
Really, then serial data frame is sent to decoder module.
Decoder module is decoded serial data frame, is reduced to the parallel signal of permanent order.If there is configuration
Register data is reduced to configuration signal.Parallel signal and the configuration every bit of signal (if there is) are sent to corresponding parallel again
Signal wire 12'.
Figure 10 is that schematic diagram is realized in a kind of backplane signal interconnection of specific embodiment of the embodiment of the present invention, such as Figure 10 institutes
Show, which includes one piece of processor plate 11', one piece of backboard 21' and one piece of management board 31'.
Include on processor plate 11'：Two processors (CPU), other circuits, back panel connector 13', CPLD chip 14',
Interconnection parallel signal line 12'(of the cpu chip (or other circuits) between CPLD includes configuration signal), CPLD and backboard be connected
Reception configuration register 16'(inside interconnection serial signal line 15', CLPD between device is connected to the configuration pin of CPU).
Include on backboard 21'：Processor plate slot position connector 23', management board slot position connector 24', backboard interconnection are serial
Signal wire 22'.Also other slot position connectors omit in figure.
Include on management board 31'：PCH chips, BMC chip, other circuits, back panel connector 33', CPLD chip 34',
PCH chips (or other circuits) are connected everywhere between interconnection parallel signal line 32', CPLD and back panel connector between CPLD
The serial signal line 36' of device plate 11' is managed, the serial signal line of another piece of processor plate is connected between CPLD and back panel connector
Transmission configuration register 37' inside 35', CLPD.Management board needs to interconnect with polylith processing board, wherein parallel signal line 32'
In have a part of signal for being connected to processor plate 11', be also attached to the part signal of another piece of processor plate.
On processor plate 11', two processors and other circuits have substantial amounts of signal to require connect to management board.These
Sending direction signal is converted to serial signal after entering CPLD chips 14' in parallel signal line 12', is sent through serial signal line 15'
Toward management board 31'.By backboard serial signal line 22' and management board serial signal line 36', management board CPLD chips 34' is reached.
Serial signal, which is sent to after being decoded in CPLD chips 34' in parallel signal line 32', needs the reception being connected with processor plate 11'
Signal.
On management board 31', BMC, which writes configuration information, sends configuration register, and processing is connected in parallel signal line 32'
The transmission signal of device plate 11' enters after CPLD chips 34' be merged into the content for sending configuration register after be converted to serial signal,
Processor plate 11' is sent to through serial signal line 36'.By backboard serial signal line 22' and processor plate serial signal line 15',
Reach the CPLD chips 14' of processing board 11'.Serial signal decoded back in CPLD chips 14' is parallel signal and with confidence
Send the reception signal and CPU configuration pins in parallel signal line 12' after number to.
Particularly, on management board 31', parallel signal line 32' is connected to the signal of another piece of processor plate, can pass through
Same method into CPLD chip 34' processing, is converted to and is sent to another piece through serial signal line 35' after serial signal
Processor plate, completes management board 31' and the signal of another piece of processor plate interconnects.
The dynamic configuration of the present invention is explained with reference to Figure 11, Figure 12.
Figure 11 is 8 road server of one kind, the 8 tunnel configuration processor topology schematic diagram of the embodiment of the present invention, as shown in figure 11,
By taking 8 road servers as an example.There are 4 pieces of identical processor plates in system, there are 2 CPU on every piece of processor plate.According to processor plate
Two CPU on processor plate 1 are configured in 8 tunnel topologys by the difference of slotting slot position, management board by writing configuration register
CPU0, CPU1, CPU2, CPU3 two CPU on processor plate 2 being configured in 8 tunnel topologys, by two on processor plate 3
A CPU is configured to CPU4, CPU5 in 8 tunnel topologys, two CPU on processor plate 4 are configured to CPU6 in 8 tunnel topologys,
CPU7.System is operated in the configuration of 8 tunnels.
Figure 12 is the double 4 tunnel configuration processor topology schematic diagrames of 8 road server of one kind of the embodiment of the present invention, such as Figure 12 institutes
Show, system need to configure for double 4 tunnels when, management board is changed each CPU configuration pins signal, will be handled by writing configuration register
Two CPU on device plate 1 are configured to CPU0, CPU1 in first 4 tunnel topology, and two CPU on processor plate 2 are configured to
CPU2, CPU3 in first 4 tunnel topology, two CPU on processor plate 3 are configured to CPU0 in second 4 tunnel topology,
CPU1, CPU2, the CPU3 two CPU on processor plate 4 being configured in second 4 tunnel topology.CPU shown in dotted line in topology
Interconnection line is closed according to configuration.System flexibly realizes that double 4 tunnels configure by the signal interconnection method of the present invention, and need not be into
Drop-down configures, plugs wire jumper or stir toggle switch in operation on row hardware, such as modification.
It is special using other that the present embodiment further includes the component of the scheme replaced as follows for serioparallel exchange transmission-receiving function
CPLD is replaced rather than used to chip or circuit；It is replaced for the specific implementation of the serioparallel exchange in CPLD and transmission-receiving function；
It is replaced for the serial signal frame format transmitted in serial signal line；It is replaced for serial signal line single-ended signal on board and backboard
Differential signal is changed to, in the case of no contradiction, use can be combined with the scheme of above-described embodiment.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should all be included in the protection scope of the present invention.
Claims (16)
1. a kind of backboard equipment, which is characterized in that including：
Backboard；
Board is inserted in the card slot of the backboard；
Back panel connector is connected between the backboard and the board, for the signal between the backboard and the board
Interconnection；
Signal conversion unit is connected between the connector and the board to turn the parallel signal from the board
After being changed to serial signal, the backboard is sent to by the connector or is converted to the serial signal from the backboard
The board is sent to after corresponding parallel signal.
2. equipment according to claim 1, which is characterized in that the signal conversion unit includes：Configuration register is used for
System configuration is carried out to the processor on the board.
3. equipment according to claim 1, which is characterized in that the signal conversion unit is Complex Programmable Logic Devices
CPLD chips.
4. equipment according to claim 1, which is characterized in that the board includes：Processor plate, input and output I O board,
Control panel, management board.
5. equipment according to claim 1, which is characterized in that the back panel connector further includes：Two null modem cables,
It is connected between the signal conversion unit and the board, is respectively used to transmission uplink signal and downlink signal.
6. a kind of signal interconnection method is applied on multipath server backboard, which is characterized in that including：
First parallel signal of the first board is converted into the first serial signal；
First serial signal is sent to the second board via back panel connector.
7. according to the method described in claim 6, it is characterized in that, the method further includes：
Receive the second serial signal that second board is sent via the back panel connector；
Decode second serial signal obtain the second parallel signal and on give first board.
8. according to the method described in claim 6, it is characterized in that, the first parallel signal of the first board is converted into the first string
Row signal includes：
The first parallel signal in board is obtained from first board；
First parallel signal is serialized by preset order；
Cyclic redundancy check (CRC) check code is calculated to the first parallel signal after serialization, and the cyclic redundancy check is attached to
Overall data is obtained after the first parallel signal after serialization；
Affix synchronizing frame head obtains first serial signal before the frame of the overall data.
9. the method according to the description of claim 7 is characterized in that decoding second serial signal obtains the second parallel signal
Including：
Detect the synchronizing frame head of second serial signal；
Receive the serial data in second serial signal；
Cyclic redundancy check is calculated to the serial data, and is compared with the additional cyclic redundancy check of data frame；
When cyclic redundancy check verification is correct, serial data frame is decoded to obtain second parallel signal.
10. according to the method described in claim 6, it is characterized in that, first parallel signal includes：From first board
Chip pin and/or the parallel signal that acquires of circuit pin and/or, configure deposit from the transmission of first board
The content of registers obtained in device.
11. according to the method described in claim 6, it is characterized in that, first board and second board are arranged on together
On one backboard.
12. the method according to the description of claim 7 is characterized in that second parallel signal includes：It is sent to described
The chip pin of one board and/or the signal of circuit pin and/or, configure signal, wherein, the configuration signal is for configuring
The configuration pin of processor.
13. a kind of signal interconnect device, is applied on multipath server backboard, which is characterized in that including：
First modular converter, for the first parallel signal of the first board to be converted to the first serial signal；
First sending module, for first serial signal to be sent to the second board via back panel connector.
14. device according to claim 13, which is characterized in that described device further includes：
Second modular converter, for receiving the second serial signal that second board is sent via the back panel connector；
Second sending module, for decode second serial signal obtain the second parallel signal and on give first plate
Card.
15. device according to claim 13, which is characterized in that first parallel signal includes：From first plate
Parallel signal that the chip and/or circuit pin of card acquire and/or, from the transmission configuration register of first board
The content of registers inside obtained.
16. device according to claim 14, which is characterized in that second parallel signal includes：It is sent to described
The chip pin of first board and/or the signal of circuit pin and/or, configure signal, wherein, the configuration signal is for matching somebody with somebody
Put the configuration pin of processor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611088931.7A CN108121412A (en) | 2016-11-30 | 2016-11-30 | Backboard equipment, signal interconnection method and device |
| PCT/CN2017/109728 WO2018099248A1 (en) | 2016-11-30 | 2017-11-07 | Back panel device, signal interconnection method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201611088931.7A CN108121412A (en) | 2016-11-30 | 2016-11-30 | Backboard equipment, signal interconnection method and device |
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| CN108121412A true CN108121412A (en) | 2018-06-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611088931.7A Pending CN108121412A (en) | 2016-11-30 | 2016-11-30 | Backboard equipment, signal interconnection method and device |
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| Country | Link |
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| CN (1) | CN108121412A (en) |
| WO (1) | WO2018099248A1 (en) |
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| WO2018099248A1 (en) | 2018-06-07 |
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