CN108109989A - Integral circuit keyset - Google Patents
Integral circuit keyset Download PDFInfo
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- CN108109989A CN108109989A CN201711349206.5A CN201711349206A CN108109989A CN 108109989 A CN108109989 A CN 108109989A CN 201711349206 A CN201711349206 A CN 201711349206A CN 108109989 A CN108109989 A CN 108109989A
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- diode
- silicon
- isolated groove
- tsv holes
- based substrate
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- 239000000758 substrate Substances 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 238000000926 separation method Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 3
- 230000000694 effects Effects 0.000 abstract description 8
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- -1 Boron ion Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of Integral circuit keyset, including:Silicon-based substrate 101, the first TSV holes 102, the 2nd TSV holes 103, the first isolated groove 104, the second isolated groove 105, the 3rd isolated groove 106, the first diode 107, the second diode 108, plug 109, metal interconnecting wires 110, salient point 111 and separation layer 112;The first TSV holes 102, first isolated groove 104, first diode 107, second isolated groove 105, the 2nd TSV holes 103, the 3rd isolated groove 106 and second diode 108 are transversely positioned apart from successively in the silicon-based substrate 101.Integral circuit keyset provided by the invention enhances the antistatic effect of laminate packaging chip.
Description
Technical field
The present invention relates to semiconductor device design and manufacturing field, more particularly to a kind of Integral circuit keyset.
Background technology
The characteristic size of integrated circuit is down to 7nm so far, and the number of transistors integrated on a single chip is
Through reaching 10,000,000,000 ranks, with the requirement of the number of transistors of 10,000,000,000 ranks, Resources on Chip and interconnection length problem become existing
The bottleneck of modern integrated circuit fields development, 3D integrated circuits are considered as the developing direction of future integrated circuits, its original circuit
On the basis of, it is stacked on Z axis, in the hope of integrating more functions on minimum area, this method overcomes original integrated
The limitation of degree using emerging technology silicon wafer through hole (Through SiliconVias, abbreviation TSV), is greatly improved integrated
The performance of circuit is reduced and postponed on line, reduces chip power-consumption.
Inside semicon industry, with the raising of integrated circuit integrated level and the reduction of device feature size, integrate
Potentiality damage caused by static discharge has become more and more apparent in circuit.According to relevant report, the event of integrated circuit fields
The failure for having nearly 35% in barrier is triggered by Electro-static Driven Comb (Electro-Static discharge, abbreviation ESD), therefore
Chip internal is all designed with esd protection structure to improve the reliability of device.However the antistatic effect of different chips is different,
The weak chip of antistatic effect influences whether the antistatic effect of whole system after encapsulation when three-dimensional stacked, therefore how to improve
The antistatic effect of 3D integrated circuits based on TSV techniques becomes semicon industry urgent problem to be solved.
The content of the invention
To solve technological deficiency and deficiency existing in the prior art, the present invention proposes a kind of antistatic suitable for integrated circuit
Pinboard.
An embodiment provides a kind of Integral circuit keyset, including:Silicon-based substrate 101, the first TSV holes
102nd, the 2nd TSV holes 103, the first isolated groove 104, the second isolated groove 105, the 3rd isolated groove 106, the first diode
107th, the second diode 108, plug 109, metal interconnecting wires 110, salient point 111 and separation layer 112;
The first TSV holes 102, first isolated groove 104, first diode 107, second isolating trenches
Slot 105, the 2nd TSV holes 103, the 3rd isolated groove 106 and second diode 108 transversely compartment of terrain successively
It is arranged in the silicon-based substrate 101;
The first TSV holes 102, the 2nd TSV holes 103, first isolated groove 104, second isolating trenches
Slot 105 and the 3rd isolated groove 106 run through the silicon-based substrate 101 along longitudinal direction;Wherein, the first TSV holes 102 with
Polysilicon, first isolated groove 104, second isolated groove 105 and described are filled in the 2nd TSV holes 103
Silica is filled in three isolated grooves 106;
The anode of first diode 107 and second diode 108 is arranged at 101 top of silicon-based substrate,
Cathode is arranged at and 101 lower part of silicon-based substrate;
The separation layer 112 is arranged at 101 upper and lower surface of silicon-based substrate;
The plug 109 is arranged in the separation layer 112 and is located at the polysilicon, first diode respectively
107 and 108 upper and lower surface of the second diode;
The metal interconnecting wires 110 are arranged in the separation layer 112 and make the first TSV holes through the plug 109
102nd, first diode 107, the 2nd TSV holes 103 and second diode 108 are connected in series;
The salient point 111 be arranged in the separation layer 112 and through the plug 109 respectively with the first TSV holes 102
Lower end, the lower end in the 2nd TSV holes 103, the moon of the cathode of first diode 107 and second diode 108
Pole is connected.
In one embodiment of the invention, the crystal orientation of the silicon-based substrate 101 is 100 either 110 or 111, doping
Concentration is 1014~1017cm-3, thickness is 450~550 μm.
In one embodiment of the invention, the impurity of the polysilicon is phosphorus, and doping concentration is 2 × 1021cm-3。
In one embodiment of the invention, the doped anode of first diode 107 and second diode 108
Impurity is boron, doping concentration preferably 5 × 1018cm-3。
In one embodiment of the invention, the cathode of first diode 107 and second diode 108 adulterates
Impurity is phosphorus, doping concentration preferably 5 × 1018cm-3。
In another embodiment of the present invention, the plug 109 is tungsten.
In one embodiment of the invention, the metal interconnecting wires 110 are copper.
In one embodiment of the invention, the salient point 111 is copper.
In one embodiment of the invention, the separation layer 112 is silica.
Compared with prior art, the present invention at least has the advantages that:
1st, Integral circuit keyset provided by the invention, by processing ESD protection device --- two poles on TSV pinboards
Pipe enhances the antistatic effect of laminate packaging chip;
2nd, the isolated groove of up/down perforation is used around above-mentioned diode, there is smaller leakage current and parasitic capacitance;
It 3rd, can be since process proposed by the invention can be realized in existing TSV technique platforms
In the case of any fund of addition and equipment investment, increase the antistatic effect of TSV pinboards.
Description of the drawings
Below in conjunction with attached drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is a kind of structure diagram of Integral circuit keyset provided in an embodiment of the present invention;
Fig. 2 a- Fig. 2 i are a kind of preparation method schematic diagram of Integral circuit keyset provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Refer to Fig. 1, Fig. 1 is a kind of structure diagram of Integral circuit keyset provided in an embodiment of the present invention, the collection
Include into adapter plate for circuit 100:Silicon-based substrate 101, the first TSV holes 102, the 2nd TSV holes 103, the first isolated groove 104,
Two isolated grooves 105, the 3rd isolated groove 106, the first diode 107, the second diode 108, plug 109, metal interconnecting wires
110th, salient point 111 and separation layer 112;
First TSV holes 102, the first isolated groove 104, the first diode 107, the second isolated groove 105, the 2nd TSV holes
103rd, the 3rd isolated groove 106 and the second diode 108 are transversely positioned apart from silicon-based substrate 101 successively;
First TSV holes 102, the 2nd TSV holes 103, the first isolated groove 104, the second isolated groove 105 and the 3rd isolating trenches
Slot 106 runs through silicon-based substrate 101 along longitudinal direction;Wherein, polysilicon is filled in the first TSV holes 102 and the 2nd TSV holes 103, first
Silica is filled in isolated groove 104, the second isolated groove 105 and the 3rd isolated groove 106;
The anode of first diode 107 and the second diode 108 is arranged at 101 top of silicon-based substrate, cathode be arranged at
101 lower part of silicon-based substrate;
Separation layer 112 is arranged at 101 upper and lower surface of silicon-based substrate;
Plug 109 is arranged in separation layer 112 and is located at polysilicon, the first diode 107 and the second diode 108 respectively
Upper and lower surface;
Metal interconnecting wires 110 are arranged in separation layer 112 and make the first TSV holes 102, the first diode through plug 109
107th, the 2nd TSV holes 103 and the second diode 108 are connected in series;
Salient point 111 be arranged in separation layer 112 and through plug 109 respectively with the lower end in the first TSV holes 102, the 2nd TSV holes
The cathode of 103 lower end, the cathode of the first diode 107 and the second diode 108 is connected.
Preferably, the crystal orientation of silicon-based substrate 101 is 100 either 110 or 111, doping concentration 1014~1017cm-3, it is thick
It spends for 450~550 μm.
Preferably, the impurity of polysilicon is phosphorus, and doping concentration is 2 × 1021cm-3。
Preferably, the doped anode impurity of the first diode 107 and the second diode 108 be boron, doping concentration preferably 5 ×
1018cm-3。
Preferably, the cathode impurity of the first diode 107 and the second diode 108 be phosphorus, doping concentration preferably 5 ×
1018cm-3。
Preferably, plug 109 is tungsten.
Preferably, metal interconnecting wires 110 are copper.
Preferably, salient point 111 is copper.
Preferably, separation layer 112 is silica.
Integral circuit keyset provided in this embodiment, by processing ESD protection device --- two poles on TSV pinboards
It manages (wherein, the quantity of diode can be set as needed), enhances the antistatic effect of laminate packaging chip;It is in addition, above-mentioned
The isolated groove of up/down perforation is used around diode, there is smaller leakage current and parasitic capacitance.
Embodiment two
Fig. 2 a- Fig. 2 i, Fig. 2 a- Fig. 2 i be refer to as a kind of preparation of Integral circuit keyset provided in an embodiment of the present invention
Method schematic diagram, the preparation method include the following steps:
1st step chooses silicon-based substrate 201;The crystal orientation of silicon-based substrate 201 can be (100) either (110) or (111),
No limitations are hereby intended, in addition, the doping type of silicon-based substrate 201 can be N-type or be p-type, doping concentration example
Such as it is 1014~1017Cm-3, thickness are, for example, 450~550um.As shown in Figure 2 a.
2nd step, at a temperature of 1050~1100 DEG C, using thermal oxidation technology in silicon-based substrate 201 growth thickness be 800
The silicon dioxide layer of~1000nm;Using photoetching process, the first region to be etched, second to be etched is made in silicon dioxide layer
Region, the 3rd region to be etched, the 4th region to be etched and the 5th region to be etched;Using deep reaction ion etch process,
In the first region to be etched, the second region to be etched, the 3rd region to be etched, the 4th region to be etched and the 5th region to be etched
Silicon-based substrate is etched, is respectively formed the first TSV holes 202, the 2nd TSV holes 203, the first isolated groove 204, the second isolated groove
205 and the 3rd isolated groove 206;Silicon dioxide layer is removed using CMP process and silicon-based substrate surface is put down
Smoothization processing, as shown in Figure 2 b.
3rd step, using thermal oxidation technology, in TSV holes and isolated groove so that the inner wall of blind hole forms oxide layer;Wherein,
Oxidate temperature is 1050~1100 DEG C, and the thickness of oxide layer is 200~300nm;Utilize wet-etching technology, selective etch
Oxide layer is so that TSV holes and isolated groove inner wall are smooth, as shown in Figure 2 c;The purpose of the step is each TSV in order to prevent
The protrusion of hole side wall forms electric field concentrated area.
4th step, using photoetching process, form isolated groove filling region on silicon-based substrate surface;In 690~710 DEG C of temperature
Under degree, using chemical vapor deposition method, silica is deposited in isolated groove by isolated groove filling region, such as Fig. 2 d
It is shown.
5th step, using photoetching process, TSV holes filling region is formed on silicon-based substrate surface;In 600~620 DEG C of temperature
Under, using chemical vapor deposition method, by TSV holes filling region in TSV holes depositing polysilicon, and introduce impurity gas with
Doping in situ is carried out to polysilicon;Wherein, polysilicon doping concentration is preferably 2 × 1021cm-3, the preferred phosphorus of impurity, such as figure
Shown in 2e.
6th step, using CMP process, planarizing process is carried out to silicon-based substrate upper surface;Utilize photoetching work
Skill, selective etch photoresist form the first ion region to be implanted and the second ion area to be implanted in silicon-based substrate upper surface
Domain;Boron ion is mixed in silicon substrate to silicon-based substrate 201 by the first ion region to be implanted and the second ion region to be implanted
Substrate top is respectively formed the first P areas 207 and the 2nd P areas 208;Wherein, the doping concentration in the first P areas 207 and the 2nd P areas 208
It is preferred that 5 × 1018cm-3, the preferred boron of impurity, as shown in figure 2f.
7th step utilizes mechanical grinding technique, removal silicon-based substrate low portion material;Using CMP process,
To 201 lower surface of silicon-based substrate carry out planarizing process, the first TSV holes 202, the 2nd TSV holes 203, the first isolated groove 204,
Second isolated groove 205 and the 3rd isolated groove 206 run through silicon-based substrate 201;Wherein, the silicon-based substrate 201 of remainder is thick
Degree is preferably 300 μm~400 μm, as shown in Figure 2 g.
8th step, using photoetching process, selective etch photoresist forms the 3rd ion in silicon-based substrate upper surface and waits to note
Enter region and the 4th ion region to be implanted;It is served as a contrast by the 3rd ion region to be implanted and the 4th ion region to be implanted to silicon substrate
Bottom 201 mixes phosphonium ion to form the first N areas 209 and the 2nd N areas 210 in 201 lower part of silicon-based substrate, in 950~1100 DEG C of temperature
Under degree, to entire 15~120s of anneal of material, by mixed impurity activation, N-type region dopant concentration preferably 5 × 1018cm-3,
The preferred phosphorus of impurity;Wherein, the first P areas 207, the first N areas 209 and its between silicon-based substrate form the first diode, the
Two P areas 208, the 2nd N areas 210 and its between silicon-based substrate formed the second diode, as shown in fig. 2h.
9th step, the upper and lower surface making plug 211 in polysilicon, the first diode and the second diode;In specified region
211 surface of plug make metal interconnecting wires 212 so that the first TSV holes 202, the first diode, the 2nd TSV holes 203 and second
Diode forms serial connection;211 table of plug on 211 surface of plug and the second diode cathode below the first TSV holes 202
Face makes salient point 213, as shown in fig. 2i;Wherein, while surround spiral using metal interconnecting wires and make it have inductance
Characteristic to be more particularly for the electrostatic protection of RF IC.
It should be noted that isolated groove is to separate diode and the connection of other structures in pinboard, therefore isolate
Groove can be made as enclosed construction (such as cyclic structure) and through substrate material, and diode is located inside the enclosed construction.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
On the premise of not departing from present inventive concept, several simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (9)
1. a kind of Integral circuit keyset (100), which is characterized in that including:Silicon-based substrate (101), the first TSV holes (102),
Two TSV holes (103), the first isolated groove (104), the second isolated groove (105), the 3rd isolated groove (106), the first diode
(107), the second diode (108), plug (109), metal interconnecting wires (110), salient point (111) and separation layer (112);
The first TSV holes (102), first isolated groove (104), first diode (107), second isolation
Groove (105), the 2nd TSV holes (103), the 3rd isolated groove (106) and second diode (108) are transversely
It is positioned apart from successively in the silicon-based substrate (101);
The first TSV holes (102), the 2nd TSV holes (103), first isolated groove (104), second isolation
Groove (105) and the 3rd isolated groove (106) run through the silicon-based substrate (101) along longitudinal direction;Wherein, described first
TSV holes (102) and filling polysilicon in the 2nd TSV holes (103), first isolated groove (104), second isolation
Filling silica in groove (105) and the 3rd isolated groove (106);
The anode of first diode (107) and second diode (108) is arranged in the silicon-based substrate (101)
Portion, cathode are arranged at and the silicon-based substrate (101) lower part;
The separation layer (112) is arranged at the silicon-based substrate (101) upper and lower surface;
The plug (109) is arranged in the separation layer (112) and is located at the polysilicon, first diode respectively
(107) and second diode (108) upper and lower surface;
The metal interconnecting wires (110) are arranged in the separation layer (112) and make the first TSV through the plug (109)
Hole (102), first diode (107), the 2nd TSV holes (103) and second diode (108) serial connection;
The salient point (111) be arranged in the separation layer (112) and through the plug (109) respectively with the first TSV holes
(102) lower end, the lower end of the 2nd TSV holes (103), the cathode of first diode (107) and the two or two pole
The cathode of pipe (108) is connected.
2. Integral circuit keyset according to claim 1, which is characterized in that the crystal orientation of the silicon-based substrate (101) is
(100) either (110) or (111), doping concentration 1014~1017cm-3, thickness is 450~550 μm.
3. Integral circuit keyset according to claim 1, which is characterized in that the impurity of the polysilicon is phosphorus,
Doping concentration is 2 × 1021cm-3。
4. Integral circuit keyset according to claim 1, which is characterized in that first diode (107) with it is described
The doped anode impurity of second diode (108) is boron, and doping concentration is 5 × 1018cm-3。
5. Integral circuit keyset according to claim 1, which is characterized in that first diode (107) with it is described
The cathode impurity of second diode (108) is phosphorus, and doping concentration is 5 × 1018cm-3。
6. Integral circuit keyset according to claim 1, which is characterized in that the plug (109) is tungsten.
7. Integral circuit keyset according to claim 1, which is characterized in that the metal interconnecting wires (110) are copper.
8. Integral circuit keyset according to claim 1, which is characterized in that the salient point (111) is copper.
9. Integral circuit keyset according to claim 1, which is characterized in that the separation layer (112) is silica.
Priority Applications (1)
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CN201711349206.5A CN108109989A (en) | 2017-12-15 | 2017-12-15 | Integral circuit keyset |
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CN201711349206.5A CN108109989A (en) | 2017-12-15 | 2017-12-15 | Integral circuit keyset |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
US20090283914A1 (en) * | 2008-05-15 | 2009-11-19 | Shinko Electric Industries Co., Ltd. | Silicon interposer and method for manufacturing the same |
US20140346651A1 (en) * | 2013-05-21 | 2014-11-27 | Xilinx, Inc. | Charge damage protection on an interposer for a stacked die assembly |
US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
CN105702667A (en) * | 2014-12-16 | 2016-06-22 | 台湾积体电路制造股份有限公司 | Interposer and method for fabricating the interposer, electronic device and production device |
-
2017
- 2017-12-15 CN CN201711349206.5A patent/CN108109989A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
US20090283914A1 (en) * | 2008-05-15 | 2009-11-19 | Shinko Electric Industries Co., Ltd. | Silicon interposer and method for manufacturing the same |
US20140346651A1 (en) * | 2013-05-21 | 2014-11-27 | Xilinx, Inc. | Charge damage protection on an interposer for a stacked die assembly |
US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
CN105702667A (en) * | 2014-12-16 | 2016-06-22 | 台湾积体电路制造股份有限公司 | Interposer and method for fabricating the interposer, electronic device and production device |
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