CN108109919B - Three-dimensional field effect transistor and manufacturing method thereof - Google Patents
Three-dimensional field effect transistor and manufacturing method thereof Download PDFInfo
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- CN108109919B CN108109919B CN201711337484.9A CN201711337484A CN108109919B CN 108109919 B CN108109919 B CN 108109919B CN 201711337484 A CN201711337484 A CN 201711337484A CN 108109919 B CN108109919 B CN 108109919B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 63
- 230000005669 field effect Effects 0.000 claims abstract description 44
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 37
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 14
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 32
- 239000002210 silicon-based material Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 7
- 230000002411 adverse Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention provides a three-dimensional field effect transistor and a manufacturing method thereof, wherein the manufacturing method of the three-dimensional field effect transistor comprises the following steps: providing an SOI substrate, and carrying out incomplete etching on top silicon of the SOI substrate to form a fin structure, wherein a silicon thin layer is arranged below the fin structure; forming a silicon nitride layer on the surfaces of the silicon thin layer and the fin structure; etching the silicon nitride layer and the silicon thin layer to form a silicon interface region between the fin structure and the insulating layer of the SOI substrate; oxidizing a silicon interface region at the bottom of the fin structure into a silicon dioxide region; and removing the silicon nitride layer on the surface of the fin part structure, and forming a gate oxide layer on the surface of the fin part structure.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a three-dimensional field effect transistor and a manufacturing method thereof.
[ background of the invention ]
A fin field effect transistor (FinFET) adopts a fin channel structure and is a field effect transistor with a three-dimensional structure. In a three-dimensional field effect transistor, a Fin (Fin) is vertically formed on a surface of an SOI (Silicon on Insulator) substrate, and the Fin serves as a channel, and a gate electrode covers the surface of the Fin to control the channel.
In a conventional three-dimensional field effect transistor structure, because various defects are easily existing at an interface between an insulating layer and top silicon in a manufacturing process of an SOI substrate material, and a current between a source and a drain of the three-dimensional field effect transistor generally needs to pass through the interface region, the current control capability of a gate to the interface region has many electrical anomalies due to the existence of the defects, so that the overall performance of the three-dimensional field effect transistor is influenced.
In view of the above, it is desirable to provide a three-dimensional field effect transistor and a method for fabricating the same to solve the above-mentioned problems in the prior art.
[ summary of the invention ]
One of the objectives of the present invention is to provide a method for fabricating a three-dimensional field effect transistor to solve the above problems. Another object of the present invention is to provide a three-dimensional field effect transistor manufactured by the above manufacturing method.
The invention provides a method for manufacturing a three-dimensional field effect transistor, which comprises the following steps: providing an SOI substrate, and etching top silicon of the SOI substrate to form a fin structure, wherein a silicon thin layer is arranged below the fin structure; forming a silicon nitride layer on the surfaces of the silicon thin layer and the fin structure; etching the silicon nitride layer and the silicon thin layer to form a silicon interface region between the fin structure and the insulating layer of the SOI substrate; oxidizing a silicon interface region at the bottom of the fin structure into a silicon dioxide region; and removing the silicon nitride layer on the surface of the fin part structure, and forming a gate oxide layer on the surface of the fin part structure.
As an improvement of the method for manufacturing the three-dimensional field effect transistor provided in the present invention, in a preferred embodiment, the top layer silicon of the SOI substrate is not completely etched to form a fin structure perpendicular to the SOI substrate, and a thin layer of silicon remains on the surface of the insulating layer below the fin structure.
As an improvement of the method for manufacturing the three-dimensional field effect transistor provided in the present invention, in a preferred embodiment, the silicon nitride layer is formed on the surface of the thin silicon layer and entirely covers the side surfaces and the top surface of the fin structure.
As an improvement of the method for manufacturing the three-dimensional field effect transistor provided by the present invention, in a preferred embodiment, the silicon nitride layer is grown at a temperature of 600-1100 ℃, and the thickness of the silicon nitride layer is 0.01-0.1 um.
As an improvement of the method for manufacturing a three-dimensional field effect transistor provided by the present invention, in a preferred embodiment, the silicon nitride layer and the silicon thin layer are etched by a dry etching process, and the silicon nitride layer on the top surface of the fin structure is etched away during the etching process to expose the silicon material on the top of the fin structure.
As an improvement of the method for manufacturing a three-dimensional field effect transistor provided by the present invention, in a preferred embodiment, the silicon interface region is oxidized into the silicon dioxide region by performing an oxidation treatment at a temperature of 1000 to 1300 ℃ for 50 to 300 minutes.
As an improvement of the method for fabricating the three-dimensional field effect transistor provided in the present invention, in a preferred embodiment, during the oxidation process of the silicon interface region, the silicon material exposed at the top of the fin structure is simultaneously oxidized to form a top silicon dioxide layer.
As an improvement of the method for manufacturing the three-dimensional field effect transistor provided in the present invention, in a preferred embodiment, the gate oxide layer is formed on a side surface of the fin structure, and surrounds the silicon material of the fin structure together with the silicon dioxide regions at the top and bottom of the fin structure.
As an improvement of the method for manufacturing a three-dimensional field effect transistor provided in the present invention, in a preferred embodiment, the method further includes: and manufacturing a grid electrode on the surface of the gate oxide layer, wherein the grid electrode integrally covers the gate oxide layer on the side surface of the fin part structure, and the silicon dioxide top layer and the silicon dioxide area on the top and the bottom of the fin part structure.
The three-dimensional field effect transistor provided by the invention is manufactured by adopting the manufacturing method and comprises a silicon substrate, an insulating layer positioned on the surface of the silicon substrate and a fin structure positioned above the insulating layer, wherein a silicon dioxide region is arranged between the bottom of the fin structure and the insulating layer, and a gate oxide layer is formed on the side wall of the fin structure.
Compared with the prior art, the three-dimensional field effect transistor and the manufacturing method thereof provided by the invention have the advantages that the silicon dioxide region is formed by oxidizing the intersection boundary region of the top layer silicon and the insulating layer, so that the source-drain current of the three-dimensional field effect transistor is prevented from passing through the region, the adverse effect caused by the defect of the interface region between the top layer silicon and the insulating layer is effectively solved, and the electrical performance of the three-dimensional field effect transistor is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional field effect transistor according to an embodiment of the present invention;
fig. 2 to 9 are schematic views of the process steps of the method for manufacturing the three-dimensional field effect transistor shown in fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the problem that the three-dimensional field effect transistor in the prior art has defects in an interface region between top silicon and an insulating layer of an SOI substrate, the three-dimensional field effect transistor and the manufacturing method thereof provided by the invention form a silicon dioxide region by oxidizing a junction region where the top silicon and the insulating layer intersect, thereby preventing source-drain current of the three-dimensional field effect transistor from passing through the region, effectively solving the adverse effect caused by the defects in the interface region between the top silicon and the insulating layer, and improving the electrical performance of the three-dimensional field effect transistor.
Please refer to fig. 1, which is a flowchart illustrating a method for fabricating a three-dimensional field effect transistor according to an embodiment of the present invention. The three-dimensional field effect transistor can be a fin field effect transistor (FinFET) adopting a fin channel structure, and specifically, the manufacturing method of the three-dimensional field effect transistor mainly comprises the following steps:
step S1, providing an SOI substrate, and carrying out incomplete etching on top silicon of the SOI substrate to form a fin structure, wherein a thin silicon layer is arranged below the fin structure;
as shown in fig. 2, an SOI (Silicon on Insulator) substrate is first provided, and the SOI substrate includes a back substrate (Si), an insulating layer formed on a bottom surface of the back substrate, and a top Silicon formed on a surface of the insulating layer, wherein the insulating layer between the back substrate and the top Silicon is also called a Buried Oxide (BOX).
Etching the top silicon layer of the SOI substrate to form a fin structure vertical to the SOI substrate; referring to fig. 3, in this step, the top silicon is not completely etched, i.e., the top silicon around the fin structure is not etched through to the surface of the insulating layer of the SOI substrate, so that a thin layer of silicon still remains on the surface of the insulating layer below the fin structure.
Step S2, forming a silicon nitride layer on the silicon thin layer and the surface of the fin structure;
referring to fig. 4, the silicon nitride layer is formed on the surface of the thin silicon layer and entirely covers the side surfaces and the top surface of the fin structure. Wherein the silicon nitride layer can be grown at a temperature of 600-1100 ℃, and as a preferred embodiment, the thickness of the silicon nitride layer can be about 0.01-0.1 um.
Step S3, etching the silicon nitride layer and the silicon thin layer to form a silicon interface region between the fin structure and the insulating layer of the SOI substrate;
specifically, referring to fig. 5, the silicon nitride layer and the silicon thin layer covered by the silicon nitride layer may be processed by dry etching, and in a specific embodiment, the silicon nitride layer and the silicon thin layer outside the region where the fin structure is located are completely etched. And in the etching process, the silicon nitride layer on the top surface of the fin structure is etched away to expose the silicon material on the top of the fin structure, and after the etching is finished, the silicon nitride layer on the side surface of the fin structure still remains. In the etching process, due to the existence of the fin structure, the silicon thin layer below the fin structure is not etched and still remains, so that a silicon interface region is formed between the fin structure and the insulating layer of the SOI substrate.
Step S4, oxidizing a silicon interface region at the bottom of the fin structure into a silicon dioxide region;
referring to fig. 6, in step S4, the silicon interface region at the bottom of the fin structure is oxidized to a silicon dioxide region because the silicon interface region is not covered by the silicon nitride layer on the side of the fin structure, wherein the silicon interface region may be oxidized at a temperature of 1000-1300 ℃ for 50-300 minutes. In this step, since the silicon interface region at the bottom of the fin structure is oxidized into the silicon dioxide region, the fin structure and the insulating layer of the SOI substrate are insulated and isolated by the silicon dioxide region, so that the source-drain current of the fin structure is prevented from passing through the interface region between the fin structure and the insulating layer, which may have defects.
On the other hand, since the silicon nitride layer on the top surface of the fin structure is etched away in step S3 to expose the silicon material on the top of the fin structure, a top silicon dioxide layer is simultaneously formed on the top of the fin structure during the oxidation process, as shown in fig. 6.
Step S5, removing the silicon nitride layer on the surface of the fin part structure, and forming a gate oxide layer on the surface of the fin part structure;
specifically, referring to fig. 7, first, the silicon nitride layer on the side surface of the fin structure may be removed by placing the device in concentrated sulfuric acid, and after the silicon nitride layer is removed, the fin structure, the silicon dioxide region at the bottom thereof, and the silicon dioxide top layer at the top thereof are completely exposed.
Then, referring to fig. 8, the silicon material of the fin structure is oxidized by an oxidation process to form a gate oxide layer on the surface thereof, where the oxidation temperature may be 1000 to 1300 ℃, and the oxidation time may be 20 to 300 minutes; the method is characterized in that after the gate oxide layer is formed, the silicon nitride layer on the surface of the fin structure is replaced on the structure, and the gate oxide layer can be set to have a preset thickness through process conditions, so that the surface of the gate oxide layer is basically flush with a silicon dioxide region below the fin structure.
Since the top and the bottom of the fin structure are respectively provided with a silicon dioxide top layer and a silicon dioxide area, the gate oxide layer is actually only formed on the side surface of the fin structure. After the gate oxide layer is formed, the silicon material of the fin structure is wholly surrounded by the gate oxide layer, the silicon dioxide top layer and the silicon dioxide area.
And step S6, manufacturing a grid on the surface of the grid oxide layer.
Referring to fig. 9, the gate may be a metal electrode, and the gate entirely covers the gate oxide layer on the side of the fin structure and the silicon dioxide top layer and the silicon dioxide region on the top and bottom of the fin structure.
Compared with the prior art, the manufacturing method of the three-dimensional field effect transistor provided by the invention has the advantages that the silicon dioxide region is formed by oxidizing the intersection boundary region of the top layer silicon and the insulating layer, so that the source-drain current of the three-dimensional field effect transistor is prevented from passing through the region, the adverse effect caused by the defect of the interface region between the top layer silicon and the insulating layer is effectively solved, and the electrical performance of the three-dimensional field effect transistor is improved.
Based on the manufacturing method of the three-dimensional field effect transistor, the invention also provides the three-dimensional field effect transistor manufactured by the manufacturing method, and the structure of the three-dimensional field effect transistor can be shown in fig. 9.
Specifically, the three-dimensional field effect transistor comprises a silicon substrate, an insulating layer located on the surface of the silicon substrate and a fin structure located above the insulating layer, wherein a silicon dioxide region is arranged between the bottom of the fin structure and the insulating layer, and a gate oxide layer is formed on the side wall of the fin structure. In addition, in this embodiment, the top of the fin structure further has a silicon dioxide top layer, wherein the silicon dioxide top layer, the gate oxide layer and the silicon dioxide region entirely surround the silicon material of the fin structure. Further, the three-dimensional field effect transistor also comprises a grid electrode, and the grid electrode covers the surfaces of the silicon dioxide top layer, the grid oxide layer and the silicon dioxide area.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (4)
1. A method for fabricating a three-dimensional field effect transistor, comprising:
providing an SOI substrate, and etching top silicon of the SOI substrate to form a fin structure, wherein a silicon thin layer is arranged below the fin structure;
forming a silicon nitride layer on the surfaces of the silicon thin layer and the fin structure;
etching the silicon nitride layer and the silicon thin layer to form a silicon interface region between the fin structure and the insulating layer of the SOI substrate;
oxidizing a silicon interface region at the bottom of the fin structure into a silicon dioxide region;
removing the silicon nitride layer on the surface of the fin part structure, and forming a gate oxide layer on the surface of the fin part structure;
the silicon nitride layer and the silicon thin layer are etched through a dry etching process, and the silicon nitride layer on the top surface of the fin structure is etched away in the etching process so that the silicon material on the top of the fin structure is exposed; in the oxidation process of the silicon interface region, the silicon material exposed at the top of the fin structure is oxidized at the same time to form a silicon dioxide top layer; the gate oxide layer is formed on the side face of the fin portion structure and surrounds the silicon material of the fin portion structure together with the silicon dioxide regions on the top and bottom of the fin portion structure; and manufacturing a grid electrode on the surface of the gate oxide layer, wherein the grid electrode integrally covers the gate oxide layer on the side surface of the fin part structure, and the silicon dioxide top layer and the silicon dioxide area on the top and the bottom of the fin part structure.
2. The method of claim 1, wherein the silicon nitride layer is formed on the surface of the thin silicon layer and entirely covers the side surfaces and the top surface of the fin structure.
3. The method of claim 2, wherein the silicon nitride layer is grown at a temperature of 600 ℃ to 1100 ℃ and has a thickness of 0.01um to 0.1 um.
4. The method of claim 1, wherein the silicon interface region is oxidized to the silicon dioxide region by performing an oxidation treatment at a temperature of 1000 ℃ to 1300 ℃ for 50 minutes to 300 minutes.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425346A (en) * | 2013-09-10 | 2015-03-18 | 中国科学院微电子研究所 | Manufacturing method for fin on insulator |
| CN105428238A (en) * | 2014-09-17 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | FinFET device, manufacturing method thereof, and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104425346A (en) * | 2013-09-10 | 2015-03-18 | 中国科学院微电子研究所 | Manufacturing method for fin on insulator |
| CN105428238A (en) * | 2014-09-17 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | FinFET device, manufacturing method thereof, and electronic device |
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