CN108108237A - A kind of periodic associated task heterogeneous polynuclear mapping scheduler method based on MILP - Google Patents

Abstract

The invention discloses a kind of periodic associated task heterogeneous polynuclear mapping scheduler methods based on MILP, it is constrained in the priority for ensureing associated task with communicating, and on the premise of the not overlapping execution of duty cycle, processor core number used in being minimized based on mixed integer linear programming minimizes scheduler latency, and solution obtains optimal scheduling scheme.Therefore, it is the mapping scheduler problem for having in the heterogeneous multi-core system connected entirely the periodic duty successively constrained that the present invention, which can efficiently solve framework,.

Description

A kind of periodic associated task heterogeneous polynuclear mapping scheduler method based on MILP

Technical field

The present invention relates to the mapping scheduler method of heterogeneous multi-core system, more particularly to a kind of periodic associated based on MILP Business heterogeneous polynuclear mapping scheduler method.

Background technology

In real-time communication system, communication process can be modeled as periodic associated task-set, wherein each Communication module is considered as a subtask, and the dependence of data is considered as the precedence relationship between task and task, and each Communication module is all periodically to arrive, and the data frame of each module is in multiple proportion.It is continuously counted to handle According to stream, task module is usually all computation-intensive and highly-parallel, therefore they are highly suitable for holding in multiple nucleus system Row.For the mobile communication application quickly grown instantly, polycaryon processor has great advantage, has in the communications field Extremely it is widely applied.In numerous multiple nucleus systems, heterogeneous polynuclear becomes more and more concerned, by by multiple computing capabilitys Different processors integrate, and are capable of providing more effective processing capacity.And how application heterogeneity polycaryon processor comes in fact Existing diversified communication system and the solution for completing multi-standard, overriding concern is that periodic associated task is more in isomery Mapping scheduler problem in core system.

Mapping scheduler problem of the periodic associated task in heterogeneous multi-core system is how N number of periodic duty to be assigned to On suitable processor and arrange the execution sequence of task on each processor.Each task is by performing time and task week Phase is characterized, the time interval between the continuous example of any two of task be equal to its cycle, once at the beginning of task with And after the processor performed is designated, task will periodically perform on definite time point, and with other tasks It does not clash, i.e. the execution time does not overlap.

Although mapping scheduler problem of the periodic associated task in heterogeneous multi-core system has proven to np hard problem, together When researchers be made that substantial amounts of research also for different problems background.But since in practical applications, there are general places The application scenarios of reason device and application specific processor (such as DSP, FPGA) collaboration processing task, and the multiprocessing under the application scenarios Device framework is the pool of processor for including multiple isomeries, and the processor included in each pool of processor is isomorphism, between processor It connects entirely.And grinding there is presently no the mapping scheduler for periodic associated task in the heterogeneous multi-nucleus processor framework Study carefully.

The content of the invention

It is an object of the invention to overcome the above-mentioned deficiency in the presence of the prior art, providing one kind can will have successively about Mapping scheduler algorithm in the periodic duty mapping scheduler to heterogeneous multi-processor of beam, and so that processor number used is minimum Or scheduler latency is most short.

In order to realize foregoing invention purpose, the present invention provides following technical schemes：

A kind of periodic associated task heterogeneous polynuclear mapping scheduler method based on MILP, which is characterized in that including,

Task definition；Wherein, N number of task is given, task-set is expressed as T={ τ₁, τ₂..., τ_N, the cycle of each task For T_i, execution time first time of task is s_i, a length of b during the execution of task_mi；When two task τs_i, τ_jτ is expressed as when associated_i →τ_j, and task τ_iWith task τ_jBetween communication time be e_ij；Give M pool of processor, pool of processor set representations be Φ= {ψ₁, ψ₂..., ψ_M, comprising P processor in each pool of processor, the processor collection in pool of processor is defined as P={ p₁, p₂..., p_P}；

Set constraints；Wherein, the constraints of setting includes：

Tasks carrying constraints：

Duty mapping constraints：Wherein binary variable map_imp=0, 1 }, map is worked as_impFor 1 when represent task τ_iIt is mapped on p-th of processor of m-th of pool of processor；

Processor mappings constraint condition：

Wherein binary variable pro_mp={ 0,1 }, works as pro_mpFor 1 when represent that at least one task is mapped at m-th On p-th of processor for managing device pond；

Two tasks carrying constraintss：

S.t.) i ≠ j, sep_ij+map_imp+map_jmp≤2

S.t.) i ≠ j, k ≠ m or p ≠ l, sep_ij-map_imp-map_jkl≥-1

b_mmi-sep_ijZ≤(s_j-s_i)modg_{I, j}≤g_{I, j}-b_mj+sep_ijZ

Wherein, binary variable sep_ij={ 0,1 }, works as sep_ijFor 1 when represent task τ_i, τ_jIt is mapped to different processors On, and work as sep_ijFor 0 when represent task τ_i, τ_jIt is mapped in same processor；g_{I, j}For two task τs_i, τ_jThe most grand duke in cycle Approximate number, i.e. g_{I, j}=gcd (T_i, T_j)；Z is constant integer；

Moreover, because linear programming needs to handle linear constraints, and (s_j-s_i)modg_{I, j}Be it is nonlinear, therefore Make (s_j-s_i)modg_{I, j}=(s_j-s_i)-q_{J, i}g_{I, j}, by (s_j-s_i)modg_{I, j}It linearizes wherein, q_{J, i}For integer variable and q_{J, i}'s Value range is

Associated task constraints：

Situation 1, works as τ_i→τ_j, T_i=T_jWhen, then associated task constraints is：

b_mi-sep_ijZ≤(s_j-s_i)-q_{J, i}g_{I, j}≤g_{I, j}-b_mj+sep_ijZ

Wherein, c_ijRepresent task τ_iWith task τ_jBetween communication overhead；

Situation 2, works as τ_i→τ_j, aT_i=T_j,Then associated task constraints is：

Situation 3, works as τ_i→τ_j, T_i=aT_j,When, associated task constraints and the associated task of situation 1 constrain It is consistent；

Set object function；Wherein, object function is：

Moreover, the MILP in the present invention refers to mixed integer linear programming algorithm.

Compared with prior art, beneficial effects of the present invention：

The present invention is based on the periodic associated task heterogeneous polynuclear mapping scheduler methods of MILP, are ensureing the priority of associated task Constraint with communicate and duty cycle not overlap execution on the premise of, based on mixed integer linear programming to minimize The processor core number or minimum scheduler latency, solution used obtains optimal scheduling scheme.Therefore, the present invention can be effective Ground solves the problems, such as the mapping scheduler that framework is the periodic duty for having priority restriction relation in the heterogeneous multi-core system connected entirely.

Description of the drawings：

Fig. 1 is the flow diagram of the present invention；

Fig. 2 is the characterization schematic diagram of subtask；

Fig. 3 is the schematic diagram of the three dimensional task figure example of channel estimation balancing；

Fig. 4 is the task image of emulation input；

Fig. 5 and Fig. 6 is respectively the mapping scheduler knot for minimizing scheduling processor number used and minimizing scheduler latency Fruit is schemed.

Specific embodiment

With reference to test example and specific embodiment, the present invention is described in further detail.But this should not be understood Following embodiment is only limitted to for the scope of the above-mentioned theme of the present invention, it is all that this is belonged to based on the technology that present invention is realized The scope of invention.

With reference to the flow diagram of the present invention shown in FIG. 1；Wherein, the present invention includes task definition, sets constraints With setting three steps of object function.

Wherein, with reference to the characterization schematic diagram of subtask shown in Fig. 2；When carrying out task definition, N number of task is given, is appointed Business set representations are T={ τ₁, τ₂..., τ_N, the cycle of each task is T_i, execution time first time of task is s_i, task holds A length of b during row_mi.When two task τs_i, τ_jτ is expressed as when associated_i→τ_j(i.e. task τ_iWith task τ_jHave priority restriction relation), and Task τ_iWith task τ_jBetween communication time be e_ij.Meanwhile M pool of processor is given, pool of processor set representations are Φ={ ψ₁, ψ₂..., ψ_M, comprising P processor in each pool of processor, the processor collection in pool of processor is defined as P={ p₁, p₂..., p_P}。

On the basis of above-mentioned task definition, appoint for the cycle for having priority restriction relation in the multiple nucleus system connected entirely The mapping scheduler problem of business proposes constraints and object function based on mixed integer linear programming algorithm.

Wherein, the constraints of setting includes：

Tasks carrying constraints：It is non-negative at the beginning of i.e. each task.

Duty mapping constraints：Wherein binary variable map_imp=0, 1 }, and by map_impIt is defined as：Work as map_impFor 1 when represent task τ_iIt is mapped to p-th of processor of m-th of pool of processor On.

Processor mappings constraint condition：map_imp≤pro_mp, wherein binary variable pro_mp={ 0,1 }, and by pro_mpIt is defined as：Work as pro_mpFor 1 when represent that at least one task is mapped to m-th of processor On p-th of processor in pond.And if some processor is not carried out any task, it can be true by following constraints It is fixed：

Two tasks carrying constraintss：Wherein, task τ is worked as_i, τ_jWhen being performed in same processor, it is necessary to assure two The execution time of business does not overlap.Therefore, if binary variable sep_ij={ 0,1 }, and by sep_ijIt is defined as：Work as sep_ijFor 1 when represent Task τ_i, τ_jIt is mapped on different processors, and works as sep_ijFor 0 when represent task τ_i, τ_jIt is mapped to same processor On.

Specifically, work as task τ_i, τ_jIt is mapped to when being performed in same processor, the constraints of satisfaction is：

S.t.) i ≠ j, sep_ij+map_imp+map_jmp≤2

And work as task τ_i, τ_jIt is mapped to when being performed on different processors, the constraints of satisfaction is：

S.t.) i ≠ j, k ≠ m or p ≠ l, sep_ij-map_imp-map_jkl≥-1

And, it is ensured that any two task is not overlapped when being performed in same processor, according to Sheikh A A, Brun O, Hladik P E et al. are in document《Strictly periodic scheduling in IMA-based Architectures [J] .Real-Time Systems, 2012,48 (4)：359-386.》Described in content understand：Two Be engaged in τ_i, τ_jThe execution that can not overlapped on the same processor, and if only if：

Wherein, g_{I, j}For two task τs_i, τ_jThe greatest common divisor in cycle, i.e. g_{I, j}=gcd (T_i, T_j).On the one hand, in order to true It protects only in sep_ijIn the case of=0, b_mi≤(s_j-s_i)modg_{I, j}≤g_{I, j}-b_mjJust set up, and it is very big by introducing a value Constant integer Z, and obtain：

b_mi-sep_ijZ≤(s_j-s_i)modg_{I, j}≤g_{I, j}-b_mj+sep_ijZ

On the other hand, since linear programming needs to handle linear constraints, and (s_j-s_i)modg_{I, j}It is non-linear , and in order to by (s_j-s_i)modg_{I, j}Linearisation, according to SheikhAA, Brun O, Hladik P E et al. are in document 《Strictly periodic scheduling in IMA-based architectures[J].Real-Time Systems, 2012,8 (4)：359-386.》Described in content understand：

(s_j-s_i)modg_{I, j}=(s_j-s_i)-q_{J, i}g_{I, j}

Wherein, q_{J, i}For integer variable and q_{J, i}Value range be

Finally, two tasks carrying constraintss are：

S.t.) i ≠ j, sep_ij+map_imp+map_jmp≤2

b_mI-sep_ijZ≤(s_j-s_i)-q_{J, i}g_{I, j}≤g_{I, j}-b_mj+sep_ijZ

Associated task constraints：

Situation 1, works as τ_i→τ_j, T_i=T_jWhen, due to front and rear two each task τs_i, τ_jCycle phase simultaneously, work as task τ_i, τ_jQuilt , it is necessary to communication between ensureing the priority and task of tasks carrying when being mapped on different processors, therefore communication overhead is only When two tasks are performed separately (sep_ij=1) just set up when.Work as task τ_i, τ_j, it is necessary to ensure when being mapped in same processor The priority of tasks carrying and not overlapping execution, then associated task constraints be：

b_mi-sep_ijZ≤(s_j-s_i)-q_{J, i}g_{I, j}≤g_{I, j}-b_mj+sep_ijZ

Wherein, c_ijRepresent task τ_iWith task τ_jBetween communication overhead.

Situation 2, works as τ_i→τ_j, aT_i=T_j,When, due to task τ_iThe frequency of arrival is task τ_jA times when, it is first First, it should meet the constraints of situation 1.Secondly, in cycle T_jIt is interior, task τ_jExecution be can have a task τ_iTriggering 's.Moreover, processor number used is minimum or scheduler latency is most short in order to make, passes through and set first task τ_iPerform completion Communication data is consigned into task τ afterwards_j, ensure in cycle T_iInterior task τ_jIt has been be able to carry out that, therefore, associated task constraints For：

Situation 3, works as τ_i→τ_j, T_i=aT_j,When, due to working as task τ_jThe frequency of arrival is task τ_iA times when, In cycle T_iIt is interior, task τ_iCommunication data is consigned into first task τ after having performed_j, since the traffic is to be disappeared completely Consumption, therefore second task τ_jExecution will necessarily be complete in other tasks carryings and communication data be consigned into second task τ_jStart afterwards.Therefore, 3 associated task constraints of situation is consistent with the associated task constraints of situation 1.

Finally for the purpose of processor core number used in minimum or minimum scheduler latency, target letter is set Number.The object function set as：

Further to verify the performance of dispatching algorithm of the present invention, for the three dimensional task of channel estimation balancing shown in Fig. 3 Figure example carries out the emulation of mapping scheduler, and the heterogeneous polynuclear framework of mapping is arranged to two pool of processors, in each pool of processor Comprising three processors, emulation needs the task image inputted as shown in figure 3, wherein, each subtask is represented with a square, just Two numbers in the block represent execution duration of the task in two pool of processors respectively, and T is duty cycle, the arrow between task Head represents the precedence relationship of two tasks, and the weights on arrow represent communication time.

When the target of solution is minimizes the processor number used in scheduling, the results are shown in Figure 4 for mapping scheduler, as a result Processor number used in showing is 4, solves used time 0.13s.And when the target of solution is minimizes scheduler latency, mapping Scheduling result is as shown in Figure 5, the results showed that scheduler latency 25 solves used time 0.14s.Therefore, according to simulation result, the present invention Dispatching algorithm ensure associated task priority constraint with communicate and duty cycle not overlap execution on the premise of, Processor core number used in can minimizing minimizes scheduler latency.

Claims (1)

1. A kind of 1. periodic associated task heterogeneous polynuclear mapping scheduler method based on MILP, which is characterized in that including,

   Task definition；Wherein, N number of task is given, task-set is expressed as T={ τ₁, τ₂..., τ_N, the cycle of each task is T_i, The first time of task performs the time as s_i, a length of b during the execution of task_mi；When two task τs_i→τ_jτ is expressed as when associated_i→ τ_j, and task τ_iWith task τ_jBetween communication time be e_ij；M pool of processor is given, pool of processor set representations are Φ={ ψ₁, ψ₂..., ψ_M, comprising P processor in each pool of processor, the processor collection in pool of processor is defined as P={ p₁, p₂..., p_P}；

   Set constraints；Wherein, the constraints of setting includes：

   Tasks carrying constraints：s_i≥0；

   Duty mapping constraints：Wherein binary variable map_imp={ 0,1 }, when map_impFor 1 when represent task τ_iIt is mapped on p-th of processor of m-th of pool of processor；

   Processor mappings constraint condition：

   ψ_m∈ Φ, p_p∈ P, mop_imp≤pro_mp

   <mrow> <mo>&amp;ForAll;</mo> <msub> <mi>&amp;psi;</mi> <mi>m</mi> </msub> <mo>&amp;Element;</mo> <mi>&amp;Phi;</mi> <mo>,</mo> <msub> <mi>p</mi> <mi>p</mi> </msub> <mo>&amp;Element;</mo> <mi>P</mi> <mo>,</mo> <msub> <mi>pro</mi> <mrow> <mi>m</mi> <mi>p</mi> </mrow> </msub> <mo>+</mo> <munder> <mo>&amp;Sigma;</mo> <mi>i</mi> </munder> <mrow> <mo>(</mo> <munder> <mo>&amp;Sigma;</mo> <mi>k</mi> </munder> <munder> <mo>&amp;Sigma;</mo> <mi>l</mi> </munder> <msub> <mi>map</mi> <mrow> <mi>i</mi> <mi>k</mi> <mi>l</mi> </mrow> </msub> <mo>-</mo> <msub> <mi>map</mi> <mrow> <mi>i</mi> <mi>m</mi> <mi>p</mi> </mrow> </msub> <mo>)</mo> </mrow> <mo>&amp;le;</mo> <mi>N</mi> </mrow>

   Wherein binary variable pro_mp={ 0,1 }, works as pro_mpFor 1 when represent that at least one task is mapped to m-th of processor On p-th of processor in pond；

   Two tasks carrying constraintss：

   τ_j∈ T, ψ_m, ψ_k∈ Φ, p_p, p_l∈P

   S.t.) i ≠ j, sep_ij+map_imp+map_jmp≤2

   S.t.) i ≠ j, k ≠ m or p ≠ l, sep_ij-map_imp-map_jkl≥-1

   b_mi-sep_ijZ≤(s_j-s_i)modg_{I, j}≤g_{I, j}-b_mj+sep_ijZ

   Wherein, binary variable sep_ij={ 0,1 }, works as sep_ijFor 1 when represent task τ_i, τ_jIt is mapped on different processors, And work as sep_ijFor 0 when represent task τ_i, τ_jIt is mapped in same processor；g_{I, j}For two task τs_i, τ_jThe highest common divisor in cycle Number, i.e. g_{I, j}=gcd (T_i, T_j)；Z is constant integer；

   Moreover, because linear programming needs to handle linear constraints, and (s_j-s_i)modg_{I, j}It is nonlinear, therefore makes (s_j-s_i)modg_{I, j}=(s_j-s_i)-q_{J, i}g_{I, j}, by (s_j-s_i)modg_{I, j}It linearizes wherein, q_{J, i}For integer variable and q_{J, i}Take Value scope is

   Associated task constraints：

   Situation 1, works as τ_i→τ_j, T_i=T_jWhen, then associated task constraints is：

   ψ_m∈ Φ, c_ij=e_ij×sep_ij, s_i+b_mi+c_ij≤s_j

   b_mi-sep_ijZ≤(s_j-s_i)-q_{J, i}g_{I, j}≤g_{I, j}-b_mj+sep_ijZ

   <mrow> <mfrac> <mrow> <mo>-</mo> <msub> <mi>T</mi> <mi>i</mi> </msub> <mo>+</mo> <msub> <mi>b</mi> <mrow> <mi>m</mi> <mi>i</mi> </mrow> </msub> </mrow> <msub> <mi>g</mi> <mrow> <mi>i</mi> <mo>,</mo> <mi>j</mi> </mrow> </msub> </mfrac> <mo>-</mo> <mn>1</mn> <mo>&lt;</mo> <msub> <mi>q</mi> <mrow> <mi>j</mi> <mo>,</mo> <mi>i</mi> </mrow> </msub> <mo>&amp;le;</mo> <mfrac> <mrow> <msub> <mi>T</mi> <mi>j</mi> </msub> <mo>-</mo> <msub> <mi>b</mi> <mrow> <mi>m</mi> <mi>j</mi> </mrow> </msub> </mrow> <msub> <mi>g</mi> <mrow> <mi>i</mi> <mo>,</mo> <mi>j</mi> </mrow> </msub> </mfrac> </mrow>

   Wherein, c_ijRepresent task τ_iWith task τ_jBetween communication overhead；

   Situation 2, works as τ_i→τ_j, aT_i=T_j,Then associated task constraints is：

   ψ_m∈Φs.t.)aT_i=T_j, a ∈ N⁺, s_j+b_mj-s_i≤T_i

   Situation 3, works as τ_i→τ_j, T_i=aT_j,When, the associated task constraints of associated task constraints and situation 1 Unanimously；

   Set object function；Wherein, object function is：

   Or min max (s_i+b_mi)。