CN108092661A - Phase discriminator and phase-locked loop circuit - Google Patents
Phase discriminator and phase-locked loop circuit Download PDFInfo
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- CN108092661A CN108092661A CN201810034873.2A CN201810034873A CN108092661A CN 108092661 A CN108092661 A CN 108092661A CN 201810034873 A CN201810034873 A CN 201810034873A CN 108092661 A CN108092661 A CN 108092661A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
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Abstract
The invention belongs to Phase Lock Technique fields, provide a kind of phase discriminator and phase-locked loop circuit.A kind of phase discriminator, including：Phase difference output circuit, the first input end and the second input terminal of the phase difference output circuit are respectively connected to sub-frequency clock signal and are connected with input clock signal, for the phase of the sub-frequency clock signal and the input clock signal and output phase difference signal；Delay circuit output for carrying out delay output processing to the sub-frequency clock signal, and exports postpones signal；Preliminary filling discharge signal output circuit, the input terminal of preliminary filling discharge signal accesses the input clock signal, and is connected with the output terminal of the delay circuit output, and the input terminal of preliminary filling discharge signal accesses the input clock signal, for exporting preliminary filling discharge signal.Circuit calibration accuracy is high, shortens locking time, meets the needs of modern communication systems are switched fast phase-locked loop frequency.
Description
Technical field
The invention belongs to Phase Lock Technique field more particularly to a kind of phase discriminators and phase-locked loop circuit.
Background technology
In order to improve spectrum utilization efficiency, modern wireless communication systems mostly employ frequency multiplexing technique, wireless receiving and dispatching
Channel used when machine carries out wireless communication can in real time be switched according to the real-time occupancy situation of channel, channel quality etc..Channel
Switching in real time, is realized by changing the output frequency of phaselocked loop.Phaselocked loop is carried to the upper and lower frequency changer circuit in transceiver
It is a core key module in transceiver, its performance can be greatly for the local carrier signal of programmable frequency
Influence the communication quality of communication system.
As shown in Figure 1, the basic module of traditional phaselocked loop includes voltage-controlled oscillator (Voltage Control
Oscillator, VCO), phase discriminator (Phase Detector, PD) and loop filter (Loop Filter, LF).Phaselocked loop
Be the output signal generated by voltage-controlled oscillator is realized with an input reference signal in phase and frequency it is synchronous
Circuit.If the phase difference between output signal and the input reference signal of voltage-controlled oscillator changes, in phaselocked loop
There are a negative feedback control mechanismses for inside to adjust the output of oscillator so that the two phase difference reduces, and is finally reached lock
Determine state.Phase discriminator is an important component in phaselocked loop, it can when the frequency or phase hit of input signal,
Judge input reference signal and export the phase difference of signal, so as to which output signal be promoted quickly to follow the variation of input signal.
For phase discriminator after phase demodulation is carried out to clock signal, phase-locked loop systems adjust the output of oscillator, phaselocked loop just for the phase difference
System can be only achieved lock-out state by frequency calibration many times from starting to fully locked, calibration accuracy is low, work efficiency very
It is low.
Therefore, it is low there are calibration accuracy in traditional technical solution, the problem of work efficiency is very low.
The content of the invention
It is an object of the invention to provide a kind of phase discriminator and phase-locked loop circuits, it is intended to solve to deposit in traditional technical solution
Calibration accuracy it is low, the problem of work efficiency is very low.
A kind of phase discriminator, the phase discriminator include：
Phase difference output circuit, the input terminal of the phase difference output circuit respectively with sub-frequency clock signal and input clock
Signal connects, for the phase of the sub-frequency clock signal and the input clock signal and output phase difference signal；
Delay circuit output for carrying out delay output processing to the sub-frequency clock signal, and exports postpones signal；
Preliminary filling discharge signal output circuit, respectively with the input clock signal and the output terminal of the delay circuit output
Connection, the preliminary filling discharge signal output circuit are used to export preliminary filling discharge signal.
In addition, additionally providing a kind of phase-locked loop circuit, the phase-locked loop circuit includes：
Above-mentioned phase discriminator；
Charge pump, the charge pump is according to the phase signal and the postpones signal output current, to loop filtering
Device carries out charge and discharge and pre- charge and discharge；
Loop filter is connected with the charge pump and the phase discriminator, output phase control signal；
Voltage-controlled oscillator is connected with the loop filter, is controlled according to the phase control signal and is exported mesh
Mark phase signal；
Frequency divider is connected between the voltage-controlled oscillator and the phase discriminator, and the target phase signal is anti-
It feeds the phase discriminator.
Above-mentioned phase discriminator and phase-locked loop circuit, by the phase difference output circuit sub-frequency clock signal and described
Input clock signal and the phase signal for exporting the sub-frequency clock signal and the input clock signal, by postponing to export
Circuit carries out the sub-frequency clock signal delay output and handles and export postpones signal, passes through preliminary filling discharge signal output circuit
Preliminary filling discharge signal is exported, according to phase signal, postpones signal and preliminary filling discharge signal the charge pump is controlled to filter loop
The charge and discharge of ripple device carry out phase adjusted to input clock signal so as to which voltage-controlled oscillator be controlled to adjust, and export target
Phase signal realizes the Fast synchronization of sub-frequency clock signal and input clock signal, and circuit calibration accuracy is high, when shortening locking
Between, meet the needs of modern communication systems are switched fast phase-locked loop frequency.
Description of the drawings
Fig. 1 is the structure diagram of traditional phaselocked loop；
Fig. 2 is the structure diagram for the phase-locked loop circuit that present pre-ferred embodiments provide；
Fig. 3 is the exemplary circuit schematic diagram of phase discriminator in phase-locked loop circuit shown in Fig. 2；
Fig. 4 is the exemplary circuit schematic diagram of charge pump in phase-locked loop circuit shown in Fig. 2；
Fig. 5 is the exemplary circuit schematic diagram of phase-locked loop circuit loop filter shown in Fig. 2；
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, it is right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 2 shows the structure diagram for the phase-locked loop circuit that present pre-ferred embodiments provide, for convenience of description, only
Show part related to the present embodiment, details are as follows：
An embodiment of the present invention provides a kind of phase-locked loop circuit, which includes：Phase discriminator 10, charge pump 20, loop
Wave filter 30, voltage-controlled oscillator 40 and frequency divider 50, the input clock signal FREF processing to receiving, make the letter
Sub-frequency clock signal FDIV Phase synchronizations number with the output of phaselocked loop.
Wherein, phase discriminator 10 is used for the phase signal and phase of input clock signal FREF and sub-frequency clock signal FDIV
Adjusting control signal, to control charge and discharge of the charge pump 20 to loop filter 30
As shown in figure 3, phase discriminator 10 includes phase difference output circuit 101, delay circuit output 102 and preliminary filling discharge signal
Output circuit 103.
The first input end of phase difference output circuit 101 and the second input terminal input sub-frequency clock signal FDIV and defeated respectively
Enter clock signal FREF connections, compare the phase signal of simultaneously output frequency division clock signal FDIV and input clock signal FREF,
Phase signal includes the first phase difference signal UP of difference output and second phase difference signal UPB, phase difference output circuit 101
It is corresponding that there is the first output terminal and second output terminal, the first output terminal of phase difference output circuit 101 and phase difference output circuit
101 second output terminal is respectively used to output first phase difference signal UP and second phase difference signal UPB.Phase difference output circuit
101 include the first d type flip flop DFF1, the second d type flip flop DFF2, the first AND gate circuit AND1 and the first differential converter S2D1；
First d type flip flop DFF1 is connected with input clock signal FREF, for receiving input clock signal FREF, the first differential converter
S2D1 is connected to the output terminal of the first d type flip flop DFF1, and the signal for the first d type flip flop DFF1 to be exported is converted to difference letter
Number and export；Second d type flip flop DFF2 is connected with sub-frequency clock signal FDIV, for receiving sub-frequency clock signal FDIV, first
The first input end of AND gate circuit AND1 is connected with the output terminal of the first d type flip flop DFF1, and the second of the first AND gate circuit AND1
Input terminal is connected with the output terminal of the second d type flip flop DFF2, the output terminal of the first AND gate circuit AND1 respectively with the first trigger
Reset terminal and the second trigger reset terminal connection, for the reset of the first d type flip flop DFF1 and the second d type flip flop DFF2.
Wherein, when the output of the first d type flip flop DFF1 and the second d type flip flop DFF2 are all " 1 ", the first d type flip flop DFF1 and the 2nd D
Trigger DFF2 resets simultaneously, the output terminal output frequency division clock signal FDIV and input clock signal of the first d type flip flop DFF1
The phase signal is converted to the first phase difference signal UP and the second phase of difference by the phase signal of FREF, differential converter
Potentiometer signal UPB.
Delay circuit output 102 for carrying out delay output processing to sub-frequency clock signal FDIV, and exports delay letter
Number, postpones signal includes the first postpones signal HOLDP and the second postpones signal HODLM delay circuit outputs 102 of difference output
With the first output terminal and second output terminal, the first output terminal of delay circuit output 102 and the second of delay circuit output 102
Output terminal is respectively used to output the first postpones signal HOLDP and the second postpones signal HODLM.Delay circuit output 102 includes the
One delayer DU1, the second delayer DU2,3d flip-flop DFF3 and the second differential converter S2D2；First delayer DU1's
Input terminal is connected with sub-frequency clock signal FDIV, receive the output terminal of sub-frequency clock signal FDIV, the first delayer DU1 respectively with
The input terminal of second delayer DU2 and 3d flip-flop DFF3 connections, the output terminal and 3d flip-flop of the second delayer DU2
The reset terminal connection of DFF3, for the reset of 3d flip-flop DFF3, the second differential converter S2D2 is connected to the 3rd D triggerings
The output terminal of device DFF3, for 3d flip-flop DFF3 output signals to be converted to differential signal and are exported.Wherein, during frequency dividing
Clock signal FDIV is after the first delayer DU1 delays, by 3d flip-flop DFF3, with passing through the first delayer DU1 simultaneously
The sub-frequency clock signal FDIV being delayed twice with the second delayer DU2 resets 3d flip-flop DFF3, obtains one narrow prolong
Slow signal, the second differential converter S2D2 is again by this postpones signal by single-ended the first postpones signal HOLDP for being converted into difference
With the second postpones signal HODLM.
Preliminary filling discharge signal output circuit 103, is connected with the second output terminal of delay circuit output 102, pre- charge and discharge letter
Number output circuit 103 is for exporting preliminary filling discharge control signal.Preliminary filling discharge signal output circuit 103 includes the first phase inverter
INV1, the second phase inverter INV2, four d flip-flop DFF4, the 5th d type flip flop, the second AND gate circuit AND2, the 3rd phase inverter
INV3 and the 4th phase inverter INV4；The input terminal input input clock signal FREF of first phase inverter INV1, the second phase inverter
INV2 is series between the output terminal of the first phase inverter INV1 and four d flip-flop DFF4, the output terminal of four d flip-flop DFF4
It is connected to the second input terminal of the second AND gate circuit AND2, the second output of the 5th d type flip flop DFF5 and delay circuit output 102
End connection, the output terminal for accessing the second postpones signal HODLM, the 5th d type flip flop DFF5 pass through the 3rd phase inverter that is connected in series
INV3 and the 4th phase inverter INV4 outputs, the output terminal of the second AND gate circuit AND2 connect the reset terminal of the 5th d type flip flop DFF5.
Wherein, preliminary filling discharge control signal PRECHG is to 30 precharging signal of loop filter, is believed in the second postpones signal HOLDM
It is " 1 " during number rising edge, and is reset to " 0 " when input clock signal FREF rising edges arrive.
As shown in figure 4, charge pump 20 carries out loop filter 30 according to phase signal and postpones signal output current
Charge and discharge and pre- charge and discharge, charge pump 20 include：First current source I1, the second current source I2, first switch K1, second switch
K2, the 3rd switch K3 and metal-oxide-semiconductor Q1；
The cathode of first current source I1 is connected with the cathode of the second current source I2, and first switch K1 is connected to the first current source
Between the source electrode of the anode metal-oxide-semiconductor Q1 of I1, the grid of metal-oxide-semiconductor Q1 is connected with the drain electrode of metal-oxide-semiconductor Q1, and second switch K2 and the 3rd is opened
K3 is closed to be sequentially connected in series between the drain electrode of the anode and metal-oxide-semiconductor Q1 of the second current source I2, the switches of second switch K2 and the 3rd K3's
Public connecting end is connected as the output terminal of charge pump 20 with loop filter 30；Wherein, phase signal control first switch
The open and close of K1 and second switch K2, the open and close of the 3rd switch K3 of preliminary filling discharge signal PRECHG controls.Specifically
, first phase difference signal UP and second phase difference signal UPB are respectively used to control control first switch K1 and second switch K2,
When control signal is " 1 ", first switch, second switch and the 3rd switch K3 are closed, and when control signal is " 0 ", first opens
It closes K1, second switch K2 and the 3rd switch K3 is disconnected, with this electric energy of charge pump 20 is controlled to export.
As shown in figure 5, loop filter 30 is connected with charge pump 20 and phase discriminator 10, output phase control signal；Loop
Wave filter 30 includes the 4th switch K4, the first capacitance C1, the second capacitance C2, the 3rd capacitance C3, the 4th capacitance C4, first resistor R1
With second resistance R2；4th switch K4, first resistor R1 and second resistance R1 are series at the output terminal of charge pump 20 and voltage control
Between oscillator 40 processed, the first capacitance C1 is connected between the output terminal and ground of charge pump 20, and the second capacitance C2 is connected to the 4th
Between the public connecting end and ground that switch K4 and first resistor R1, the 3rd capacitance C3 is connected to first resistor R1 and second resistance
Between R2 public connecting ends and ground, the 4th capacitance C4 is connected between voltage-controlled oscillator 40 and ground；Wherein, postpones signal control
Make the open and close of the 4th switch K4.Specifically, the first postpones signal HOLDP and the second postpones signal HODLM while difference
The switch of control the 4th to carry out charge and discharge to the first capacitance C1 of loop filter, and pass through the second capacitance C2, the 3rd capacitance
The RC filter circuit output phase control signal VCTRL that C3, the 4th capacitance C4, first resistor R1 and second resistance R2 are formed, with
Control the output of voltage-controlled oscillator 40.
Voltage-controlled oscillator 40 is connected with loop filter 30, is controlled according to phase control signal VCTRL and is exported mesh
Mark phase signal；Frequency divider 50 is connected between voltage-controlled oscillator 40 and phase discriminator 10, and target phase signal is fed back to
Phase discriminator 10.
Above-mentioned phase-locked loop circuit compares sub-frequency clock signal and input clock signal and defeated by phase difference output circuit
Go out the phase signal of sub-frequency clock signal and input clock signal, sub-frequency clock signal is prolonged by delay circuit output
Output late handles and exports postpones signal, preliminary filling discharge signal is exported by preliminary filling discharge signal output circuit, according to phase difference
The charge and discharge of signal, postpones signal and preliminary filling discharge signal control charge pump to loop filter, so as to which voltage control be controlled to shake
It swings device to adjust to input clock signal progress phase adjusted, and exports target phase signal, realize sub-frequency clock signal and input
The Fast synchronization of clock signal, circuit calibration accuracy is high, shortens locking time, meets modern communication systems to phase-locked loop frequency
The demand being switched fast.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, it is all the present invention spirit and
All any modification, equivalent and improvement made within principle etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of phase discriminator, which is characterized in that the phase discriminator includes：
Phase difference output circuit, the first input end and the second input terminal of the phase difference output circuit are respectively connected to frequency-dividing clock
Signal is connected with input clock signal, for the phase of the sub-frequency clock signal and the input clock signal and output
Phase signal；
Delay circuit output for carrying out delay output processing to the sub-frequency clock signal, and exports postpones signal；
Preliminary filling discharge signal output circuit, the input terminal of preliminary filling discharge signal accesses the input clock signal, and prolongs with described
The output terminal connection of slow output circuit, the input terminal of preliminary filling discharge signal accesses the input clock signal, for exporting preliminary filling
Discharge signal.
2. phase discriminator as described in claim 1, which is characterized in that the phase difference output circuit has the first output terminal and the
Two output terminals, the phase signal include the first phase difference signal of difference output and second phase difference signal, the phase
The second output terminal of first output terminal of poor output circuit and the phase difference output circuit is respectively used to export first phase
Potentiometer signal and the second phase difference signal.
3. phase discriminator as described in claim 1, which is characterized in that the delay circuit output has the first output terminal and second
Output terminal, the postpones signal include the first postpones signal and the second postpones signal of difference output, the delay circuit output
The first output terminal and the second output terminal of the delay circuit output be respectively used to export first postpones signal and described
Second postpones signal.
4. phase discriminator as claimed in claim 3, which is characterized in that the triggering end of the preliminary filling discharge signal output circuit and institute
State the second output terminal connection of delay circuit output.
5. phase discriminator as described in claim 1, which is characterized in that the phase difference output circuit includes the first d type flip flop, the
2-D trigger, the first AND gate circuit and the first differential converter；
First d type flip flop is connected with the input clock signal, and for receiving the input clock signal, described first is poor
Converter is divided to be connected to the output terminal of first d type flip flop, the signal for first d type flip flop to be exported is converted to difference
Sub-signal simultaneously exports；
Second d type flip flop is connected with the sub-frequency clock signal, for receiving the sub-frequency clock signal, described first with
The first input end of gate circuit is connected with the output terminal of first d type flip flop, the second input terminal of first AND gate circuit
Be connected with the output terminal of second d type flip flop, the output terminal of first AND gate circuit respectively with first d type flip flop
Reset terminal is connected with the reset terminal of second d type flip flop, for answering for first d type flip flop and second d type flip flop
Position.
6. phase discriminator as described in claim 1, which is characterized in that the delay circuit output includes the first delayer, second
Delayer, 3d flip-flop and the second differential converter；
The input terminal of first delayer is connected with the sub-frequency clock signal, receives the sub-frequency clock signal, and described
The output terminal of one delayer is connected respectively with the input terminal of second delayer and the 3d flip-flop, and described second prolongs
When device output terminal be connected with the reset terminal of the 3d flip-flop, for the reset of the 3d flip-flop, described second
Differential converter is connected to the output terminal of the 3d flip-flop, for 3d flip-flop output signal to be converted to difference
Sub-signal simultaneously exports.
7. phase discriminator as described in claim 1, which is characterized in that the preliminary filling discharge signal output circuit includes the first reverse phase
Device, the second phase inverter, four d flip-flop, the 5th d type flip flop, the second AND gate circuit, the 3rd phase inverter and the 4th phase inverter；
The input terminal of first phase inverter is connected with the input clock signal, and second inverter series are in described first
Between the output terminal of phase inverter and the four d flip-flop, the output terminal of the four d flip-flop is connected to described second and door
Second input terminal of circuit, the 5th d type flip flop are connected with the output terminal of the delay circuit output, the 5th D triggerings
The output terminal of device is exported by the 3rd phase inverter being connected in series and the 4th phase inverter, second AND gate circuit
Output terminal connects the reset terminal of the 5th d type flip flop.
8. a kind of phase-locked loop circuit, which is characterized in that the phase-locked loop circuit includes：
Phase discriminator as described in any one in Claims 1-4；
Charge pump, the charge pump according to the phase signal and the postpones signal output current, to loop filter into
Row charge and discharge and pre- charge and discharge；
Loop filter is connected with the charge pump and the phase discriminator, output phase control signal；
Voltage-controlled oscillator is connected with the loop filter, is controlled according to the phase control signal and is exported target phase
Position signal；
Frequency divider is connected between the voltage-controlled oscillator and the phase discriminator, and the target phase signal is fed back to
The phase discriminator.
9. phase-locked loop circuit as claimed in claim 8, which is characterized in that the charge pump includes：First current source, the second electricity
Stream source, first switch, second switch, third switch and metal-oxide-semiconductor；
The cathode of first current source is connected with the cathode of second current source, and the first switch is connected to described first
Between the source electrode of metal-oxide-semiconductor described in the anode of current source, the grid of the metal-oxide-semiconductor is connected with the drain electrode of the metal-oxide-semiconductor, and described second
Switch and the 3rd switch are sequentially connected in series between the drain electrode of the anode and the metal-oxide-semiconductor of second current source, and described the
The public connecting end of two switches and the 3rd switch is connected as the output terminal of the charge pump with the loop filter；
Wherein, the phase signal controls the open and close of the first switch and the second switch, the pre- charge and discharge
The open and close of electric signal control the 3rd switch.
10. phase-locked loop circuit as claimed in claim 8, which is characterized in that the loop filter includes the 4th switch, first
Capacitance, the second capacitance, the 3rd capacitance, the 4th capacitance, first resistor and second resistance；
4th switch, first resistor and second resistance be series at the charge pump output terminal and voltage-controlled oscillator it
Between, first capacitance connection between the output terminal and ground of the charge pump, in the described 4th open by second capacitance connection
It closes between the public connecting end and ground of the first resistor, the 3rd capacitance connection is in the first resistor and described second
Between the public connecting end and ground of resistance, the 4th capacitance connection is between the voltage-controlled oscillator and ground；
Wherein, the postpones signal is used for the open and close of the described 4th switch.
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| CN201810034873.2A CN108092661B (en) | 2018-01-15 | 2018-01-15 | Phase discriminator and phase-locked loop circuit |
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| CN201810034873.2A CN108092661B (en) | 2018-01-15 | 2018-01-15 | Phase discriminator and phase-locked loop circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110475045A (en) * | 2019-09-11 | 2019-11-19 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Ratio Phase-Locked Synchronous electronic device |
| CN110957659A (en) * | 2019-11-20 | 2020-04-03 | 邹虚 | Movable transformer substation |
| CN111835344A (en) * | 2020-07-29 | 2020-10-27 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and terminal |
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| CN110957659A (en) * | 2019-11-20 | 2020-04-03 | 邹虚 | Movable transformer substation |
| CN111835344A (en) * | 2020-07-29 | 2020-10-27 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and terminal |
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