CN108091554B - Shallow PN junction diffusion technology - Google Patents
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 96
- 238000005516 engineering process Methods 0.000 title description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 81
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 36
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 6
- 239000011574 phosphorus Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 25
- 239000010453 quartz Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 235000012431 wafers Nutrition 0.000 claims description 19
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000007787 solid Substances 0.000 claims description 6
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 230000003595 spectral effect Effects 0.000 claims description 2
- 230000001105 regulatory effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 13
- 238000013461 design Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000004401 flow injection analysis Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
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Abstract
The present invention relates to a shallow PN junction formation technique, namely a shallow PN junction diffusion technique, in a semiconductor process, which combines conventional equipment and processes to produce a thin silicon dioxide barrier layer with a reduced thickness, followed by diffusion of boron, phosphorus, etc. to form a shallow PN junction.
Description
Technical Field
The invention relates to a thermal diffusion doping technology in a semiconductor process, in particular to a shallow PN junction diffusion technology in the semiconductor process.
Background
As integrated electronics technology continues to advance, the feature size of chips continues to decrease, and thus, there are several challenges, one of which is the doping of shallow PN junctions. Such as source/drain regions in deep submicron mos devices, particularly the junction depth of the source/drain extensions, is required to be continuously reduced with the reduction of the gate length to suppress the gradually increasing short channel effect, while the corresponding surface concentration is increased to reduce the source/drain series resistance to increase the circuit speed. As specified in the international association for Semiconductors (SIA) ultra-large scale integration (Roadmap): the junction depth of the source/drain extension region in the MOS device with the technical level of 130nm and the characteristic dimension of 100nm is 30-50nm, otherwise, the MOS device cannot work normally. According to the principle of equal scaling down, the ultra-shallow junction depth of 0.18 μm technology is about 54 +/-18 nm, the 0.1 μm technology is 30 +/-10 nm, the technological requirements on the source/drain extension regions are more strict along with the reduction of the characteristic gate length, and how to prepare the source/drain extension regions with shallow junction depth becomes an important problem in the technological process. In addition to integrated circuit devices, other bipolar and MOS discrete devices have different special performance requirements, and how to prepare shallow PN junctions (hereinafter referred to as shallow junctions, and PN junction depth x) with a shallow junction depth is requiredpnLess than 0.1 μm) has become an important issue in semiconductor processing technology.
Disclosure of Invention
The task of the invention is to provide a shallow PN junction forming technology, namely a shallow PN junction diffusion technology, in a semiconductor process, and the task of the invention is completed by the following technical scheme, wherein the shallow PN junction diffusion technology is combined with conventional equipment and processes, a thin silicon dioxide blocking layer with a certain weight and thickness is prepared, and then boron, phosphorus and the like are diffused to form the shallow PN junction, and the shallow PN junction diffusion technology is concretely as follows:
(a) designing the thickness x of the silicon dioxide barrier layer with shallow PN junction depthmin,
In the formula DSiO2The diffusion coefficient of the diffused impurities in the silicon dioxide is t, the thermal diffusion time at the diffusion temperature is t, and the thermal diffusion time for the subsequent formation of shallow junctions is t plus delta t, namely
The diffusion time t in the formula is added with the diffusion time delta t needed for ensuring the shallow junction depth, and the delta t is approximately equal to t (x)pn/xmin)(DSiO2/DSi) In the formula xpnIs shallow PN junction depth, DSiO2Diffusion coefficient of impurities in silicon dioxide for diffusion at diffusion temperature, DSiDiffusion coefficient of impurity in silicon for diffusion at diffusion temperature;
(b) firstly, a layer with the thickness x required by (a) is formed on the silicon wafer to form the shallow PN junctionminThe silicon dioxide layer and solid diffusion impurity source sheets (namely Si sheet and BN sheet) are alternately arranged on a quartz boat, and are put into a quartz tube furnace mouth to be communicated with N2Prebaking for 30 minutes, pushing into a constant temperature area of a diffusion furnace, and introducing N in a vertical flow mode at constant temperature2：O2= 8.8: 1.8 atmosphere, adding a quartz diffusion plate at the gas inlet end of a quartz tube to avoid gas jet, enabling the gas to uniformly enter a diffusion area, routinely placing 1-2 dummy wafers at two ends of a quartz boat, and estimating the gas flow according to the reference Re ═ D-mu rho)/w ≤ 15, wherein: re is a Reynolds coefficient; d is the diameter of the quartz tube; μ is the average flow rate of the gas stream; ρ is the gas density; w is the gas viscosity coefficient.
Compared with the prior art: namely, the junction depth is difficult to form less than 0.1 μm by using the traditional thermal diffusion technology after photoetching an oxide layer window, and the surface is a shallow junction with high doping concentration; the use of advanced ion implantation doping (PD) and laser induced doping and rapid gas phase doping is not only difficult, but also complicated in equipment and process. The invention provides a new technology for forming shallow junctions by utilizing a silicon dioxide barrier layer with a proper thickness to carry out thermal diffusion on impurities such as boron, phosphorus and the like. The invention provides and designs a shallow junction diffusion process technology of adding a barrier layer film by exploring a diffusion theory mechanism and combining multiple experimental practices, is easy to operate in process and high in productivity, and optimizes the process technology for forming a shallow PN junction in a device. Compared with the ion implantation doping technology, the laser-induced doping technology and the rapid gas-phase diffusion technology, the method has the advantages of only needing to increase one-time high-temperature oxidation process, simple equipment and process, short high-temperature time, less ion contamination, good lattice integrity, wide applicability and the like. The invention utilizes a thin silicon dioxide barrier layer to carry out thermal diffusion of impurities such as boron, phosphorus and the like to form a novel technology, and is characterized in that conventional equipment and processes are combined, the design thought of solid thermal diffusion theory estimation and a large number of process tests is carried out, and an improved thermal diffusion technology is adopted to be used in a semiconductor process to prepare a shallow PN junction diffusion layer, so that the process problem that the shallow PN junction is difficult to form by using a direct thermal diffusion technology after a pattern window is photoetched is solved.
The invention has the following advantages:
1. shallow junction P suitable for all thermal diffusion methods+N junction or N+And a P junction layer.
2. The invention has the advantages of easy operation, large chip loading amount, high yield, high production efficiency and low cost.
3. The prepared shallow junction has good repeatability. The method can be applied to the CMOS integrated circuit based on the bipolar process, other bipolar semiconductor integrated circuits needing shallow PN junctions and discrete device process lines, and is flexible in application.
Drawings
FIG. 1 is an oxidation furnace plant;
FIG. 2 is a diffusion furnace apparatus for use with the present invention.
Detailed Description
The invention is further illustrated by the following specific examples in connection with the accompanying drawings. (but not limiting to the invention).
The invention combines conventional equipment and process, adopts a thermal oxidation method used on a general standard process line or other conventional process methods through the design thinking of solid-state thermal diffusion theoretical estimation and a large number of process tests, firstly prepares a thin silicon dioxide barrier layer with a certain thickness, and then diffuses boron, phosphorus and the like to form a shallow PN junction (P) to ensure that the thin silicon dioxide barrier layer has a certain thickness+N junction or N+P). The method solves the process problem that the shallow PN junction is difficult to form by using a direct thermal diffusion process technology after a pattern window is photoetched, and the method is successfully applied to a 4-inch semiconductor process line.
The diffusion technology of the invention is concretely as follows:
1) ensuring the diffusion time to be t plus delta t in the process condition of the thickness of the oxide layer slightly larger than the depth of the shallow junction, namely the middle thermal diffusion time t plus
The diffusion time delta t required by shallow junction depth is ensured. The empirical formula of the invention is obtained according to theoretical calculation and practical experience: Δ t ≈ t (x)pn/xmin)(DSiO2/DSi) (in the formula, DSiO2Diffusion coefficient of impurities in silicon dioxide, DSiDiffusion coefficient, x, in silicon for diffusing impuritiespnShallow PN junction depths).
2) When the silicon wafer (namely the semi-finished silicon wafer) of the silicon oxide barrier layer which meets the thickness requirement is prepared, the silicon wafer and the flaky impurity source are arranged in a quartz boat at intervals and then are placed into a quartz tube furnace mouth to be communicated with N2Prebaking for 30 minutes, and introducing N in a vertical flow mode at constant temperature2：O2= 8.8: 1.8 atmosphere, in order to improve the uniformity of the gas flow, a quartz diffuser plate is added at the gas inlet end of the quartz tube to avoid the gas flow injection, the gas flow can uniformly enter the diffusion area, and in addition, 1 to 2 dummy wafers (namely, reusable silicon wafers without positive wafers) are routinely placed at the two ends of the quartz boat. The gas flow rate is estimated with reference to Re ═ D- μ ρ)/w ≦ 15, where: re is a Reynolds coefficient; d is quartzThe diameter of the tube; μ is the average flow rate of the gas stream; ρ is the gas density; and w is the gas viscosity coefficient (the data can be specifically referred to relevant semiconductor process manuals). Otherwise, general process conditions and process parameters are used (this is common general semiconductor process knowledge and is omitted here).
According to the above points, it can become a shallow PN junction diffusion technology that can be popularized and applied.
The invention is mainly based on the principle that the diffusion coefficient of the common silicon semiconductor doped impurities in silicon dioxide is far smaller than that in silicon, the impurity segregation phenomenon exists on the interface of silicon and silicon dioxide, and smoother high-concentration impurity distribution does not exist on the surface, namely, the doped layer which is similar to the exponential function impurity concentration distribution and has small junction depth can be obtained on the silicon surface.
The diffusion technology is improved according to the above thought, as long as the design can ensure that the thickness x of the silicon dioxide barrier layer with shallow junction depth is obtainedmin, And is calculated according to the following formula： 
(in the formula, DSiO2Diffusion coefficient of diffused impurities in silicon dioxide, t thermal diffusion time at diffusion temperature), and thermal diffusion time of the subsequent shallow junction formation is t +. DELTA.t. Namely, it is
T in the formula is added with the diffusion time delta t needed for ensuring the shallow junction depth. Obtaining an empirical formula according to theoretical calculation and practical experience: Δ t ≈ t (x)pn/xmin)(DSiO2/DSi) (in the formula DSiO2Diffusion coefficient of impurities in silicon dioxide, DSiDiffusion coefficient of impurity in silicon, xpnJunction depth of shallow junction).
The schematic diagram of the thermal oxidation and diffusion system equipment is shown in the attached figure 1: the diffusion furnace controls the temperature in three zones with the precision of +/-0.5 ℃. The thermal diffusion process aims at achieving a predetermined impurity concentration distribution through high-temperature heat treatment, and is characterized by directly measurable sheet resistance and junction depth, and for a certain diffusion method, the required sheet resistance and junction depth are mainly determined by the diffusion process conditions: diffusion temperature, time and protective atmosphere and flow. After the process conditions are determined by theoretical evaluation and a large number of process tests, strict control is applied to the batch production.
In the implementation of the technology of the invention, a process (namely, a conventional thermal oxidation process) for oxidizing the surface of a silicon wafer by introducing gas containing high-purity oxygen into an oxidation furnace by using the silicon wafer shown in figure 1 in a high temperature is used for generating a layer of silicon dioxide layer with the thickness of x on a wafer (semi-finished silicon wafer) needing to generate shallow junctionsminE.g., 180nm, (is omitted from the conventional process). Boron diffusion employs gas-solid diffusion (i.e., thermal diffusion of impurities from a solid impurity diffusion source such as boron nitride or the like under a high purity inert gas atmosphere, see general semiconductor processing manual for details), as shown in fig. 2.
The plate source adopts commercially available spectral pure boron nitride (or boron microcrystalline glass PWB), namely BN plate in the figure, the plates are alternately arranged in a quartz boat and put into a quartz tube furnace mouth for introducing N2Prebaking for 30 minutes, and adjusting the furnace temperature to 350 ℃. After prebaking, the furnace is slowly pushed into a constant-temperature area in 3 minutes, and N is introduced in a vertical flow mode2Then raising the temperature at the rate of 5 ℃/min to reach the required constant temperature (such as 1180 ℃) for constant temperature 65min (namely t +. DELTA.t), then reducing the temperature at the rate of 5 ℃/min to 350 ℃, and then pushing out the quartz boat in 3 minutes. Placing the silicon wafer in a 10: 1, the shallow junction diffusion can be completed by rinsing with HF solution, and the surface concentration of the shallow junction diffusion is stabilized at 1017/cm3Nearby, the junction depth is more than or equal to 60nm, and the relative deviation is less than 5%; the relative deviation between the same furnace plate is less than 5 percent, and the relative deviation between different batches is less than 10 percent. (from the above, it can be seen that a shallow PN junction layer having such a surface boron impurity concentration is difficult to achieve with the conventional impurity thermal diffusion method.) satisfies the process variation and reproducibility requirements of mass production line products. The technology is stably applied to the discrete device process line of the unit mass production.
Claims (3)
1. A shallow PN junction diffusion method is characterized in that the shallow PN junction diffusion method is combined with conventional equipment and processes, a thin silicon dioxide barrier layer is prepared firstly, and then boron and phosphorus are diffused to form a shallow PN junction;
the shallow PN junction diffusion method specifically comprises the following steps:
(a) designing the thickness x of the silicon dioxide barrier layer with shallow junction depthmin,
In the formula DSiO2The diffusion coefficient of the diffused impurities in the silicon dioxide is t, the thermal diffusion time at the diffusion temperature is t, and the thermal diffusion time for the subsequent formation of shallow junctions is t plus delta t, namely
The diffusion time t in the formula is added with the diffusion time delta t needed for ensuring the shallow junction depth, and the delta t is approximately equal to t (x)pn/xmin)(DSiO2/DSi) In the formula xpnIs shallow PN junction depth, DSiO2Diffusion coefficient of impurities in silicon dioxide for diffusion at diffusion temperature, DSiDiffusion coefficient of impurity in silicon for diffusion at diffusion temperature;
(b) forming a layer with thickness x required by (a) on the silicon wafer to form shallow junctionminThe silicon dioxide layer and the solid diffusion impurity source are arranged on a quartz boat in a mutual interval, and a Si sheet and a BN sheet are arranged in a quartz tube furnace mouth and are communicated with N2Prebaking for 30 minutes, pushing into a constant temperature area of a diffusion furnace, and introducing N in a vertical flow mode at constant temperature2：O2= 8.8: 1.8 atmosphere, adding a quartz diffusion plate at the gas inlet end of a quartz tube to avoid gas jet, enabling the gas to uniformly enter a diffusion area, routinely placing 1-2 dummy wafers at two ends of a quartz boat, and estimating the gas flow according to the reference Re ═ D-mu rho)/w ≤ 15, wherein: re is a Reynolds coefficient; d is the diameter of the quartz tube; μ is the average flow rate of the gas stream; ρ is the gas density; w is the gas viscosity coefficient.
2. The shallow PN junction diffusion method of claim 1, wherein the temperature control accuracy of the diffusion furnace in the diffusion system equipment is ± 0.5 ℃.
3. The shallow PN junction diffusion method of claim 1, wherein said shallow PN junction diffusion methodIntroducing high-purity oxygen-containing gas into an oxidation furnace by using a silicon wafer to oxidize the surface of the silicon wafer at high temperature, and generating a layer of silicon dioxide layer with the thickness of x on the wafer needing to generate shallow junctionsminThe impurity diffusion adopts gas-solid diffusion, the sheet source adopts the spectral pure boron nitride sold in the market, the sheets are alternately arranged in a quartz boat and put into a quartz tube furnace mouth to be communicated with N2Prebaking for 30 min, regulating furnace temp. to 350 deg.C, slowly pushing into constant-temp. zone in furnace for 3 min after prebaking, introducing N in vertical flow mode2Then raising the temperature at the rate of 5 ℃/min to reach the required constant temperature and keeping the temperature t + delta t constant, then lowering the temperature at the rate of 5 ℃/min to 350 ℃, pushing out the quartz boat in 3 minutes, placing the silicon wafer in a temperature range of 10: 1, rinsing with HF solution to complete shallow junction diffusion: except the surface impurity concentration, the junction depth is less than or equal to 100nm, and the relative deviation is less than 5 percent; the relative deviation between the same furnace plate is less than 5 percent, and the relative deviation between different batches is less than 10 percent.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277445A (en) * | 1999-03-23 | 2000-10-06 | Okaya Electric Ind Co Ltd | Adjusting method for surface layer resistance value of semiconductor substrate |
| CN102486997A (en) * | 2010-12-01 | 2012-06-06 | 天威新能源控股有限公司 | Method for preparing PN (Positive-Negative) junctions by utilizing solid-state phosphorus source for assisting dispersion of phosphorus source gas |
| CN102637778A (en) * | 2012-05-10 | 2012-08-15 | 英利能源（中国）有限公司 | PN junction diffusion method |
| CN104393107A (en) * | 2014-10-27 | 2015-03-04 | 中国电子科技集团公司第四十八研究所 | High-sheet resistance crystalline silicon cell low-voltage diffusion process |
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| JP4244549B2 (en) * | 2001-11-13 | 2009-03-25 | トヨタ自動車株式会社 | Photoelectric conversion element and manufacturing method thereof |
| CN103367551B (en) * | 2013-08-06 | 2015-08-19 | 中利腾晖光伏科技有限公司 | A kind of diffusion technology of crystal silicon solar energy battery |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000277445A (en) * | 1999-03-23 | 2000-10-06 | Okaya Electric Ind Co Ltd | Adjusting method for surface layer resistance value of semiconductor substrate |
| CN102486997A (en) * | 2010-12-01 | 2012-06-06 | 天威新能源控股有限公司 | Method for preparing PN (Positive-Negative) junctions by utilizing solid-state phosphorus source for assisting dispersion of phosphorus source gas |
| CN102637778A (en) * | 2012-05-10 | 2012-08-15 | 英利能源（中国）有限公司 | PN junction diffusion method |
| CN104393107A (en) * | 2014-10-27 | 2015-03-04 | 中国电子科技集团公司第四十八研究所 | High-sheet resistance crystalline silicon cell low-voltage diffusion process |
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