CN108074945A - Solid-state imaging apparatus, imaging system and the method for manufacturing solid-state imaging apparatus - Google Patents
Solid-state imaging apparatus, imaging system and the method for manufacturing solid-state imaging apparatus Download PDFInfo
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- CN108074945A CN108074945A CN201711118602.7A CN201711118602A CN108074945A CN 108074945 A CN108074945 A CN 108074945A CN 201711118602 A CN201711118602 A CN 201711118602A CN 108074945 A CN108074945 A CN 108074945A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
- H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
- H01L27/14818—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of solid-state imaging apparatus, imaging system and the method for manufacturing solid-state imaging apparatus.The solid-state imaging apparatus includes：Light shield layer, it is deployed in the contact site office in pixel region and peripheral region and in peripheral region and is electrically connected to substrate, wherein pixel region includes pixel, and pixel includes photo-electric conversion element and charge retention section, and the signal from pixel is processed in peripheral region；First insulating layer has the side surface between charge retention section and contact portion, and is deployed between substrate and light shield layer in plan view；And first insulating component, on the side surface for the end for being deployed in the first insulating layer and buffer the step caused by the end.The shape of the upper surface of the part Chong Die with the first insulating component of light shield layer follows the shape of the first insulating component in plan view.
Description
Technical field
This disclosure relates to solid-state imaging apparatus, imaging system and for manufacturing the one of the method for solid-state imaging apparatus or more
A embodiment.
Background technology
It has been proposed that the active pixel type solid-state imaging apparatus represented with cmos image sensor has global electronic shutter
Function (global electronic shutter function).
The solid-state imaging apparatus for having the function of global electronic shutter includes the light receiving part for opto-electronic conversion and holding
In the charge retention section for the charge that light receiver office is generated by opto-electronic conversion.During this time, exist and incide into charge
The opto-electronic conversion of light in holding part causes the risk of noise signal, this causes image deterioration.Thus, charge retention section has
Necessity is covered by light shield layer, to prevent that light is incident.
Preferably, the current potential of light shield layer is not floating but controlled.In Japanese Patent Publication No.2014-
In 22421, light shield layer is connected to gate electrode or upper-layer wirings (wiring line), and the current potential of light shield layer passes through connection
To control.
The content of the invention
Present disclose provides at least one embodiment of solid-state imaging apparatus, which includes：In pixel region
Pixel in domain, pixel include photo-electric conversion element and the charge maintaining part being sent to by the charge that photo-electric conversion element generates
Point；Peripheral circuit in peripheral region handles the signal from pixel；Light shield layer is deployed in pixel region and peripheral region
In and the contact site office in peripheral region be electrically connected to substrate；First insulating layer has protected in charge in plan view
The side surface between part and contact portion is held, and substrate and shading are being deployed in the section of the plane of plan view
Between layer；And first insulating component, it is deployed on the side surface of the first insulating layer.In the upper surface of the first insulating layer and first
The angle formed between the side surface of insulating component be more than the side surface of the upper surface of the first insulating layer and the first insulating layer it
Between the angle that is formed.The shape of the upper surface of the part Chong Die with the first insulating component of light shield layer follows first in plan view
The shape of insulating component.
Present disclose provides at least one embodiment of solid-state imaging apparatus, including：Pixel region comprising pixel, pixel
The charge retention section being sent to including photo-electric conversion element and by the charge that photo-electric conversion element generates；Peripheral region,
It is middle to dispose the peripheral circuit handled the signal from pixel；Light shield layer is deployed in pixel region and peripheral region simultaneously
And the contact site office in peripheral region is electrically connected to substrate；First insulating layer, in plan view in charge retention section and
Between contact portion there is end, and be deployed in the section of the plane of plan view between substrate and light shield layer；
And first insulating component, on the side surface for the end for being deployed in the first insulating layer and buffer the step caused by end
(step).The shape of the upper surface of the part Chong Die with the first insulating component of light shield layer follows the first insulation structure in plan view
The shape of part.
Present disclose provides for manufacturing at least one embodiment of the method for solid-state imaging apparatus, this method is included in base
The first insulating film is formed on plate, wherein substrate has pixel region and peripheral region, and wherein pixel region includes photoelectric conversion element
The semiconductor regions of part, the gate electrode of the semiconductor regions of charge retention section and transistor and peripheral region include crystalline substance
The gate electrode of body pipe；A part for the first insulating film is removed, to form the first insulating layer；By removing the first insulating film
A part and formed the first insulating layer end side surface on form insulating component, the insulating component buffer due to drawing end
The step risen；And light shield layer is formed, the semiconductor regions of light shield layer covering charge retention section, the end of the first insulating layer
With insulating component and substrate will be electrically connected in peripheral region.The portion Chong Die with insulating component of light shield layer in plan view
The shape for the upper surface divided follows the shape of insulating component.
According to the other aspects of the disclosure, there is discussed herein one or more additional solid-state imaging apparatus, one or more
A imaging system and one or more methods for manufacturing solid-state imaging apparatus.From below with reference to attached drawing to exemplary implementation
In the description of example, the other feature of the disclosure will be apparent.
Description of the drawings
Fig. 1 is the block diagram according to an at least part for the solid-state imaging apparatus of first embodiment.
Fig. 2A is the plan view according to an at least part for the pixel region of the solid-state imaging apparatus of first embodiment.
Fig. 2 B are the schematic sectional views along the solid-state imaging apparatus intercepted of the line IIB-IIB in Fig. 2A.
Fig. 2 C are the schematic sectional views of a part for peripheral region.
Fig. 3 A are the plan views according to an at least part for the solid-state imaging apparatus of first embodiment.
Fig. 3 B are the sectional views along the solid-state imaging apparatus intercepted of the line IIIB-IIIB in Fig. 3 A.
Fig. 3 C are the schematic sectional views of step part.
Fig. 4 A to Fig. 4 C are the sections for being used to manufacture the method for solid-state imaging apparatus illustrated according at least first embodiment
Figure.
Fig. 5 A to Fig. 5 C are the sections for being used to manufacture the method for solid-state imaging apparatus illustrated according at least first embodiment
Figure.
Fig. 6 A and Fig. 6 B are the sections for being used to manufacture the method for solid-state imaging apparatus illustrated according at least first embodiment
Figure.
Fig. 7 A to 7C are the sectional views for being used to manufacture the method for solid-state imaging apparatus illustrated according at least second embodiment.
Fig. 8 A to Fig. 8 C are the sections for being used to manufacture the method for solid-state imaging apparatus illustrated according at least second embodiment
Figure.
Fig. 9 instantiates the exemplary application according at least solid-state imaging apparatus of 3rd embodiment.
Specific embodiment
In at least one embodiment of the solid-state imaging element including light shield layer, it can be formed according in peripheral region
The mode at the joint part (joint) between light shield layer and substrate controls the current potential of light shield layer.But optical anti-reflection structure is deposited
Or be not present or metal silicide region be present or not present in it is different between pixel region and peripheral region.With
It is also different in the quantity for forming these insulating film.In some cases, the end of insulating film be deployed in substrate and light shield layer it
Between, and form step due to the end of insulating film.Step it is possible that reduce light shield layer thickness or cause its disconnection, and
It is likely to occur the conducting failure of light shield layer.
First embodiment
It will be described with reference to the drawings according to the solid-state imaging apparatus of at least first embodiment of the disclosure and for manufacturing solid-state
The method of imaging device.Fig. 1 is the block diagram according to an at least part for the solid-state imaging apparatus of first embodiment.Solid-state imaging is set
It is standby to include：Pixel region 10 comprising the pixel 1 arranged in the matrix form and the peripheral region 20 near pixel region,
And peripheral circuit deployment is enclosed outside in region 20.
For example, each pixel 1 includes photoelectric converter, photoelectric converter includes the photo-electric conversion element for opto-electronic conversion
With for reading the reading section of charge.Reading section includes being protected by the charge that the charge of photo-electric conversion element generation is sent to
Part is held, the charge generated by photo-electric conversion element is transmitted to the transfer transistor of charge retention section and is transmitted by electricity
The transfer transistor for the charge that lotus holding part is kept.It is brilliant that reading section further includes the reset for resetting charge-voltage converter
The amplifying transistor of body pipe, output signal corresponding with the current potential of charge-voltage converter and for selecting amplifying transistor
Transistor.
Pixel region 10 can include the optics black picture element of the shielded photo-electric conversion element of light and not include
Photo-electric conversion element and the pixel (dummy pixels such as in addition to valid pixel) for not exporting image.
Peripheral region 20 includes peripheral circuit, such as vertical scanning circuit 21, column amplifier circuit 22, horizontal scanning circuit
23 and output unit 24.Vertical scanning circuit 21 provides to connect (conducting state) or shut-off (nonconducting state) each picture
The control signal of the transistor of element 1.Vertical signal line 11 is arranged in the row of pixel 1 and reads signal from the pixel 1 in row.
Column amplifier circuit 22 includes differential amplifier circuit and sampling hold circuit, and column amplifier circuit 22 will be output to vertically
The picture element signal amplification of signal wire 11.
Horizontal scanning circuit 23 provides the switch for the amplifier being connected in row and the control for turning on and off switch
Signal.Output unit 24 is formed by such as buffer amplifier and difference amplifier, and by the pixel from column amplifier circuit 22
Signal processing unit outside signal output to solid-state imaging apparatus.Signal processing unit performs modulus to the picture element signal of output
Conversion and the correction to its input data.Solid-state imaging apparatus can be the digital sensor for having analog-digital conversion function.
Fig. 2A to Fig. 2 C is instantiated according at least pixel region of the solid-state imaging element of first embodiment of the present disclosure
The example of a part for a part and peripheral region.Fig. 2A is the plan view of the part of the pixel region of solid-state imaging apparatus.Figure
2B is the schematic sectional view along the solid-state imaging apparatus intercepted of the line IIB-IIB in Fig. 2A.Fig. 2 C are the portions of peripheral region
The schematic sectional view divided.In the accompanying drawings, similar component is by similar symbolic indication.Description herein is included by opto-electronic conversion
The charge of element generation is the situation of electronics.But the charge of generation can be hole.In this case, element and region
Conduction type it is opposite.
Fig. 2A instantiates wherein pixel 1 and is arranged to 3 rows, the example of 3 row.But structure according to the present invention is not limited to
This.For example, each pixel 1 includes photo-electric conversion element 101, charge retention section 102, floating diffusion part (hereinafter referred to as FD
Part) 103, two transfer transistor and source follower (hereinafter referred to as SF) transistors.Pixel 1 further includes reset transistor
With spilling drain electrode (hereinafter referred to as OFD) transistor.
Charge is transmitted to the transfer transistor of charge retention section 102 from photo-electric conversion element 101 includes gate electrode
104.Charge is transmitted to the transfer transistor of FD parts from charge retention section includes gate electrode 105.It is connected to FD parts
Reset transistor include gate electrode 106.The charge of FD parts is converted into the SF transistors of voltage includes gate electrode
107。
OFD transistors include gate electrode 108.Light shield layer 109 covers charge retention section 102, and is deployed
Substrate is connected in peripheral region.Light shield layer 109 can be formed continuously in pixel 1, to be connected in peripheral region
Substrate.The example of substrate can include semiconductor substrate (such as silicon substrate 200).
In fig. 2b, for example, photo-electric conversion element 101 include be located at silicon substrate 200 in n-type semiconductor region 121 with
And PN junction and be the part of a part for the p-type well area of silicon substrate 200 is formed together with n-type semiconductor region 121.Example
Such as, p-type semiconductor region 201 can be deployed in n-type semiconductor region 121, and photo-electric conversion element can have insertion
Formula photoelectric diode structure.Such a configuration reduce the noises generated at the surface of silicon substrate.
For example, charge retention section 102 includes n-type semiconductor region 122, as in photo-electric conversion element 101.Example
Such as, p-type semiconductor region 202 can be deployed in n-type semiconductor region 122, to form damascene structures.
The charge being stored at charge retention section 102 is so that the gate electrode 105 of transfer transistor has electric conduction
The mode of position (on-potential) is transmitted to FD parts 103.FD parts 103 are used as charge-voltage converter and including n-types
Semiconductor regions 123.N-type semiconductor region 123 is connected to the gate electrode 107 of SF transistors, wherein contact 215 and wiring
216 are interposed therebetween.Using this structure, the charge of FD parts 103 is transmitted to according to n-type semiconductor region 123, contact 215
Voltage signal is converted into the capacitance of wiring 216.
OFD parts 203 are deployed to adjacent with photo-electric conversion element 101.When having the gate electrode 108 of OFD transistors
When turning on current potential, charge discharge at photo-electric conversion element 101 is stored in OFD parts 203.Preferably at least one implementation
In example, in all pixels, charge discharges into OFD parts 203 simultaneously.Then, in one or more embodiments, in all pictures
In element, make gate electrode 108 while there is shut-off current potential (off-potential), to start simultaneously at the storage of charge.
After a predetermined time period has elapsed, at least one embodiment, in all pixels, it is stored in photoelectric conversion element
Charge at part 101 is sent to charge retention section 102 simultaneously.It is simultaneously and constant that this realizes the setting in all pixels
The electronic shutter of time for exposure.Which reduce the hysteresis of the phototiming caused by reading charge from pixel order, and
Reduce the distortion of image.
Each pixel is included on the photo-electric conversion element 101, anti-reflective Chong Die with semiconductor regions 121 in plan view
Penetrate film.Anti-reflective film includes insulating film, and can be the insulating layer 211 for example formed by silicon oxide film (SiO) and by nitrogenizing
The multilayer for the insulating layer 212 that silicon fiml (SiN) is formed.Light shield layer 109 is used as the shading light part of covering charge retention section 102,
In be used as be in close contact layer insulating layer 213 be interposed therebetween.
Light shield layer 109 prevents light from inciding into charge retention section 102；That is, light shield layer 109 is reduced due to being kept in charge
The generation of the noise as caused by the charge of incident photogenerated at part 102.Plan view has the surface parallel to silicon substrate 200
The plane of (forming photo-electric conversion element 101 above), and herein refer to the plane on the surface parallel to semiconductor regions 201
Plan view.
In pixel region, light shield layer 109 be deployed at least about charge retention section 102, gate electrode 104 one
Part and a part for gate electrode 105.In other words, light shield layer 109 is deployed at least keeps in plan view with charge
The part overlapping of part 102, a part for gate electrode 104 and gate electrode 105.It needs to use up irradiation photo-electric conversion element
101, therefore, light shield layer 109 is with having opening in photo-electric conversion element 101 in plan view be overlapped part.But shading
Layer 109 can be partly extended in plan view from region Chong Die with the semiconductor regions 122 of charge retention section 102 and
The region of the end overlapping of photo-electric conversion element 101.
Plan view can be parallel to the plan view of the plane on the surface of semiconductor regions 201 or can be parallel to
The plane on the surface (that is, the surfaces of semiconductor regions 202) of the part of the formation charge retention section 102 of silicon substrate 200 is put down
Face figure.
Light shield layer 109 can be less likely the material passed through (such as tungsten, tungsten silicide, tungsten oxide, aluminium or its conjunction by visible ray
Gold) film or its multilayer film formed.The film thickness of light shield layer 109 can be such as 100nm to 200nm.As close contact layer
Insulating layer 213 can be silicon oxide film.Insulating layer 213 is not limited to be used as the layer for being in close contact layer, but can be by any exhausted
Edge material is formed.Light shield layer 109 is integrally formed at the part of deployment gate electrode and does not dispose the part of gate electrode
Place, and can have bumps due to the film thickness of gate electrode.
Interlayer dielectric 214, such as the wiring 216,218 and 220 for signal transmission, contact 215 and through hole
(via) 217 and 219 it is deployed in 200 top of silicon substrate.The example of wiring 216,218 and 220 includes aluminium film, copper film and its alloy
Film.The example of contact 215 and through hole 217 and 219 includes metal film (such as tungsten film, titanium nitride film and titanium film) and its more
Layer.
It is saturating that each pixel 1 can also include the interlayer as optical device being deployed in directly over photo-electric conversion element 101
Mirror 222.Interlayer lens 222 are formed by such as silicon nitride film.The anti-reflective film 221 formed by such as silicon oxynitride film (SiON) can
To be deployed between interlayer dielectric 214 and interlayer lens 222.The anti-reflective film 223 formed by silicon oxynitride film can be disposed
On interlayer lens.Using this anti-reflection structure, the transmissivity of incident light is improved, therefore can improve sensitivity.Not
The colour filter or lenticule of illustration can be deployed in the top of interlayer lens 222.
Fig. 2 C are the sectional views of the transistor for the part that peripheral circuit is formed in peripheral region.In fig. 2 c, illustrate
N-type transistor is as example.In silicon substrate 200, the n-type semiconductor region 112 of transistor is formed.Metal silicide region
402 form on semiconductor regions 112.Side wall is deployed on the side surface of gate electrode 110 of transistor.Side wall is to etch
What the insulating layer 211 and the mode of insulating layer 212 formed by the insulating film for being used as anti-reflective film in pixel region was formed.
For example, the oxygen of insulating layer 211 can be used as by being formed on the pixel region of substrate 200 and peripheral region
SiClx film form side wall with to be etched back (etch back) afterwards as the silicon nitride film of insulating layer 212.
Insulating layer 403 and interlayer dielectric 214 are deployed in the top of the silicon substrate 200 including gate electrode 110 and side wall.
When formed for the opening of contact in interlayer dielectric 214 and can by for example silicon nitride film is formed when, insulating layer 403 can
For use as etch stop film.Interlayer dielectric 214 can be by using plasma activated chemical vapour deposition (CVD) by silicon oxide film
It is formed.These material is without being limited thereto, and might be chosen such that the etch-rate of interlayer dielectric 214 is higher than insulating layer
403 etch-rate.
Fig. 3 A are the plan views according at least solid-state imaging apparatus of first embodiment, from one in pixel 1 to hiding
A part for the peripheral region near contact portion between photosphere 109 and silicon substrate.Fig. 3 B are along the line IIIB- in Fig. 3 A
The sectional view of the solid-state imaging apparatus of IIIB interceptions.
Light shield layer 109 is deployed in pixel region and peripheral region, and electric at the contact portion 302 in peripheral region
It is connected to silicon substrate 200.The side surface that the insulating layer of step part 301 is formed due to insulating film is located at pixel in plan view
Between contact portion 302 in the charge retention section 102 and peripheral region of pixel 1 in region.Light shield layer 109 is from plane
The part Chong Die with charge retention section extends across step part 301, and the contact portion 302 in peripheral region in figure
Place is electrically connected to silicon substrate 200.Can by control silicon substrate 200 current potential and control in the way of being inserted into contact portion 302
The current potential of light shield layer 109 processed.
Thus, apply current potential from substrate 200 to light shield layer 109, and the current potential of light shield layer 109 can be fixed value.It can
With according to photo-electric conversion element 101, the charge holding that the light shield layer 109 with fixed current potential is deployed in wiring and substrate 200
Mode between part 102 and well area prevents photo-electric conversion element 101, charge retention section 102 and well area to be subject to cloth
The influence of line.The reason is that the light shield layer 109 with fixed current potential is used as shielding, which prevents charge retention section 102 and trap
The current potential in region changes due to wiring and coupling between photo-electric conversion element 101, charge retention section 102 and well area.
Earthing potential or other current potentials can be applied to light shield layer 109.For example, negative potential can be applied to enhance charge
The damascene structures of holding part 102.The impedance of the wiring in pixel region can be reduced using auxiliary wiring.
According at least first embodiment, each light shield layer 109 in corresponding row is independent of one another, but in pixel region or
Can be continuous in peripheral region.For example, light shield layer 109 can cover entire pixel region, and can turn with photoelectricity
It changes and opening is formed in the part that element 101 is overlapped in plan view.
In figure 3b, the insulating layer 211 as anti-reflective film and insulating layer 212 and formed by silicon oxide film and be used as tight
The insulating layer 213 of contiguity contact layer, which is disposed, must compare step part 301 closer to pixel.It contacts and is insulating with insulating layer 212
The insulating layer 213 formed on layer 212 has the refractive index different from the refractive index of insulating layer 212.Insulating layer 211, insulating layer 212
It can be formed respectively by such as silicon oxide film, silicon nitride film and silicon oxide film with insulating layer 213.
At compared to position of the step part 301 closer to peripheral circuit, each metal silicide region 402 is in silicon substrate
200 face side (for example, being deployed with the one side of gate electrode above) is formed, and the insulating layer 403 formed by silicon nitride film is disposed
On it, and by silicon oxide film the insulating layer 213 formed is disposed on it.
Each metal silicide region 402 can be formed in contact portion 302 between silicon substrate 200 and light shield layer 109
Peripheral region in formed.Can the electricity of the contact between light shield layer 109 and silicon substrate 200 be reduced by using metal silicide
Resistance.
At step part 301, deployment insulating layer 211, insulating layer 212, insulating layer 401, insulating layer 403 and insulating layer
213, and form step 411 and step 412 by etching insulating film.In figure 3b, at step part 301, from photoelectricity
The insulating layer 211 and 212 that conversion element 101 extends each has end.The end of insulating layer 401 and insulating layer 211 and 212
End part aligning.The insulating layer 403 formed on insulating layer 401 has step due to the end of insulating layer 211,212 and 401
411。
In figure 3b, the insulating layer for extending and being deployed on insulating layer 401 from the contact portion 302 in peripheral region
403 have end at step part 301.The end of insulating layer 403 and another end part aligning of insulating layer 401.Insulating layer
401 and 403 end forms step 412.
Insulating layer 401 and insulating layer 403 can be formed by such as silicon oxide film and silicon nitride film respectively.Forming step
411 and step 412 insulating layer side surface on formed be used as the insulating component 413 of step bolster and insulating component 414.
That is, insulating component 413 is deployed in insulating layer 403 on the side surface at step 411.Insulating component 414 is deployed in form step
On the end of 412 insulating layer 401 and 403.
As shown in FIG. 3 C, at the upper end of insulating layer 403 and insulating component 413 the upper surface of insulating layer 403 421 with
The angle A 2 formed between the side surface 422 of insulating component 413 is more than at the upper end of insulating layer 403 in the upper of insulating layer 403
The angle A 1 formed between surface 421 and side surface 424.In insulating layer at the upper end of insulating layer 403 and insulating component 414
The angle B 2 formed between 403 upper surface 421 and the side surface 423 of insulating component 414 be more than insulating layer 403 another
Upper end is in the angle B 1 formed between the upper surface 421 of insulating layer 403 and side surface 425.Thus, insulating component 413 and absolutely
Edge component 414 is used as the step bolster of buffering step 411 and 412 caused by insulating layer 211,212,401 and 403.
The insulation of angle is formed together with the upper surface of insulating layer 403 at the upper end of insulating layer 403 and insulating component 413
The side surface of component 413 is the curved surface projected upwards and contacted with insulating layer 213, as shown in Figure 3B.Similarly, exist
The insulating component 414 of angle is formed at the upper end of insulating layer 403 and insulating component 414 together with the upper surface of insulating layer 403
Side surface is the curved surface projected upwards and contacted with insulating layer 213, as shown in Figure 3B.
As shown in Figure 3B, the upper surface 421 of insulating layer 403 is illustrated by single dotted broken line, and side surface 424 is by double dot dash line example
Show, another side surface 425 is illustrated by straight line, and the side 422 and 423 of insulating component 413 is illustrated by dotted line.Fig. 3 C are illustrated
The angle A 1, Yi Ji that is formed at the upper end of insulating layer 403 between the upper surface of insulating layer 403 421 and side surface 424
The upper end of insulating layer 403 and insulating component 413 is in the upper surface 421 of insulating layer 403 and the side surface 422 of insulating component 413
Between the angle A 2 that is formed.Fig. 3 C are also illustrated at another upper end of insulating layer 403 in the upper surface of insulating layer 403 421
The angle B 1 that is formed between side surface 425 and at the upper end of insulating layer 403 and insulating component 414 in insulating layer 403
The angle B 2 formed between upper surface 421 and the side surface of insulating component 414 423.
Light shield layer 109 covers charge retention section 102 in pixel region, and is deployed and is electrically connected in peripheral region
It is connected to silicon substrate 200.In plan view, light shield layer 109 in the part of covering charge retention section 102 and is connected to silicon substrate
The step caused by the end of insulating layer is covered at step part 301 between 200 part.Therefore, illustrate in figure 3b
Section in, insulating layer 211,212,401,403 and 213 is deployed between silicon substrate 200 and light shield layer 109.
At step part 301, pin disposes insulating component 413 and 414 in the step 411 and 412 caused by insulating layer,
To buffer step.Thus, light shield layer 109 follows the upper surface of the shape of insulating component 413,414 with its shape.I.e., it is possible to
Prevent the disconnection of light shield layer 109 and the reduction of its film thickness caused by step 411 and 412.Thus, for example, light shield layer
The film thickness of 109 part Chong Die with insulating layer 401 in plan view can be less than the film thickness of the end of insulating layer 401
The film thickness of twice of end for being even less than insulating layer 401.
Phrase " light shield layer 109 follows the upper surface of the shape of component A with its shape " refers to light shield layer 109 with its shape
Shape follows the shape of the upper surface of component A and the upper surface influenced by the shape of the upper surface of component A.Thus, on component A
In the case of forming planarization film and forming light shield layer 109 on planarization film, light shield layer 109 has flat upper surface,
Without pipe component A shape how.In this case, at least one embodiment, light shield layer 109 is abided by without its shape
Follow the upper surface of the shape of component A.
Fig. 3 B instantiate each light shield layer 109 in the insulating layer 403 (and insulating layer 213) being formed in peripheral region
The example of the correspondence metal silicide region 402 of silicon substrate 200 is connected in opening 415.Therefore, light shield layer 109 is electrically connected to
Silicon substrate 200.In this case, contact portion 302 be metal silicide region 402 and light shield layer 109 in opening 415 that
The part of this connection.But embodiment is without being limited thereto.The conductive member different from light shield layer 109 can be deployed in opening 415
In, to be connected to silicon substrate 200 (or silicide regions 402).In this case, contact portion is conductive member and silicon substrate
The part that plate 200 (or silicide regions 402) is in contact with each other.
Using the structure illustrated in Fig. 3 B, insulating layer 213 is deployed the insulating component 413 of 200 top of covering silicon substrate
The insulating layer 212 and 403 of top is deployed in 414 and insulating component 413 and 414.However, it is possible to insulating layer 213 is not provided.
Reference chart 4A to Fig. 4 C, Fig. 5 A to Fig. 5 C in the section identical with Fig. 3 B and Fig. 6 A and Fig. 6 B are described into root
According to the process of the formation solid-state imaging apparatus of at least first embodiment.Fig. 4 A to Fig. 4 C, Fig. 5 A to Fig. 5 C and Fig. 6 A and Fig. 6 B
Instantiate the manufacturing process according to an at least part for the solid-state imaging apparatus of first embodiment.
Isolate (STI) for example, by shallow trench and separated part is formed in the pixel region (not illustrating) of silicon substrate 200.
Then, implanted dopant, to form charge converter, charge retention section and FD parts in such as pixel region.Then, formed
The gate insulating film and gate electrode of transistor.
Therefore, as shown in Figure 2 B, the semiconductor regions 121 of photo-electric conversion element 101, charge retention section 102 are partly led
The gate electrode 104 to 106 and 108 of body region 122 and transistor is formed in pixel region.As shown in Figure 2 C, transistor
Semiconductor regions 112 and gate electrode 110 formed in peripheral region.The process of implanted dopant, which can be divided into, to be formed
Two steps performed before gate electrode and after formation gate electrode.
Then, as shown in Figure 4 A, insulating film 1211 is formed on silicon substrate 200, and insulation is formed on insulating film 1211
Film 1212.The semiconductor regions 121 of photo-electric conversion element 101, the semiconductor regions 122 of charge retention section 102 and crystal
The gate electrode 104 to 108 of pipe forms (not illustrating) on the silicon substrate 200 in pixel region.The gate electrode of transistor exists
It is formed in peripheral region.Insulating film 1211 and 1212 is used as anti-reflective film and for example can accumulate silicon oxide film and silicon nitride
The mode of film is formed.
In Figure 4 A, insulating film 1401 is formed on insulating film 1212, wherein insulating film 1401 is used as when in peripheral region
In silicon substrate 200 on the silicide protection film of pixel region is covered when forming each metal silicide region 402.Insulating film 1401
It can be formed by such as silicon oxide film 401.When the contact openings being formed in later in pixel region, insulating film 1212 can also
As etch stop film.
Then, the part of insulating film 1211,1212 and 1401 is removed, to form insulating layer 211,212 and 401 (referring to figure
4B).For example, photoetching and dry etching are performed, to form pattern so that at least insulating film 1211,1212 and 1401 is retained in picture
In plain region.Therefore, formed between the contact portion 302 in the charge retention section 102 and peripheral region in pixel region
The step 411 caused by the end of insulating layer 211,212 and 401.
Insulating film 1211,1212 and 1401 continues to cover partly leading for photo-electric conversion element 101 after being removed in its part
Body region 121 and 201.During this time, in insulating film 1211,1212 and 1401 it is at least one it is a part of can be in periphery
Side wall is formed on the side surface of the gate electrode of transistor in region.
Then, by with dystectic metal (such as cobalt) and for the titanium nitride oxidation-resistant film with dystectic metal
Form multilayer film.In addition to cobalt, the example with dystectic metal includes titanium, nickel, tungsten, molybdenum, tantalum, chromium, palladium and platinum.Except nitridation
Beyond titanium, include nickel and titanium for the example of the oxidation-resistant film with refractory metal.Then, heat treatment is performed to multilayer film.
By be heat-treated on silicon substrate 200 at least a portion of peripheral region formed each metal silicide region 402 (referring to
Fig. 4 C).Then, removal includes the multilayer film with dystectic unreacted metal.
During this time, by insulating layer 211,212 and 401 cover substrate 200 region not with dystectic gold
The film contact of category, and do not form metal silicide region wherein (except through the part diffuseed to form of metallic element).
Thus, in plan view, formed step 411 insulating layer 211,212 and 401 end substantially with metal silicide region
402 end matching.
In example as described herein, the end of insulating layer 211 and 212 and the end part aligning of insulating layer 401.But absolutely
The end of edge layer 401 can than insulating layer 211 and 212 end closer to the contact portion 302 in peripheral region, such as institute later
As description.Moreover, in this case, insulating layer 401 is used as silicide protection film, and metal silicide region 402 is not
It is formed in the region of the substrate 200 covered by insulating layer 401.
After each metal silicide region 402 is formed, formed on insulating layer 401 and metal silicide region 402
Insulating film, to form insulating layer 403, when forming contact openings in peripheral region, insulating layer 403 is used as etch stop film.
This insulating film can be formed by such as silicon nitride film.A part for insulating film is removed, at least one of peripheral region
Insulating layer 403 is formed in point.
During this time, in the case that the metal silicide region formed in peripheral region is exposed, there are metallic silicons
Compound region disconnecting and the possibility for generating particle, it reduce yields.Thus, insulating layer 403 is by etching insulating film and shape
Into so that metal silicide region 402 does not expose, and part Chong Die with insulating layer 211,212 and 401 in plan view obtains
To retain.In the case where insulating layer 403 is not used as etch stop film, the material of insulating layer 403 is not particularly limited.
The a part of of insulating film can remove for example, by dry etching.During this time, except insulating layer to be used as
Outside 403 insulating film, etching isolation layer 401 is gone back.This forms step 412.Fig. 5 A instantiate the section under this state.
Then, insulating film is formed on the insulating layer 401 and 403 with end, such as in a manner of accumulating silica, and
And by being etched back to form insulating component 413 and 414, wherein, dry method erosion is performed to entire chip in the case of no mask
It carves.Insulating component 413 is formed on the side surface of insulating layer 403 for forming step 411.Insulating component 414 is forming step 412
Insulating layer 401 and 403 end side surface on formed.Fig. 5 B instantiate the section under this state.During this time, may be used
To form insulating component on the side surface of the gate electrode in pixel region and peripheral region.
Then, insulating film is formed by such as silicon oxide film on insulating component 413 and 414 and insulating layer 403 and 212
1213.For example, by being etched with insulating film 1403 as etch stop film, by one of the insulating film 1213 in peripheral region
Part removes, to form the insulating layer 213 (participating in Fig. 5 C) with opening 415a.
After the 415a that is open is formed, for example, by etch to remove insulating film 1403 in plan view with opening 415a
The part of overlapping so that the exposure in peripheral region of each metal silicide region 402, to form the insulation with opening 415
403 (referring to Fig. 6 A) of layer.Therefore, opening 415 is formed in peripheral region, so as in plan view with metal silicide region
402 overlappings.Insulating layer 213 is used as being in close contact layer.Silicon substrate 200 and the distance between light shield layer 109 are shorter, and light-proofness is got over
It is good.It is thus preferable to reduce the film thickness of insulating layer 213.
Then, conductive material (such as tungsten) is accumulated and is patterned by sputtering, with formed light shield layer 109 (referring to
Fig. 6 B).From the perspective of shading, as described above, the distance between the upper surface of charge retention section 102 and light shield layer 109
It is preferably short.Thus, be deployed between insulating layer 403 and light shield layer 109 and insulating component 413 and 414 and light shield layer 109 it
Between insulating layer 213 have reduce film thickness.Insulating layer 403 and light shield layer 109 are deployed in the layer in addition to insulating layer 213
Between and insulating component 413 and 414 and light shield layer 109 between in the case of, the layer disposed preferably has the film reduced
Thickness.Thus, light shield layer 109 has its shape, and corresponding with the shape of insulating component 413 and 414 (that is, its shape follows insulation structure
The shape of part 413 and 414) upper surface.
In the case where not forming insulating component 413 and 414, at step 411 and step 412, light shield layer 109 may
Film thickness or disconnection with reduction, this causes conducting failure.According at least first embodiment, in the side of the end of insulating layer
At least one mode in insulating component 413 and 414 is formed on surface, to the end due to insulating layer 211,212,401 or 403
Step caused by portion is into row buffering.The light shield layer that this prevention is formed on insulating layer 211,212,401 and 403 and insulating component
109 conducting failure.
Then, such as interlayer dielectric 214, wiring, interlayer lens, colour filter and lenticule are formed in known manner.
Using said structure, set including charge retention section 102 and light shield layer 109 and the solid-state imaging with global electronic shutter
The standby current potential that can steadily control light shield layer 109.
One or more other embodiments of the present disclosure are not limited to said structure.For example, it is described according at least first embodiment
Example in, although foring the joint part between light shield layer 109 and silicon substrate 200 in metal silicide region 402,
Joint part can be formed between light shield layer and the part for not becoming metal silicide of silicon substrate 200.It is real according at least first
Example is applied, is not formed for the step (step is caused by being formed of opening 415) formed by insulating layer 211 and 212
Insulating component as step bolster, because the film thickness of step and light shield layer 109 is in comparison small.But as step
The insulating component of bolster can be deployed in opening 415.It can carry out other various modifications, improvement and combination.
Second embodiment
It will be described with reference to figure 7A to 7C and Fig. 8 A to 8C according at least second embodiment for manufacturing solid-state imaging
The method of element.The component similar to the component at least first embodiment represent by similar reference numeral, and omit or
Simplify its description.
As at least first embodiment, the semiconductor regions 121 of photo-electric conversion element 101, charge retention section 102
Semiconductor regions 122 and the gate electrode of transistor form (not illustrating) on silicon substrate 200 in pixel region.Crystal
The semiconductor regions 112 and gate electrode 110 of pipe are formed in peripheral region.Then, accumulation is for example made of silicon oxide film
Insulating film and the insulating film made of silicon nitride film, and by photoetching and a part for dry etching removal insulating layer, with shape
Into insulating layer 211 and insulating layer 212 as anti-reflective film.
Therefore, form step 501 caused by insulating layer 211 and 212 (referring to Fig. 7 A).During this time, Ke Yi
By side will be formed as the insulating film of insulating layer 211 and 212 on the side surface of the gate electrode of transistor in peripheral region
Wall.
Then, form insulating layer 211 and 212 and removing part of it for example, by etching, be used as silication to be formed
After the insulating layer 401 of protective film, the insulating film made of such as silicon oxide film is formed on silicon substrate 200.Therefore, insulating
The end of layer 401 forms step 502.
Then, there is dystectic metal (such as cobalt) to perform heat treatment accumulation, at least the one of peripheral region
Each metal silicide region 402 is formed on silicon substrate 200 in part (referring to Fig. 7 B).Metal silicide region 402 does not exist
It is formed on the part (outside the part formed except through the diffusion of metallic element) covered by insulating layer 401 of substrate 200.
Thus, end of the end of insulating layer 401 in plan view substantially with metal silicide region 402 matches.
Then, formed insulating layer 211,212 and 401 and remove part of it with formed be used as etch stop film it is exhausted
After edge layer 403, such as silicon nitride film is formed on silicon substrate 200.The shape at least a portion of peripheral region of insulating layer 403
Into.During this time, in addition to silicon nitride film, also for example, by a part for etching removal insulating layer 401 (referring to Fig. 7 C).
The corresponding portion of insulating layer 401 and 403 is removed so that metal silicide region 402 is not exposed, and 401 He of insulating layer
The part of insulating layer 403 is stacked.Therefore, the step 503 caused by the end of insulating layer 401 and 403 is formed.
Then, the insulating film made of such as silicon oxide film is formed, and performs eatch-back (wherein, without patterning
In the case of to entire chip perform dry etching), to form insulating component 511,512 and 513.Insulating component 511 is deployed in
On the side surface of the end of insulating layer 211 and 212.Insulating component 512 is deployed in the formation of insulating layer 403 due to insulating layer 401
End caused by step 502 part side surface on.Insulating component 513 is deployed in the side of the end of insulating layer 401 and 403
(referring to Fig. 8 A) on surface.It during this time, can be in the side of the gate electrode of the transistor in pixel region and peripheral region
By forming side wall with the same dielectric film in insulating component 511,512 and 513 on surface.
Then, form the insulating film made of such as silicon oxide film, and remove in peripheral region in plan view with
The part that metal silicide region 402 is overlapped, to form opening and insulating layer 213.During this time, insulating layer 403 is used as erosion
Carve stopper film.Then, by etching to remove the part with superposition of end gap in plan view of insulating layer 403, to form opening
415 so that metal silicide region 402 exposes (referring to Fig. 8 B).
Then, film is formed and is patterned for example, by sputtering by conductive material (such as tungsten), to form light shield layer
109 (referring to Fig. 8 C).The part that silicon substrate 200 is connected in opening portion 415 of light shield layer 109 is contact portion 302.Such as
At least in first embodiment like that, the covering of light shield layer 109 charge retention section 102, step 501,502 and 503, and in periphery
Silicon substrate 200 is electrically connected at contact portion 302 in region.
Moreover, according at least second embodiment, to form insulating component 511,512 on the side surface of the end of insulating layer
With 513 at least one mode to the step caused by the end of insulating layer 211,212,401 or 403 into row buffering.
Which prevent the conducting failures of the light shield layer 109 formed on insulating layer 211,212,401 and 403 and insulating component.
3rd embodiment
To the imaging system according at least 3rd embodiment be described.According at least 3rd embodiment, by showing for imaging system
Example is described as the exemplary application according at least solid-state imaging apparatus of first embodiment and second embodiment.Imaging system is shown
Example includes Digital Still Camera, digital camera, duplicator, facsimile machine, cellular phone, in-vehicle camera and observation satellite.Fig. 9 examples
Show as the block diagram according at least exemplary Digital Still Camera of the imaging system of 3rd embodiment.
In fig.9, imaging system includes the barrier 1001 for lens protection, the optical imagery of object is focused on solid-state
Lens 1002 on imaging device 1004, for changing by the diaphragm of the light quantity of lens 1002 (diaphragm) 1003 and
Mechanical shutter 1005.Imaging system further includes the solid-state imaging apparatus 1004 according at least first embodiment or second embodiment.
The optical imagery focused on by lens 1002 is converted into image data by solid-state imaging apparatus 1004.The half of solid-state imaging apparatus 1004
Conductor substrate includes converter.
Imaging system further include signal processing unit 1007, timing generator 1008, overall control-computing unit 1009,
Memory 1010, recording medium control interface 1011, recording medium 1012 and external interface 1013.Signal processing unit 1007
It corrects and compresses the image data exported from solid-state imaging apparatus 1004.Timing signal is output to solid-state by timing generator 1008
Imaging device 1004 and signal processing unit 1007.Overall control-computing unit 1009 controls entire Digital Still Camera.Example
Such as, central processing unit (CPU) can be used as overall control-computing unit 1009.Memory 1010 is used as depositing temporarily
Store up the frame memory of image data.Recording medium control interface 1011 performs record on the recording medium and therefrom reads.
Recording medium 1012 includes separable semiconductor memory, and performs record and read image data.It is external
Interface 1013 is the interface for communicating with such as outer computer.Timing signal for example can be defeated from the outside of imaging system
Enter.Imaging system is only needed to include the image letter that at least solid-state imaging apparatus 1004 and processing are exported from solid-state imaging apparatus 1004
Number signal processing unit 1007.
Other embodiments
Above-described embodiment is performed for the specific example of the one or more aspects of the disclosure.Not in limited scope
Explain the technical scope of the present invention.That is, on the premise of without departing substantially from technological concept, the present invention can be held as various embodiments
Row.
Although describe the disclosure by reference to exemplary embodiment it should be appreciated that the invention is not restricted to institutes
Disclosed exemplary embodiment.The scope of the following claims will be endowed broadest interpretation, to cover all such repair
Change and equivalent structure and function.
Claims (30)
1. a kind of solid-state imaging apparatus, which is characterized in that including：
Pixel in pixel region, the pixel include photo-electric conversion element and the charge generated by the photo-electric conversion element
The charge retention section being sent to；
Peripheral circuit in peripheral region, the peripheral circuit handle the signal from the pixel；
Light shield layer is deployed in the contact site office in the pixel region and the peripheral region and in the peripheral region
It is electrically connected to substrate；
First insulating layer has the side surface between the charge retention section and the contact portion in plan view, and
And it is being deployed in the section of the plane of the plan view between the substrate and the light shield layer；And
First insulating component is deployed on the side surface of the first insulating layer,
The angle wherein formed between the upper surface of the first insulating layer and the side surface of the first insulating component is more than first absolutely
The angle that is formed between the upper surface of edge layer and the side surface of the first insulating layer and
The shape of the upper surface of the part Chong Die with the first insulating component of light shield layer follows wherein described in the plan view
The shape of first insulating component.
2. solid-state imaging apparatus according to claim 1,
Wherein second insulating layer is deployed in the section between the substrate and the first insulating layer.
3. solid-state imaging apparatus according to claim 2,
Wherein second insulating layer has the end in the section between the substrate and the first insulating layer,
Wherein the first insulating layer covers the end of second insulating layer and with due to drawing the end of second insulating layer
Rise step and
Wherein the second insulating component be deployed in the first insulating layer on the side surface at the step.
4. solid-state imaging apparatus according to claim 3,
Wherein second insulating layer have in the section with another end of the end part aligning of the first insulating layer and
Wherein the first insulating component be deployed in the end of the first insulating layer side surface and second insulating layer it is described another
On the side surface of a end.
5. solid-state imaging apparatus according to claim 4,
Wherein the 3rd insulating layer is deployed in the section between the substrate and second insulating layer,
Wherein the 3rd insulating layer have with the end of another end part aligning described in second insulating layer and
The 3rd insulating layer covers the charge retention section wherein in the plan view.
6. solid-state imaging apparatus according to claim 1,
Wherein the first insulating layer has the opening that the light shield layer is electrically connected to the substrate in the peripheral region.
7. solid-state imaging apparatus according to claim 1,
Wherein, in a state that the silicide regions being formed on the substrate are inserted between the light shield layer and the substrate,
The light shield layer is electrically connected to the substrate.
8. solid-state imaging apparatus according to claim 1,
The film thickness of the part Chong Die with the first insulating layer of light shield layer is less than the first insulation wherein described in the plan view
Twice of the film thickness of the end of layer.
9. solid-state imaging apparatus according to claim 1,
The film thickness of the part Chong Die with the first insulating layer of light shield layer is less than the first insulation wherein described in the plan view
The film thickness of the end of layer.
10. a kind of imaging system, which is characterized in that including：
Solid-state imaging apparatus according to any one of claim 1 to 9；And
Signal processing unit handles the signal of the solid-state imaging apparatus output.
11. a kind of solid-state imaging apparatus, which is characterized in that including：
Pixel region comprising pixel, the pixel include photo-electric conversion element and the charge generated by the photo-electric conversion element
The charge retention section being sent to；
Peripheral region disposes the peripheral circuit handled the signal from the pixel in the external zones；
Light shield layer is deployed in the contact site office in the pixel region and the peripheral region and in the peripheral region
It is electrically connected to substrate；
First insulating layer has the end between the charge retention section and the contact portion in plan view, and
It is being deployed in the section of the plane of the plan view between the substrate and the light shield layer；And
First insulating component on the side surface for the end for being deployed in the first insulating layer and is buffered since the end causes
Step,
The shape of the upper surface of the part Chong Die with the first insulating component of light shield layer follows wherein described in the plan view
The shape of first insulating component.
12. solid-state imaging apparatus according to claim 11,
Wherein second insulating layer is deployed in the section between the substrate and the first insulating layer.
13. solid-state imaging apparatus according to claim 12,
Wherein second insulating layer has the end between the substrate and the first insulating layer in the section,
Wherein the first insulating layer covering second insulating layer the end and with due to second insulating layer the end and
Caused step and
Wherein the second insulating component be deployed in the first insulating layer on the side surface at the step.
14. solid-state imaging apparatus according to claim 13,
Wherein second insulating layer have in the section with another end of the end part aligning of the first insulating layer and
Wherein the first insulating component be deployed in the end of the first insulating layer side surface and second insulating layer it is described another
On the side surface of a end.
15. solid-state imaging apparatus according to claim 14,
Wherein the 3rd insulating layer is deployed in the section between the substrate and second insulating layer,
Wherein the 3rd insulating layer have with the end of another end part aligning described in second insulating layer and
The 3rd insulating layer covers the charge retention section wherein in the plan view.
16. solid-state imaging apparatus according to claim 11,
Wherein the first insulating layer has the opening that the light shield layer is electrically connected to the substrate in the peripheral region.
17. solid-state imaging apparatus according to claim 11,
Wherein, in a state that the silicide regions being formed on the substrate are inserted between the light shield layer and the substrate,
The light shield layer is electrically connected to the substrate.
18. solid-state imaging apparatus according to claim 11,
The film thickness of the part Chong Die with the first insulating layer of light shield layer is less than the first insulation wherein described in the plan view
Twice of the film thickness of the end of layer.
19. solid-state imaging apparatus according to claim 11,
The film thickness of the part Chong Die with the first insulating layer of light shield layer is less than the first insulation wherein described in the plan view
The film thickness of the end of layer.
20. a kind of imaging system, which is characterized in that including：
Solid-state imaging apparatus according to any one of claim 11 to 19；And
Signal processing unit handles the signal of the solid-state imaging apparatus output.
A kind of 21. method for manufacturing solid-state imaging apparatus, which is characterized in that the described method includes：
The first insulating film is formed on the substrate with pixel region and peripheral region, wherein the pixel region turns comprising photoelectricity
Change the semiconductor regions of element, the gate electrode of the semiconductor regions of charge retention section and transistor and wherein described
Peripheral region includes the gate electrode of transistor；
A part for the first insulating film is removed, to form the first insulating layer；
On the side surface of the end of the first insulating layer formed by removing the part of the first insulating film, formed exhausted
Edge component, insulating component buffering step caused by the end；And
Light shield layer is formed, the light shield layer covers the semiconductor regions of the charge retention section, the institute of the first insulating layer
It states end and the insulating component and the substrate is electrically connected in the peripheral region,
Described in wherein the shape of the upper surface of the part Chong Die with the insulating component of the light shield layer follows in plan view
The shape of insulating component.
22. the method according to claim 21 for manufacturing the solid-state imaging apparatus,
Wherein, with formed on the first insulating layer with the end the second insulating film and by dry etching remove second
The form of insulating film forms the insulating component.
23. the method according to claim 22 for manufacturing the solid-state imaging apparatus,
The 3rd insulating film is wherein formed on the substrate, and removes a part for the 3rd insulating film to form the second insulation
Layer,
Wherein the first insulating film formed over the second dielectric and
Wherein, when the part of the first insulating film is removed, a part for second insulating layer is removed.
24. the method according to claim 23 for manufacturing the solid-state imaging apparatus,
Wherein, remove the 3rd insulating film it is described a part at least in the pixel region formed second insulating layer after
And before the first insulating film is formed, to form metal film at least in the peripheral region and be held on the metal film
The mode of row heat treatment at least forms metal silicide region in a part for the peripheral region.
25. the method according to claim 23 for manufacturing the solid-state imaging apparatus,
Wherein, when before the first insulating film is formed remove the 3rd insulating film the part when, the 3rd insulating film it is described
A part is included in the part on the semiconductor regions of the transistor in the peripheral region.
26. the method according to claim 23 for manufacturing the solid-state imaging apparatus further includes：
The 4th insulating film is formed on the substrate before the 3rd insulating film is formed,
Wherein, when removing the part of the 3rd insulating film, a part for the 4th insulating film is removed to form the 3rd insulation
Layer and
Wherein, after the part is removed, the 4th insulating film, which continues to cover the described of the photo-electric conversion element, partly leads
Body region.
27. the method according to claim 26 for manufacturing the solid-state imaging apparatus,
Wherein, when the part of the 4th insulating film is removed, the part and the 4th insulating film of the 4th insulating film
The part that is formed in the peripheral region correspond to, and the refractive index of the 4th insulating film is different from contacting with the 4th insulating film
And the refractive index of the insulating film formed on the 4th insulating film.
28. according to any one of claim 21 to 27 for the method that manufactures the solid-state imaging apparatus,
Wherein, formed before the light shield layer is formed, in the first insulating layer in the peripheral region opening and
Wherein described light shield layer is electrically connected to the substrate in said opening.
29. according to any one of claim 21 to 27 for the method that manufactures the solid-state imaging apparatus,
Wherein, before the light shield layer is formed, the semiconductor regions for covering the charge retention section, first are formed absolutely
5th insulating film of edge layer and the insulating component and
A part for wherein the 5th insulating film is removed to form opening, wherein the first insulating layer is used as etch stop film.
30. the method according to claim 29 for manufacturing the solid-state imaging apparatus,
Wherein, after the part of the 5th insulating film is removed to form the opening, in said opening, first absolutely
A part for edge layer is removed, in the first insulating layer formed opening and
Wherein described light shield layer is connected to the substrate in said opening.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2016-224382 | 2016-11-17 | ||
| JP2016224382A JP6833470B2 (en) | 2016-11-17 | 2016-11-17 | Solid-state image sensor, image sensor, and method for manufacturing solid-state image sensor |
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| JP2021019058A (en) * | 2019-07-18 | 2021-02-15 | キヤノン株式会社 | Photoelectric conversion device and apparatus |
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| JPH10289994A (en) * | 1997-04-14 | 1998-10-27 | Denso Corp | Optical sensor integrated circuit device |
| JP2007059834A (en) * | 2005-08-26 | 2007-03-08 | Sharp Corp | Solid-state imaging apparatus and manufacturing method thereof, and electronic information apparatus |
| JP2012248681A (en) * | 2011-05-27 | 2012-12-13 | Canon Inc | Manufacturing method of solid-state image pickup device |
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| JP4652773B2 (en) | 2004-11-05 | 2011-03-16 | パナソニック株式会社 | Amplification type solid-state imaging device |
| JP2012094719A (en) * | 2010-10-27 | 2012-05-17 | Sony Corp | Solid-state imaging device, method of manufacturing the same and electronic device |
| JP2012182426A (en) * | 2011-02-09 | 2012-09-20 | Canon Inc | Solid state image pickup device, image pickup system using solid state image pickup device and solis state image pickup device manufacturing method |
| JP2014022421A (en) | 2012-07-13 | 2014-02-03 | Sony Corp | Solid-state imaging element, method for manufacturing the same, and electronic device |
| WO2014103150A1 (en) | 2012-12-28 | 2014-07-03 | パナソニック株式会社 | Solid state imaging device and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10289994A (en) * | 1997-04-14 | 1998-10-27 | Denso Corp | Optical sensor integrated circuit device |
| JP2007059834A (en) * | 2005-08-26 | 2007-03-08 | Sharp Corp | Solid-state imaging apparatus and manufacturing method thereof, and electronic information apparatus |
| JP2012248681A (en) * | 2011-05-27 | 2012-12-13 | Canon Inc | Manufacturing method of solid-state image pickup device |
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| US10461119B2 (en) | 2019-10-29 |
| CN108074945B (en) | 2022-03-08 |
| JP6833470B2 (en) | 2021-02-24 |
| US20180138234A1 (en) | 2018-05-17 |
| JP2018082098A (en) | 2018-05-24 |
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