CN108063115B - TSV adapter plate for system-in-package and preparation method thereof - Google Patents

TSV adapter plate for system-in-package and preparation method thereof Download PDF

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CN108063115B
CN108063115B CN201711352394.7A CN201711352394A CN108063115B CN 108063115 B CN108063115 B CN 108063115B CN 201711352394 A CN201711352394 A CN 201711352394A CN 108063115 B CN108063115 B CN 108063115B
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tsv
region
substrate
photoetching
forming
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CN108063115A (en
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张捷
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Institute of Flexible Electronics Technology of THU Zhejiang
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Institute of Flexible Electronics Technology of THU Zhejiang
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

The invention relates to a TSV adapter plate for system-in-package and a preparation method thereof, wherein the method comprises the following steps: selecting a Si substrate; preparing a plurality of TSVs and a plurality of isolation trenches in the Si substrate; filling the isolation trench and the TSV to form an isolation region and a TSV region respectively; preparing a gate region of the MOS tube on the upper surface of the Si substrate; preparing a source region and a drain region of the MOS tube by using an ion implantation process; preparing an interconnection line between the first end face of the TSV region and the MOS tube on the upper surface of the Si substrate; and preparing a metal salient point on the second end face of the TSV region. According to the TSV adapter plate, the ESD protection device MOS tube is processed on the TSV adapter plate, so that the antistatic capacity of the stacked packaged chip is enhanced.

Description

TSV adapter plate for system-in-package and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a TSV adapter plate for system-in-package and a preparation method thereof.
Background
Three-dimensional (3D) integration calculation is currently considered as the preferred solution for sustainable realization of miniaturization, high density and multiple functions beyond moore's law, and Through-silicon via (TSV) technology is the key of Three-dimensional integration, and interconnection with the shortest distance and the smallest pitch between chips can be realized.
As an important index of success and mass production of chips, the overall electrostatic Discharge (ESD) performance of a 3D-IC (three-dimensional integrated circuit) after stacking is an important aspect, and an ultra-large scale 3D-IC chip faces a huge challenge in ESD design, and ESD affects the electrical performance of the whole 3D-IC chip, even fails to work normally.
An interposer generally refers to the functional layer of interconnection and pin redistribution between a chip and a package substrate. The adapter plate can redistribute dense I/O leads, high-density interconnection of multiple chips is achieved, and the adapter plate becomes one of the most effective means for electrical signal connection between a nanoscale integrated circuit and a millimeter-scale macroscopic world. Conventional ESD designs focus on solving the problem of electrostatic discharge within a single chip. When the adapter plate is used for realizing integration of multifunctional chips, the antistatic capacity of different chips is different, and the antistatic capacity of the packaged whole system can be influenced by the chips with weak antistatic capacity when the chips are stacked in three dimensions, so that how to improve the antistatic capacity of the system-in-package based on the TSV process becomes a problem to be solved urgently in the semiconductor industry.
Disclosure of Invention
In order to improve the antistatic capacity of a 3D integrated circuit based on a TSV process, the invention provides a TSV adapter plate for system-in-package and a preparation method thereof; the technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a TSV adapter plate for system-in-package, which comprises the following steps:
s101, selecting a Si substrate;
s102, preparing TSV and an isolation trench in a Si substrate;
s103, filling the isolation trench and the TSV to form an isolation region and a TSV region respectively;
s104, preparing a gate region of the MOS tube on the upper surface of the Si substrate;
s105, preparing a source region and a drain region of the MOS tube by using an ion implantation process;
s106, preparing an interconnection line between the first end face of the TSV region and the MOS tube on the upper surface of the Si substrate;
and S107, preparing a metal bump on the second end face of the TSV region.
In one embodiment of the invention, the doping type of the Si substrate is P type, and the doping concentration is 1 x 1014～1×1015cm-3The thickness is 150 to 250 μm; the thickness of the isolation region and the TSV region is 80-120 mu m.
In one embodiment of the present invention, S102 includes:
s1021, forming an etching pattern of the TSV and the isolation groove on the upper surface of the Si substrate by utilizing a photoetching process;
s1022, Etching the Si substrate by utilizing a Deep Reactive Ion Etching (DRIE) process to form TSV and an isolation trench;
wherein the isolation trench is located between the two TSVs.
In one embodiment of the present invention, S103 includes:
s1031, thermally oxidizing the TSV and the isolation trench to form a first oxidation layer on the inner walls of the TSV and the isolation trench;
s1032, etching the first oxide layer by using a wet etching process to finish the planarization of the inner walls of the TSV and the isolation trench;
s1033, forming a filling pattern of the isolation groove by utilizing a photoetching process;
s1034, filling the first SiO in the isolation trench by Chemical Vapor Deposition (CVD)2Forming an isolation region from a material;
s1035, forming a TSV filling pattern by utilizing a photoetching process;
s1036, filling polycrystalline silicon in the TSV by using a CVD (chemical vapor deposition) process, and introducing doping gas to perform in-situ doping to form a TSV region.
In one embodiment of the present invention, S104 includes:
s1041, photoetching a P well region on the Si substrate, and forming the P well by adopting an ion implantation process with glue;
s1042, forming a gate oxide layer on the surface of the Si substrate by using a thermal oxidation process;
s1043, adjusting the threshold voltage by adopting an ion implantation process with glue;
s1044, depositing polycrystalline silicon on the surface of the Si substrate by using a CVD (chemical vapor deposition) process, photoetching a gate electrode pattern, and etching the polycrystalline silicon by using a dry etching process to form a polycrystalline silicon gate;
and S1045, photoetching a gate electrode graph, and doping the polysilicon gate by using an ion implantation process with glue to form a gate region.
In one embodiment of the present invention, S105 includes:
s1051, depositing a second SiO on the surface of the Si substrate by CVD process2Forming a second oxide layer by using a dry etching process;
s1052, photoetching source region and drain region patterns, and performing N by adopting a photoresist ion implantation process+Ion implantation is carried out, the photoresist is removed, and a source region and a drain region of the MOS tube are formed;
s1053, photoetching a P well contact area pattern, and performing P by adopting a photoresist ion implantation process+And (4) performing ion implantation, removing the photoresist and forming a P well contact region of the MOS tube.
In an embodiment of the present invention, S107 further includes:
x1, using the auxiliary wafer as a support of the upper surface of the Si substrate;
and X2, thinning the lower surface of the Si substrate by using a Mechanical grinding and thinning process, and flattening the lower surface of the Si substrate by using a Chemical Mechanical Polishing (CMP) process until the second end face of the TSV region is exposed.
In one embodiment of the present invention, S107 includes:
s1071, forming a liner layer and a barrier layer on the lower surface of the Si substrate by using a sputtering process, and forming a tungsten plug on the second end face of the TSV region by using a CVD process;
s1072, depositing an insulating layer, photoetching a pattern of the metal salient point on the second end face of the TSV region, depositing metal by using an electrochemical process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal salient point on the second end face of the TSV region;
s1073, removing the auxiliary wafer.
In one embodiment of the invention, the thickness of the isolation region and the TSV region is 80-120 μm.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the TSV adapter plate, the ESD protection device MOS tube is processed on the TSV adapter plate, so that the antistatic capacity of a stacked packaged chip is enhanced;
2. according to the invention, the MOS tube is processed on the TSV adapter plate, and the high heat dissipation capacity of the adapter plate is utilized, so that the high-current passing capacity of the device in the working process is improved;
3. the TSV adapter plate provided by the invention has the advantages that the isolation grooves which are communicated up and down are utilized around the MOS tube, so that the leakage current and the parasitic capacitance are smaller;
4. the preparation method of the TSV adapter plate for the system-in-package can be realized in the conventional TSV process platform, so that the compatibility is strong, and the application range is wide.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a TSV interposer for system-in-package according to an embodiment of the present invention;
fig. 2a to fig. 2i are flow charts of another method for manufacturing a TSV interposer for system-in-package according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a TSV interposer for system in package according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a TSV interposer for system-in-package according to an embodiment of the present invention, including:
s101, selecting a Si substrate;
s102, preparing TSV and an isolation trench in a Si substrate;
s103, filling the isolation trench and the TSV to form an isolation region and a TSV region respectively;
s104, preparing a gate region of the MOS tube on the upper surface of the Si substrate;
s105, preparing a source region and a drain region of the MOS tube by using an ion implantation process;
s106, preparing an interconnection line between the first end face of the TSV region and the MOS tube on the upper surface of the Si substrate;
and S107, preparing a metal bump on the second end face of the TSV region.
Preferably, the doping type of the Si substrate is P type, and the doping concentration is 1 multiplied by 1014～1×1015cm-3The thickness is 150 to 250 μm; the thickness of the isolation region and the TSV region is 80-120 mu m.
Preferably, S102 may include:
s1021, forming an etching pattern of the TSV and the isolation groove on the upper surface of the Si substrate by utilizing a photoetching process;
s1022, etching the Si substrate by using a DRIE process to form a TSV and an isolation trench;
wherein the isolation trench is located between the two TSVs.
Preferably, S103 may include:
s1031, thermally oxidizing the TSV and the isolation trench to form a first oxidation layer on the inner walls of the TSV and the isolation trench;
s1032, etching the first oxide layer by using a wet etching process to finish the planarization of the inner walls of the TSV and the isolation trench;
s1033, forming a filling pattern of the isolation groove by utilizing a photoetching process;
s1034, filling the first SiO in the isolation trench by using a CVD process2Forming an isolation region from a material;
s1035, forming a TSV filling pattern by utilizing a photoetching process;
s1036, filling polycrystalline silicon in the TSV by using a CVD (chemical vapor deposition) process, and introducing doping gas to perform in-situ doping to form a TSV region.
Preferably, S104 may include:
s1041, photoetching a P well region on the Si substrate, and forming the P well by adopting an ion implantation process with glue;
s1042, forming a gate oxide layer on the surface of the Si substrate by using a thermal oxidation process;
s1043, adjusting the threshold voltage by adopting an ion implantation process with glue;
s1044, depositing polycrystalline silicon on the surface of the Si substrate by using a CVD (chemical vapor deposition) process, photoetching a gate electrode pattern, and etching the polycrystalline silicon by using a dry etching process to form a polycrystalline silicon gate;
and S1045, photoetching a gate electrode graph, and doping the polysilicon gate by using an ion implantation process with glue to form a gate region.
Preferably, S105 may include:
s1051, depositing a second SiO on the surface of the Si substrate by CVD process2Forming a second oxide layer by using a dry etching process;
s1052 and photoetching sourcePatterning the region and the drain region by ion implantation with glue+Ion implantation is carried out, the photoresist is removed, and a source region and a drain region of the MOS tube are formed;
s1053, photoetching a P well contact area pattern, and performing P by adopting a photoresist ion implantation process+And (4) performing ion implantation, removing the photoresist and forming a P well contact region of the MOS tube.
Specifically, S107 is preceded by:
x1, using the auxiliary wafer as a support of the upper surface of the Si substrate;
and X2, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process, and flattening the lower surface of the Si substrate by using a CMP process until the second end face of the TSV region is exposed.
Preferably, S107 may include:
s1071, forming a liner layer and a barrier layer on the lower surface of the Si substrate by using a sputtering process, and forming a tungsten plug on the second end face of the TSV region by using a CVD process;
s1072, depositing an insulating layer, photoetching a pattern of the metal salient point on the second end face of the TSV region, depositing metal by using an electrochemical process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal salient point on the second end face of the TSV region;
s1073, removing the auxiliary wafer.
Preferably, the thickness of the isolation region and the TSV region is 80-120 mu m.
According to the preparation method of the TSV adapter plate, the ESD protection device MOS tube is processed on the TSV adapter plate, so that the antistatic capacity of stacked and packaged chips is enhanced, and the problem that the antistatic capacity of a packaged whole system is affected by chips with weak antistatic capacity during three-dimensional stacking is solved; meanwhile, the embodiment provides the TSV adapter plate with the isolation region which is communicated up and down and has smaller leakage current and parasitic capacitance.
Example two
In this embodiment, on the basis of the above embodiments, specific parameters in the method for manufacturing the TSV interposer for system-in-package according to the present invention are described as follows. Specifically, referring to fig. 2a to fig. 2i, fig. 2a to fig. 2i are flow charts of another method for manufacturing a TSV interposer for system-in-package according to an embodiment of the present invention,
s201, as shown in FIG. 2a, selecting a Si substrate 201;
preferably, the doping type of the Si substrate is P type, and the doping concentration is 1 multiplied by 1014～1×1015cm-3The thickness is 150 to 250 μm.
S202, as shown in fig. 2b, preparing the TSV202 and the isolation trench 203 on the Si substrate by using an etching process may include the following steps:
s2021, growing a layer of SiO with the thickness of 800nm to 1000nm on the upper surface of the Si substrate by a thermal oxidation process at the temperature of 1050 ℃ to 1100 DEG C2A layer;
s2022, completing TSV and isolation trench etching graphs by using a photoetching process through processes of gluing, photoetching, developing and the like;
s2023, etching the Si substrate by using a DRIE (deep etch etching) process to form TSV and an isolation trench with the depth of 80-120 mu m;
s2024, removing SiO on the Si substrate by using CMP process2The substrate surface is planarized.
Preferably, two isolation trenches are located between two TSVs.
S203, as shown in FIG. 2 c; deposition of SiO on Si substrates by CVD process2Filling the isolation trench to form an isolation region, which may specifically include the following steps:
s2031, thermally oxidizing the inner walls of the TSV and the isolation trench to form an oxide layer with the thickness of 200nm to 300nm at the temperature of 1050 ℃ to 1100 ℃;
s2032, etching the oxidation layer of the inner walls of the TSV and the isolation trench by using a wet etching process to finish the planarization of the inner walls of the TSV and the isolation trench. Preventing the TSV and the protrusion of the side wall of the isolation trench from forming an electric field concentration area;
s2033, completing the filling pattern of the isolation trench by gluing, photoetching, developing and other processes by utilizing a photoetching process;
s2034, Low pressure chemical Vapor Deposition (L) at 690-710 deg.CPCVD) process, deposition of SiO2Filling the isolation groove to form an isolation region; as can be appreciated, the SiO2The material is mainly used for isolation and can be replaced by other materials such as undoped polysilicon and the like;
s2035, planarizing the surface of the substrate by using a CMP process.
S204, as shown in FIG. 2 d; the method comprises the following steps of depositing a polycrystalline silicon material on a Si substrate by using a CVD (chemical vapor deposition) process to fill TSV, and simultaneously introducing doping gas to carry out in-situ doping on the polycrystalline silicon to form a TSV region, wherein the method specifically comprises the following steps:
s2041, completing a TSV filling pattern through processes such as gluing, photoetching and developing by utilizing a photoetching process;
s2042, depositing a polycrystalline silicon material by using a CVD (chemical vapor deposition) process at the temperature of 600-620 ℃ to fill the TSV, introducing doping gas to carry out in-situ doping, and realizing in-situ activation of doping elements to form highly doped polycrystalline silicon filling. Therefore, when the TSV is filled, the conductive material with uniform impurity distribution and high doping concentration can be formed for filling, and the resistance of the TSV is favorably reduced. The doping concentration of polysilicon is preferably 2 × 1021cm-3The doping impurity is preferably phosphorus;
and S2043, flattening the surface of the substrate by utilizing a CMP process.
S205, as shown in FIG. 2 e; the preparation of the gate region 204 on the upper surface of the Si substrate may specifically include the following steps:
s2051, forming a silicon dioxide buffer layer on the surface of the Si substrate by utilizing a thermal oxidation process at the temperature of 1050-1100 ℃;
s2052, depositing a silicon nitride layer on the surface of the Si substrate by an LPCVD process at the temperature of 700-800 ℃;
and S2053, photoetching the P well region, performing boron injection by adopting an ion injection process with glue, removing the photoresist, and forming the P well region of the MOS tube. The doping concentration of silicon is preferably 1 × 1016cm-3；
S2054, annealing the substrate for 2.5 hours at the temperature of 950 ℃ to carry out P well propulsion.
S2055, removing the silicon nitride layer and the silicon dioxide buffer layer by using a CMP process;
s2056, forming a gate oxide layer on the surface of the Si substrate by utilizing a thermal oxidation process at the temperature of 1050-1100 ℃;
s2057, adopting a glue-carrying ion implantation process to carry out boron implantation, removing photoresist, and carrying out threshold voltage adjustment on the MOS tube;
s2058, depositing a polysilicon material on the surface of the Si substrate by using a CVD (chemical vapor deposition) process at the temperature of 600-620 ℃;
s2059, completing a gate electrode etching graph by using a photoetching process through processes such as gluing, photoetching, developing and the like;
s20510, etching the polycrystalline silicon by using a dry etching process to form a gate electrode;
s20511, photoetching the gate electrode area image, performing phosphorus injection by adopting a photoresist-carrying ion injection process, removing the photoresist to form a gate area of the MOS tube, wherein the doping concentration of the polycrystalline silicon is preferably 5 multiplied by 1019cm-3；
S20512, annealing the substrate for 15-120S at 950-1100 ℃ to activate the impurities.
S206, as shown in FIG. 2 f; the method for preparing the source region 205 and the drain region 206 of the MOS by using the ion implantation process may specifically include the following steps:
s2061, depositing a silicon dioxide layer on a Si substrate at the temperature of 750 ℃ by adopting a CVD process;
s2062, completing an oxide layer side wall etching graph by using a photoetching process through processes of gluing, photoetching, developing and the like;
s2063, etching the silicon dioxide by using a dry etching process to form an oxide layer side wall;
s2064, photoetching source region and drain region images, performing phosphorus implantation by adopting a photoresist-carrying ion implantation process, removing photoresist, and forming a source region and a drain region of the MOS tube, wherein the doping concentration of the source region and the drain region of the MOS tube is preferably 5 x 1019cm-3；
S2065, photoetching the P well contact region, performing boron implantation by adopting a photoresist-carrying ion implantation process, removing photoresist, and forming the P well contact region 207 of the MOS tube, wherein the doping concentration of the P well contact region is preferably 1 × 1020cm-3；
S2066, annealing the substrate for 15-120S at the temperature of 950-1100 ℃ and carrying out impurity activation.
S207, as shown in FIG. 2 g; the copper interconnection line 208 is formed on the upper surface of the Si substrate by using an electroplating process, which may specifically include the following steps:
s2071, depositing SiO on the surface of the substrate by Plasma Enhanced Chemical Vapor Deposition (PECVD) process2A layer;
s2072, completing contact hole patterns at the first end of the TSV region and the gate region, the source region, the drain region and the P well contact region of the MOS by using a photoetching process through processes of gluing, photoetching, developing and the like;
s2073, depositing a Ti film, a TiN film and tungsten on the first end of the TSV region and the gate region, the source region, the drain region and the P well contact region of the MOS by using a CVD process to form a tungsten plug;
s2074, flattening the surface of the substrate by using a CMP process;
s2075, depositing SiO2The insulating layer is used for photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating method, removing redundant copper by using a chemical mechanical grinding method, and forming a first end of the TSV region and an MOS (metal oxide semiconductor) tube serial copper interconnection line;
and S2076, flattening the surface of the substrate by using a CMP process.
Further, when the copper interconnection line is prepared, the metal interconnection line can be used to be wound in a spiral shape so as to have the characteristic of inductance for better electrostatic protection of the radio frequency integrated circuit.
S208, as shown in FIG. 2 h; the method for thinning the Si substrate by using the chemical mechanical polishing process to leak the TSV region specifically comprises the following steps:
s2081, bonding the upper surface of the Si substrate with an auxiliary wafer by using a high polymer material as an intermediate layer, and finishing the thinning of the Si substrate through the support of the auxiliary wafer;
s2082, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process until the thickness is slightly larger than the depth of the TSV region, preferably larger than the depth of the TSV by 10 microns;
s2083, flattening the lower surface of the Si substrate by using a CMP process until the TSV region is exposed;
s209, as shown in FIG. 2 i; the forming of the copper bump 209 on the lower surface of the Si substrate by electroplating may specifically include the following steps:
s2091, depositing SiO on the lower surface of the substrate by using a PECVD process2A layer;
s2092, at the second end of the TSV region, completing a contact hole pattern through processes of gluing, photoetching, developing and the like by using a photoetching process;
s2093, depositing a Ti film, a TiN film and tungsten at the second end of the TSV region by using a CVD (chemical vapor deposition) process to form a tungsten plug;
s2094, flattening the surface of the substrate by using a CMP process;
s2095, depositing SiO2An insulating layer for photoetching copper convex point pattern at the second end of the TSV region, depositing copper by electrochemical copper plating process, removing excessive copper by chemical mechanical grinding process, and etching SiO2A layer, forming a copper bump at a second end of the TSV region;
s2096, removing the temporarily bonded auxiliary wafer by using a heating mechanical method.
In the method for manufacturing the esd protection device for system in package provided in this embodiment, the periphery of the MOS device is covered by SiO2The process surrounded by the insulating layer can effectively reduce the parasitic capacitance between the active region and the substrate. According to the invention, on the basis of considering process feasibility, the parasitic capacitance and resistance are reduced by optimally setting the TSV holes with a certain length and utilizing the doping concentration in a given range and considering the current passing capacity of the device, and the parasitic capacitance of the device is tuned to a certain degree by utilizing the inductance introduced by the TSV holes, so that the ESD resistance of the system-in-package is improved and the working range of the ESD protection circuit is expanded.
EXAMPLE III
Referring to fig. 3, fig. 3 is a schematic structural diagram of a TSV interposer for system-in-package according to an embodiment of the present invention; in this embodiment, a structure of a TSV interposer is described in detail based on the above embodiments, wherein the TSV interposer is manufactured by the above manufacturing process shown in fig. 2a to fig. 2 i. Specifically, the TSV adapter plate includes:
a Si substrate 301;
a device region 302 disposed within the Si substrate 301;
the TSV region 303 is arranged in the Si substrate 301, is positioned on two sides of the device region 302, and penetrates through the Si substrate 301 up and down;
an interconnection line 304 disposed on the Si substrate 301, for connecting a first end surface of the TSV region 303 and the device region 302;
and a copper bump 305 disposed on the second end surface of the TSV region 303.
Specifically, the device region 302 includes MOS devices and isolation regions; the isolation regions are disposed on two sides of the MOS device and penetrate the Si substrate 301 from top to bottom.
Preferably, the MOS device comprises: the P well region, the gate region, the source region, the drain region and the P well contact region; the gate region is arranged on the P well region, the source region and the drain region are arranged in the P well region and located on two sides of the gate region, and the P well contact region is arranged in the P well region.
Further, the interconnect lines 304 include a first interconnect line and a second interconnect line; the TSV region 303 includes a first TSV region and a second TSV region; the first interconnecting line is used for connecting the first end face of the first TSV region and the source region, and the second interconnecting line is used for connecting the first end face of the second TSV region, the P well contact region, the drain region and the gate region.
Preferably, the depth of the TSV region 303 is 80 μm to 120 μm.
Preferably, the material of the interconnect line 304 is copper.
Specifically, it further includes SiO provided on the upper and lower surfaces of the Si substrate 3012An insulating layer.
The beneficial effects of this embodiment are the same as those described above, and are not described herein again.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For example, the plurality of isolation regions mentioned in the present invention are only illustrated according to the cross-sectional view of the device structure provided in the present invention, wherein the plurality of isolation regions may also be a first portion and a second portion shown in a cross-sectional view of a ring body as a whole, and it should not be limited to these descriptions for a person skilled in the art to which the present invention pertains, and several simple deductions or replacements can be made without departing from the spirit of the present invention, and all of them should be considered as belonging to the protection scope of the present invention.

Claims (8)

1. A preparation method of a TSV adapter plate for system-in-package is characterized by comprising the following steps:
s101, selecting a Si substrate; the doping type of the Si substrate is P type, and the doping concentration is 1 multiplied by 1014～1×1015cm-3The thickness is 150 to 250 μm; the thickness of the isolation region and the TSV region is 80-120 mu m;
s102, preparing TSV and an isolation trench in the Si substrate;
s103, depositing SiO on the Si substrate2Filling the isolation groove to form an isolation region; filling polycrystalline silicon in the TSV, and introducing doping gas to carry out in-situ doping to form a TSV region;
s104, preparing a gate region of the MOS tube on the upper surface of the Si substrate;
s105, preparing a source region and a drain region of the MOS tube by using an ion implantation process; the periphery of the MOS tube is SiO2The insulating layer surrounds the substrate;
s106, preparing an interconnection line between the first end face of the TSV region and the MOS tube on the upper surface of the Si substrate;
and S107, preparing a metal bump on the second end face of the TSV region.
2. The method according to claim 1, wherein S102 comprises:
s1021, forming etching graphs of the TSV and the isolation groove on the upper surface of the Si substrate by utilizing a photoetching process;
and S1022, etching the Si substrate by using a DRIE process to form the TSV and the isolation trench.
3. The method according to claim 1, wherein S103 comprises:
s1031, thermally oxidizing the TSV and the isolation trench to form a first oxidation layer on the inner walls of the TSV and the isolation trench;
s1032, etching the first oxide layer by utilizing a wet etching process to finish the planarization of the TSV and the inner wall of the isolation groove;
s1033, forming a filling pattern of the isolation groove by utilizing a photoetching process;
s1034, filling the first SiO in the isolation trench by using a CVD process2Forming the isolation region of material;
s1035, forming a filling pattern of the TSV by utilizing a photoetching process;
s1036, filling polycrystalline silicon in the TSV by using a CVD (chemical vapor deposition) process, and introducing doping gas to perform in-situ doping to form the TSV region.
4. The method according to claim 1, wherein S104 comprises:
s1041, photoetching a P well region on the Si substrate, and forming the P well by adopting an ion implantation process with glue;
s1042, forming a gate oxide layer on the surface of the Si substrate by using a thermal oxidation process;
s1043, adjusting the threshold voltage by adopting an ion implantation process with glue;
s1044, depositing polycrystalline silicon on the surface of the Si substrate by using a CVD (chemical vapor deposition) process, photoetching a gate electrode pattern, and etching the polycrystalline silicon by using a dry etching process to form a polycrystalline silicon gate;
and S1045, photoetching a gate electrode graph, and doping the polysilicon gate by using a glue ion implantation process to form the gate region.
5. The method according to claim 4, wherein S105 comprises:
s1051, depositing a second SiO on the surface of the Si substrate by using a CVD process2Forming a second oxide layer by using a dry etching process;
s1052, photoetching source region and drain region patterns by adopting an ion implantation tool with glueArt proceeding N+Performing ion implantation, and removing the photoresist to form a source region and a drain region of the MOS tube;
s1053, photoetching a P well contact area pattern, and performing P by adopting a photoresist ion implantation process+And (4) performing ion implantation, removing the photoresist and forming a P well contact region of the MOS tube.
6. The method of claim 1, wherein S107 is preceded by:
x1, using an auxiliary wafer as a support of the upper surface of the Si substrate;
and X2, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process, and then flattening the lower surface of the Si substrate by using a CMP process until the second end face of the TSV region is exposed.
7. The method according to claim 6, wherein S107 comprises:
s1071, forming a liner layer and a barrier layer on the lower surface of the Si substrate by using a sputtering process, and forming a tungsten plug on the second end face of the TSV region by using a CVD process;
s1072, depositing an insulating layer, photoetching a pattern of the metal bump on the second end face of the TSV region, depositing metal by using an electrochemical process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal bump on the second end face of the TSV region;
s1073, removing the auxiliary wafer.
8. A TSV interposer for a system-in-package is prepared by the method of any one of claims 1-7.
CN201711352394.7A 2017-12-15 2017-12-15 TSV adapter plate for system-in-package and preparation method thereof Active CN108063115B (en)

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