CN108061850A - A kind of on piece signal monitoring system - Google Patents
A kind of on piece signal monitoring system Download PDFInfo
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- CN108061850A CN108061850A CN201711370090.3A CN201711370090A CN108061850A CN 108061850 A CN108061850 A CN 108061850A CN 201711370090 A CN201711370090 A CN 201711370090A CN 108061850 A CN108061850 A CN 108061850A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31702—Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a kind of on piece signal monitoring systems.The system includes：Frequency generating circuit, track and hold circuit and 10 analog to digital conversion circuits.The present invention provides a kind of on piece signal monitoring system, on piece monitoring system is arranged on the data signal reception chip that chip transmits chip, and the data-signal of 8Gb/s in chip chamber data transmission interface is monitored；Due to including frequency generating circuit in the present invention, the source synchronous clock in chip data transmission interface is made full use of to generate sampling clock in the course of work, without external equipment additional input sampled clock signal；Track and hold circuit in the present invention has higher bandwidth, can non-delay reception high-speed data signal；10 analog to digital conversion circuits in the present invention are based on assembly line Approach by inchmeal analog to digital conversion circuit structure design, and compared with traditional analog to digital conversion circuit, power consumption is lower；The present invention is arranged on data receiver chip, small, low in energy consumption, and system independence is strong, at low cost, functional.
Description
Technical field
The present invention relates to signal monitoring fields, more particularly relate to a kind of on piece signal monitoring system.
Background technology
As chip constantly promotes the signal transmission rate in chip data transmission interface, to chip chamber transmission signal
Monitoring analysis difficulty also continues to increase, although external monitoring devices are widely adopted in the analysis of chip chamber transmission signal, works as
When inter-chip signals message transmission rate reaches a few giga bits per seconds, the performance and cost of external monitoring devices are all difficult to allow people
It is satisfied.
In conclusion being monitored in the prior art using external monitoring devices to chip chamber transmission signal, exist when number
According to transmission rate it is higher when, external monitoring devices poor performance and it is of high cost the problem of.
The content of the invention
The embodiment of the present invention provides a kind of on piece signal monitoring system, works as data transmission to solve to exist in the prior art
When rate is higher, external monitoring devices poor performance and it is of high cost the problem of.
The embodiment of the present invention provides a kind of on piece signal monitoring system, including：Frequency generating circuit, track and hold circuit and
10 analog to digital conversion circuits；
The frequency generating circuit is using the 2GHz source synchronous clock signals clock in chip chamber data transmission interface as defeated
Enter information, and the sampled clock signal sclk of frequency generating circuit output 127.5MHz；
The track and hold circuit, including：Sampling module and compensating module；The non-delay reception of track and hold circuit
The high-speed data signal of 8Gb/s, and the sampled clock signal sclk based on 127.5MHz exports chip chamber data transmission interface
Differential data signals sinp and sinm sampled；
10 analog to digital conversion circuits receive the sampled analogue signals samp and samm of the track and hold circuit output,
And sampled analogue signals samp and samm are converted into 10 position digital signal datas outputs.
Preferably, the digital signal datas is shown and is analyzed by digital waveform instrument.
Preferably, the sampling module, including：Metal-oxide-semiconductor M1 to M17, holding capacitor C1 and C2, resistance R1 and R2, sampling
Clock signal receiving port SCLK1 and SCLK2, reverse phase sampled clock signal receiving port SCLKB1 to SCLKB6, bias current
Input port B IAS, positive data signal input mouth SINP, anti-phase data signal input port SINM, positive signal output part
Mouth OUTP and inversion signal output port OUTM.
Preferably, the source electrode connection power supply of metal-oxide-semiconductor M1, the source electrode of the grid connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M1, metal-oxide-semiconductor M1's
The drain electrode of drain electrode connection metal-oxide-semiconductor M2；Grid connection reverse phase sampled clock signal the receiving port SCLKB1, metal-oxide-semiconductor M2 of metal-oxide-semiconductor M2
Source electrode connection metal-oxide-semiconductor M5 drain electrode；Under upper end connection positive the signal output port OUTP, holding capacitor C1 of holding capacitor C1
End ground connection；The drain electrode of the grid connection metal-oxide-semiconductor M6 of source electrode connection the power supply VCC, metal-oxide-semiconductor M4 of metal-oxide-semiconductor M4, the drain electrode of metal-oxide-semiconductor M4
Connect the source electrode of metal-oxide-semiconductor M3；The drain electrode of grid connection sampled clock signal the receiving port SCLK1, metal-oxide-semiconductor M3 of metal-oxide-semiconductor M3 connect
Connect the drain electrode of metal-oxide-semiconductor M5；The grid of the grid connection metal-oxide-semiconductor M9 of metal-oxide-semiconductor M5, the source electrode ground connection of metal-oxide-semiconductor M5；The source of metal-oxide-semiconductor M7
The lower end of pole connection resistance R1, the grid connection reverse phase sampled clock signal receiving port SCLKB2 of metal-oxide-semiconductor M7, metal-oxide-semiconductor M7's
The grid of drain electrode connection metal-oxide-semiconductor M4；The drain electrode of the drain electrode connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M6, the grid connection reverse phase of metal-oxide-semiconductor M6 are adopted
The source electrode ground connection of sample clock signal receiving port SCLKB3, metal-oxide-semiconductor M6；Under upper end connection the power supply VCC, resistance R1 of resistance R1
The source electrode of end connection metal-oxide-semiconductor M8；The drain electrode of grid connection anti-phase data signal the input port SINM, metal-oxide-semiconductor M8 of metal-oxide-semiconductor M8 connect
Connect the drain electrode of metal-oxide-semiconductor M9；The source electrode of the lower end connection metal-oxide-semiconductor M10 of upper end connection the power supply VCC, resistance R2 of resistance R2；Metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M9 of grid connection positive data signal input the mouth SINP, metal-oxide-semiconductor M10 of M10；Metal-oxide-semiconductor M9
Grid connection metal-oxide-semiconductor M15 grid, the source electrode ground connection of metal-oxide-semiconductor M9；The lower end of the source electrode connection resistance R2 of metal-oxide-semiconductor M11, MOS
The leakage of the drain electrode connection metal-oxide-semiconductor M12 of grid connection reverse phase sampled clock signal the receiving port SCLKB4, metal-oxide-semiconductor M11 of pipe M11
Pole；The source electrode ground connection of grid connection reverse phase sampled clock signal the receiving port SCLKB5, metal-oxide-semiconductor M12 of metal-oxide-semiconductor M12；Metal-oxide-semiconductor
The drain electrode of the grid connection metal-oxide-semiconductor M11 of source electrode connection the power supply VCC, metal-oxide-semiconductor M13 of M13, metal-oxide-semiconductor M13 drain electrode connection metal-oxide-semiconductors
The source electrode of M14；The drain electrode connection metal-oxide-semiconductor of grid connection sampled clock signal the receiving port SCLK2, metal-oxide-semiconductor M14 of metal-oxide-semiconductor M14
The drain electrode of M15；The source electrode ground connection of grid connection bias current inputs the mouth BIAS, metal-oxide-semiconductor M15 of metal-oxide-semiconductor M15；Metal-oxide-semiconductor M16
Source electrode connection power supply VCC, metal-oxide-semiconductor M16 grid connection metal-oxide-semiconductor M11 source electrode, the drain electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M16
Drain electrode；The source electrode connection MOS of grid connection reverse phase sampled clock signal the receiving port SCLKB6, metal-oxide-semiconductor M17 of metal-oxide-semiconductor M17
The drain electrode of pipe M15；The lower end ground connection of upper end connection inversion signal the output port OUTM, holding capacitor C2 of holding capacitor C2.
Preferably, the compensating module include metal-oxide-semiconductor M8 to M24, resistance R3 and R4, positive signal input port INP, instead
Phase signals input port INM, bias current inputs mouth BIAS, positive sampled signal output port SAMP, reverse phase sampled signal
Output port SAMM.
Preferably, the source electrode of the lower end connection metal-oxide-semiconductor M18 of upper end connection the power supply VCC, resistance R3 of resistance R3；Metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M20 of grid connection positive the signal input port INP, metal-oxide-semiconductor M18 of M18；Resistance R4's is upper
The source electrode of the lower end connection metal-oxide-semiconductor M19 of end connection power supply VCC, resistance R4；The grid connection inversion signal input terminal of metal-oxide-semiconductor M19
The drain electrode of the drain electrode connection metal-oxide-semiconductor M20 of mouth INM, metal-oxide-semiconductor M19；The grid connection bias current inputs mouth of metal-oxide-semiconductor M20
The source electrode ground connection of BIAS, metal-oxide-semiconductor M20；The grid connection resistance R3's of source electrode connection the power supply VCC, metal-oxide-semiconductor M21 of metal-oxide-semiconductor M21
Lower end, the drain electrode of the drain electrode connection metal-oxide-semiconductor M22 of metal-oxide-semiconductor M21；The drain electrode connection reverse phase sampled signal output port of metal-oxide-semiconductor M22
The grid of the grid connection metal-oxide-semiconductor M20 of SAMM, metal-oxide-semiconductor M22, the source electrode ground connection of metal-oxide-semiconductor M22；The source electrode connection electricity of metal-oxide-semiconductor M23
The lower end of the grid connection resistance R4 of source VCC, metal-oxide-semiconductor M23, the drain electrode of the drain electrode connection metal-oxide-semiconductor M24 of metal-oxide-semiconductor M23；Metal-oxide-semiconductor
The grid of the grid connection metal-oxide-semiconductor M22 of drain electrode connection positive sampled signal the output port SAMP, metal-oxide-semiconductor M24 of M24, metal-oxide-semiconductor
The source electrode ground connection of M24.
Preferably, 10 analog to digital conversion circuits, including：5 bit stream pipeline analog-to-digital converters, 6 bit stream waterline moduluses turn
Parallel operation, residue amplifier and digital encoder.
Preferably, positive sampled analogue signals samp and reverse phase sampled analogue signals samm is input to 5 bit stream waterlines simultaneously
In analog-digital converter and 6 bit stream pipeline analog-to-digital converters；5 bit stream pipeline analog-to-digital converters export 5 sampled digital signals
Data5,6 bit stream pipeline analog-to-digital converters export 6 sampled digital signal data6；5 sampled digital signal data5 are adopted with 6
Sample digital signal data6 is input in digital encoder simultaneously；Digital encoder is generated by two production line analog-digital converters
1 redundant code sampled digital signal is corrected, and export 10 sampled digital signal datas.
In the embodiment of the present invention, a kind of on piece signal monitoring system is provided, compared with prior art, its advantage is such as
Under：
The present invention provides a kind of on piece signal monitoring system, on piece monitoring system is arranged at the number that chip transmits chip
According on signal receiving chip, and the data-signal of 8Gb/s in chip chamber data transmission interface is monitored；Due in the present invention
Comprising frequency generating circuit, when the source synchronous clock generation sampling in chip data transmission interface is made full use of in the course of work
Clock, without external equipment additional input sampled clock signal；Track and hold circuit in the present invention has higher bandwidth, Ke Yiwu
Delay receives high-speed data signal；10 analog to digital conversion circuits in the present invention are based on assembly line Approach by inchmeal analog to digital conversion circuit
Structure design, compared with traditional analog to digital conversion circuit, power consumption is lower；The present invention is arranged on data receiver chip, small, work(
Consume low, system independence is strong, at low cost, functional.
Description of the drawings
Fig. 1 is a kind of on piece signal monitoring system principle diagram provided in an embodiment of the present invention；
Fig. 2 is the sampling module electricity of track and hold circuit in a kind of on piece signal monitoring system provided in an embodiment of the present invention
Lu Tu；
Fig. 3 is the compensating module electricity of track and hold circuit in a kind of on piece signal monitoring system provided in an embodiment of the present invention
Lu Tu；
Fig. 4 is 10 analog to digital conversion circuit structure charts in a kind of on piece signal monitoring system provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment belongs to the scope of protection of the invention.
It should be noted that when a certain element is fixed on another element, it is another including the element is directly fixed on this
The element is fixed on another element by a element by least one other elements placed in the middle.When an element connects
Another element is connect, including the element is directly connected to another element or is passed through the element at least one placed in the middle
Other elements be connected to another element.
Fig. 1 is a kind of on piece signal monitoring system principle diagram provided in an embodiment of the present invention.As shown in Figure 1, the system
Including：Frequency generating circuit, track and hold circuit and 10 analog to digital conversion circuits.
Specifically, the frequency generating circuit is by the 2GHz source synchronous clock signals in chip chamber data transmission interface
Clock is as input information, and the frequency generating circuit exports the sampled clock signal sclk of 127.5MHz；The tracking is protected
Circuit is held, including：Sampling module and compensating module；The non-delay high-speed data signal for receiving 8Gb/s of the track and hold circuit,
And the differential data signals sinp that export to chip chamber data transmission interface of the sampled clock signal sclk based on 127.5MHz and
Sinm is sampled；10 analog to digital conversion circuits receive the track and hold circuit output sampled analogue signals samp and
Samm, and sampled analogue signals samp and samm are converted into 10 position digital signal datas outputs；The digital signal datas
It shows and analyzes by digital waveform instrument.
It should be noted that on piece monitoring system is arranged on the data signal reception chip that chip transmits chip, and
The data-signal of 8Gb/s in chip chamber data transmission interface is monitored.The frequency generating circuit of on piece monitoring system is by core
2GHz source synchronous clock signals clock between piece in data transmission interface exports the sampling clock of 127.5MHz as input
Signal sclk provides additional clock signals input without external equipment.Track and hold circuit has higher bandwidth, can be without prolonging
The high-speed data signal of 8Gb/s is received late, and based on the sampled clock signal of 127.5MHz to input difference data-signal sinp
And sinm is sampled.10 analog to digital conversion circuits receive the sampled analogue signals samp and samm of track and hold circuit output,
And it is converted into 10 position digital signal datas.The digital signal datas of 10 analog to digital conversion circuit outputs passes through digital waveform
Instrument shows and analyzes.
Further, the track and hold circuit in a kind of on piece signal monitoring system provided by the invention include sampling module and
Compensating module；Sampling module is with the non-delay 8Gb/s high speed differential data signals for receiving chip interface input of the bandwidth of 4GHz
Sinp and sinm, and input data signal is sampled according to sample clock frequency；Compensating module obtains sampling module
Sampled data signal compensates amplification, and sampled data signal samp and samm is driven to be input to 10 analog to digital conversion circuits
In.
Fig. 2 is the sampling module electricity of track and hold circuit in a kind of on piece signal monitoring system provided in an embodiment of the present invention
Lu Tu；As shown in Fig. 2, the sampling module, including：Metal-oxide-semiconductor M1 to M17, holding capacitor C1 and C2, resistance R1 and R2, sampling
Clock signal receiving port SCLK1 and SCLK2, reverse phase sampled clock signal receiving port SCLKB1 to SCLKB6, bias current
Input port B IAS, positive data signal input mouth SINP, anti-phase data signal input port SINM, positive signal output part
Mouth OUTP and inversion signal output port OUTM.
Specifically, the source electrode connection power supply of metal-oxide-semiconductor M1, the source electrode of the grid connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M1, metal-oxide-semiconductor M1's
The drain electrode of drain electrode connection metal-oxide-semiconductor M2；Grid connection reverse phase sampled clock signal the receiving port SCLKB1, metal-oxide-semiconductor M2 of metal-oxide-semiconductor M2
Source electrode connection metal-oxide-semiconductor M5 drain electrode；Under upper end connection positive the signal output port OUTP, holding capacitor C1 of holding capacitor C1
End ground connection；The drain electrode of the grid connection metal-oxide-semiconductor M6 of source electrode connection the power supply VCC, metal-oxide-semiconductor M4 of metal-oxide-semiconductor M4, the drain electrode of metal-oxide-semiconductor M4
Connect the source electrode of metal-oxide-semiconductor M3；The drain electrode of grid connection sampled clock signal the receiving port SCLK1, metal-oxide-semiconductor M3 of metal-oxide-semiconductor M3 connect
Connect the drain electrode of metal-oxide-semiconductor M5；The grid of the grid connection metal-oxide-semiconductor M9 of metal-oxide-semiconductor M5, the source electrode ground connection of metal-oxide-semiconductor M5；The source of metal-oxide-semiconductor M7
The lower end of pole connection resistance R1, the grid connection reverse phase sampled clock signal receiving port SCLKB2 of metal-oxide-semiconductor M7, metal-oxide-semiconductor M7's
The grid of drain electrode connection metal-oxide-semiconductor M4；The drain electrode of the drain electrode connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M6, the grid connection reverse phase of metal-oxide-semiconductor M6 are adopted
The source electrode ground connection of sample clock signal receiving port SCLKB3, metal-oxide-semiconductor M6；Under upper end connection the power supply VCC, resistance R1 of resistance R1
The source electrode of end connection metal-oxide-semiconductor M8；The drain electrode of grid connection anti-phase data signal the input port SINM, metal-oxide-semiconductor M8 of metal-oxide-semiconductor M8 connect
Connect the drain electrode of metal-oxide-semiconductor M9；The source electrode of the lower end connection metal-oxide-semiconductor M10 of upper end connection the power supply VCC, resistance R2 of resistance R2；Metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M9 of grid connection positive data signal input the mouth SINP, metal-oxide-semiconductor M10 of M10；Metal-oxide-semiconductor M9
Grid connection metal-oxide-semiconductor M15 grid, the source electrode ground connection of metal-oxide-semiconductor M9；The lower end of the source electrode connection resistance R2 of metal-oxide-semiconductor M11, MOS
The leakage of the drain electrode connection metal-oxide-semiconductor M12 of grid connection reverse phase sampled clock signal the receiving port SCLKB4, metal-oxide-semiconductor M11 of pipe M11
Pole；The source electrode ground connection of grid connection reverse phase sampled clock signal the receiving port SCLKB5, metal-oxide-semiconductor M12 of metal-oxide-semiconductor M12；Metal-oxide-semiconductor
The drain electrode of the grid connection metal-oxide-semiconductor M11 of source electrode connection the power supply VCC, metal-oxide-semiconductor M13 of M13, metal-oxide-semiconductor M13 drain electrode connection metal-oxide-semiconductors
The source electrode of M14；The drain electrode connection metal-oxide-semiconductor of grid connection sampled clock signal the receiving port SCLK2, metal-oxide-semiconductor M14 of metal-oxide-semiconductor M14
The drain electrode of M15；The source electrode ground connection of grid connection bias current inputs the mouth BIAS, metal-oxide-semiconductor M15 of metal-oxide-semiconductor M15；Metal-oxide-semiconductor M16
Source electrode connection power supply VCC, metal-oxide-semiconductor M16 grid connection metal-oxide-semiconductor M11 source electrode, the drain electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M16
Drain electrode；The source electrode connection MOS of grid connection reverse phase sampled clock signal the receiving port SCLKB6, metal-oxide-semiconductor M17 of metal-oxide-semiconductor M17
The drain electrode of pipe M15；The lower end ground connection of upper end connection inversion signal the output port OUTM, holding capacitor C2 of holding capacitor C2.
It should be noted that metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 forms the virtual source follower of reverse phase.Metal-oxide-semiconductor M3, metal-oxide-semiconductor M4 and
Metal-oxide-semiconductor M5 forms reverse phase source follower.Resistance R1, resistance R2, metal-oxide-semiconductor M8, metal-oxide-semiconductor M9 and metal-oxide-semiconductor M10 form differential amplification
Device.Metal-oxide-semiconductor M13, metal-oxide-semiconductor M14 and metal-oxide-semiconductor M15 form positive source follower.It is empty that metal-oxide-semiconductor M16 and metal-oxide-semiconductor M17 forms positive
Intend source follower.When sampled clock signal sclk is high level, difference amplifier driving data input signal enters holding
Capacitance, circuit are in tracking mode.When sampled clock signal sclk is low level, virtual source follower is open-minded, to ensure
The biasing circuit normal work of source follower, circuit, which is in, keeps sample states.Sampling module leads to the data-signal of holding
Cross positive signal output port OUTP and inversion signal output port OUTM outputs.
Fig. 3 is the compensating module electricity of track and hold circuit in a kind of on piece signal monitoring system provided in an embodiment of the present invention
Lu Tu；As shown in figure 3, the compensating module include metal-oxide-semiconductor M8 to M24, resistance R3 and R4, positive signal input port INP, instead
Phase signals input port INM, bias current inputs mouth BIAS, positive sampled signal output port SAMP, reverse phase sampled signal
Output port SAMM.
Specifically, the source electrode of the lower end connection metal-oxide-semiconductor M18 of upper end connection the power supply VCC, resistance R3 of resistance R3；Metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M20 of grid connection positive the signal input port INP, metal-oxide-semiconductor M18 of M18；Resistance R4's is upper
The source electrode of the lower end connection metal-oxide-semiconductor M19 of end connection power supply VCC, resistance R4；The grid connection inversion signal input terminal of metal-oxide-semiconductor M19
The drain electrode of the drain electrode connection metal-oxide-semiconductor M20 of mouth INM, metal-oxide-semiconductor M19；The grid connection bias current inputs mouth of metal-oxide-semiconductor M20
The source electrode ground connection of BIAS, metal-oxide-semiconductor M20；The grid connection resistance R3's of source electrode connection the power supply VCC, metal-oxide-semiconductor M21 of metal-oxide-semiconductor M21
Lower end, the drain electrode of the drain electrode connection metal-oxide-semiconductor M22 of metal-oxide-semiconductor M21；The drain electrode connection reverse phase sampled signal output port of metal-oxide-semiconductor M22
The grid of the grid connection metal-oxide-semiconductor M20 of SAMM, metal-oxide-semiconductor M22, the source electrode ground connection of metal-oxide-semiconductor M22；The source electrode connection electricity of metal-oxide-semiconductor M23
The lower end of the grid connection resistance R4 of source VCC, metal-oxide-semiconductor M23, the drain electrode of the drain electrode connection metal-oxide-semiconductor M24 of metal-oxide-semiconductor M23；Metal-oxide-semiconductor
The grid of the grid connection metal-oxide-semiconductor M22 of drain electrode connection positive sampled signal the output port SAMP, metal-oxide-semiconductor M24 of M24, metal-oxide-semiconductor
The source electrode ground connection of M24.
It should be noted that resistance R3, resistance R4, metal-oxide-semiconductor M18, metal-oxide-semiconductor M19 and metal-oxide-semiconductor M20 form difference amplifier.
Metal-oxide-semiconductor M21 and metal-oxide-semiconductor M22 forms No. 1 single-ended source follower.Metal-oxide-semiconductor M23 and metal-oxide-semiconductor M24 forms No. 2 single-ended sources and follows
Device.When sampling module exports sampled signal according to sample clock frequency, compensating module by positive signal input port INP and
Inversion signal input port INM receives sampled signal, and sampled signal is amplified, and is designed with compensating sampling module high bandwidth
Caused by signal gain lose.After sampled signal amplification, compensating module driving sampled data signal is defeated by positive sampled signal
Exit port SAMP and reverse phase sampled signal output port SAMM are input in 10 analog to digital conversion circuits.
Fig. 4 is 10 analog to digital conversion circuit structure charts in a kind of on piece signal monitoring system provided in an embodiment of the present invention；
As shown in figure 4,10 analog to digital conversion circuits, including：5 bit stream pipeline analog-to-digital converters, 6 bit stream pipeline analog-to-digital converters,
Residue amplifier and digital encoder.
Specifically, positive sampled analogue signals samp and reverse phase sampled analogue signals samm is input to 5 bit stream waterlines simultaneously
In analog-digital converter and 6 bit stream pipeline analog-to-digital converters；5 bit stream pipeline analog-to-digital converters export 5 sampled digital signals
Data5,6 bit stream pipeline analog-to-digital converters export 6 sampled digital signal data6；5 sampled digital signal data5 are adopted with 6
Sample digital signal data6 is input in digital encoder simultaneously；Digital encoder is generated by two production line analog-digital converters
1 redundant code sampled digital signal is corrected, and export 10 sampled digital signal datas.
It should be noted that 10 analog to digital conversion circuits are realized together by sampled clock signal sclk and track and hold circuit
Step, and sampled analogue signals are converted into digital signal.When sampled clock signal sclk is high level, track and hold circuit obtains
It takes and keeps the sample magnitude of analog input signal, while sampled analogue signals are converted to digital letter by 10 analog to digital conversion circuits
Number output.When sampled clock signal sclk is low level, residue amplifier in 10 analog to digital conversion circuits is by 5 bit stream waterlines
The residual error voltage amplification that analog-digital converter provides resets 10 analog to digital conversion circuits.
In addition, a kind of on piece signal monitoring system provided in an embodiment of the present invention is designed based on 65nm CMOS technologies, frequency
It is 0.1872mm2 that circuit chip area occupied, which occurs, for rate, and track and hold circuit chip area footprints are 0.0152mm2,10 moulds
Number conversion circuit chip area footprints are 0.2368mm2.The capacitance of holding capacitor C1 is 300pF.The capacitance of holding capacitor C2
It is worth for 300pF.The resistance value of resistance R1 is 5.6k Ω.The resistance value of resistance R2 is 5.6k Ω.The resistance value of resistance R3 is 750 Ω.Resistance
The resistance value of R4 is 750 Ω.Working power VCC voltages are 1.2V.Frequency generating circuit power consumption is 6.6mW.Track and hold circuit work(
It consumes for 15.3mW.10 analog to digital conversion circuit power consumptions are 8mW.Chip believes the source synchronous clock of chip high speed data transmission interface
Number clock frequencies are 2GHz.The sampled clock signal sclk frequencies of frequency generating circuit output are 127.5MHz.Chip is to chip
The signal transmission rate of high speed data transmission interface is 8Gb/s.The bandwidth of operation of track and hold circuit is 4GHz.On piece signal is supervised
The sampled digital signal precision of examining system output is 10.
In conclusion the present invention provides a kind of on piece signal monitoring system, on piece monitoring system is arranged at chip to core
On the data signal reception chip of piece transmission, and the data-signal of 8Gb/s in chip chamber data transmission interface is monitored；By
Frequency generating circuit is included in the present invention, in the course of work source synchronous clock in chip data transmission interface is made full use of to produce
Raw sampling clock, without external equipment additional input sampled clock signal；Track and hold circuit in the present invention has higher band
Width, can non-delay reception high-speed data signal；10 analog to digital conversion circuits in the present invention are based on assembly line Approach by inchmeal mould
Number converting circuit structure design, compared with traditional analog to digital conversion circuit, power consumption is lower；The present invention is arranged at data receiver chip
On, small, low in energy consumption, system independence is strong, at low cost, functional.
Disclosed above is only several specific embodiments of the present invention, and those skilled in the art can carry out the present invention
Various modification and variations without departing from the spirit and scope of the present invention, if these modifications and changes of the present invention belong to the present invention
Within the scope of claim and its equivalent technologies, then the present invention is also intended to comprising including these modification and variations.
Claims (8)
1. a kind of on piece signal monitoring system, which is characterized in that including：Frequency generating circuit, track and hold circuit and 10 moulds
Number conversion circuit；
The frequency generating circuit is believed the 2GHz source synchronous clock signal clock in chip chamber data transmission interface as input
Breath, and the sampled clock signal sclk of frequency generating circuit output 127.5MHz；
The track and hold circuit, including：Sampling module and compensating module；The non-delay reception 8Gb/s of track and hold circuit
High-speed data signal, and the difference that the sampled clock signal sclk based on 127.5MHz exports chip chamber data transmission interface
Data-signal sinp and sinm are sampled；
10 analog to digital conversion circuits receive the sampled analogue signals samp and samm of the track and hold circuit output, and will
Sampled analogue signals samp and samm are converted to 10 position digital signal datas outputs.
2. on piece signal monitoring system as described in claim 1, which is characterized in that the digital signal datas passes through number
Waveform instrument shows and analyzes.
3. on piece signal monitoring system as described in claim 1, which is characterized in that the sampling module, including：Metal-oxide-semiconductor M1
To M17, holding capacitor C1 and C2, resistance R1 and R2, sampled clock signal receiving port SCLK1 and SCLK2, reverse phase sampling clock
Receiver port SCLKB1 to SCLKB6, bias current inputs mouth BIAS, positive data signal input mouth SINP, reverse phase
Data signal input mouth SINM, positive signal output port OUTP and inversion signal output port OUTM.
4. on piece signal monitoring system as claimed in claim 3, which is characterized in that
The source electrode connection power supply of metal-oxide-semiconductor M1, the source electrode of the grid connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M1, the drain electrode connection MOS of metal-oxide-semiconductor M1
The drain electrode of pipe M2；The source electrode connection of grid connection reverse phase sampled clock signal the receiving port SCLKB1, metal-oxide-semiconductor M2 of metal-oxide-semiconductor M2
Metal-oxide-semiconductor M5 drains；The lower end ground connection of upper end connection positive the signal output port OUTP, holding capacitor C1 of holding capacitor C1；MOS
The drain electrode of the grid connection metal-oxide-semiconductor M6 of source electrode connection the power supply VCC, metal-oxide-semiconductor M4 of pipe M4, the drain electrode connection metal-oxide-semiconductor M3 of metal-oxide-semiconductor M4
Source electrode；The drain electrode connection metal-oxide-semiconductor M5's of grid connection sampled clock signal the receiving port SCLK1, metal-oxide-semiconductor M3 of metal-oxide-semiconductor M3
Drain electrode；The grid of the grid connection metal-oxide-semiconductor M9 of metal-oxide-semiconductor M5, the source electrode ground connection of metal-oxide-semiconductor M5；The source electrode connection resistance R1 of metal-oxide-semiconductor M7
Lower end, the drain electrode connection metal-oxide-semiconductor of the grid connection reverse phase sampled clock signal receiving port SCLKB2, metal-oxide-semiconductor M7 of metal-oxide-semiconductor M7
The grid of M4；The drain electrode of the drain electrode connection metal-oxide-semiconductor M7 of metal-oxide-semiconductor M6, the grid connection reverse phase sampled clock signal of metal-oxide-semiconductor M6 receive
The source electrode ground connection of port SCLKB3, metal-oxide-semiconductor M6；The lower end connection metal-oxide-semiconductor M8 of upper end connection the power supply VCC, resistance R1 of resistance R1
Source electrode；The leakage of the drain electrode connection metal-oxide-semiconductor M9 of grid connection anti-phase data signal the input port SINM, metal-oxide-semiconductor M8 of metal-oxide-semiconductor M8
Pole；The source electrode of the lower end connection metal-oxide-semiconductor M10 of upper end connection the power supply VCC, resistance R2 of resistance R2；The grid connection of metal-oxide-semiconductor M10
The drain electrode of the drain electrode connection metal-oxide-semiconductor M9 of positive data signal input mouth SINP, metal-oxide-semiconductor M10；The grid connection MOS of metal-oxide-semiconductor M9
The grid of pipe M15, the source electrode ground connection of metal-oxide-semiconductor M9；The lower end of the source electrode connection resistance R2 of metal-oxide-semiconductor M11, the grid of metal-oxide-semiconductor M11 connect
The drain electrode of the drain electrode connection metal-oxide-semiconductor M12 of reversed phase sampled clock signal receiving port SCLKB4, metal-oxide-semiconductor M11；Metal-oxide-semiconductor M12's
The source electrode ground connection of grid connection reverse phase sampled clock signal receiving port SCLKB5, metal-oxide-semiconductor M12；The source electrode connection of metal-oxide-semiconductor M13
The drain electrode of the grid connection metal-oxide-semiconductor M11 of power supply VCC, metal-oxide-semiconductor M13, the source electrode of metal-oxide-semiconductor M13 drain electrode connection metal-oxide-semiconductors M14；Metal-oxide-semiconductor
The drain electrode of the drain electrode connection metal-oxide-semiconductor M15 of grid connection sampled clock signal the receiving port SCLK2, metal-oxide-semiconductor M14 of M14；Metal-oxide-semiconductor
The source electrode ground connection of grid connection bias current inputs the mouth BIAS, metal-oxide-semiconductor M15 of M15；The source electrode connection power supply of metal-oxide-semiconductor M16
The source electrode of the grid connection metal-oxide-semiconductor M11 of VCC, metal-oxide-semiconductor M16, the drain electrode of the drain electrode connection metal-oxide-semiconductor M17 of metal-oxide-semiconductor M16；Metal-oxide-semiconductor
The drain electrode of the source electrode connection metal-oxide-semiconductor M15 of grid connection reverse phase sampled clock signal the receiving port SCLKB6, metal-oxide-semiconductor M17 of M17；
The lower end ground connection of upper end connection inversion signal the output port OUTM, holding capacitor C2 of holding capacitor C2.
5. on piece signal monitoring system as described in claim 1, which is characterized in that the compensating module includes metal-oxide-semiconductor M8 extremely
M24, resistance R3 and R4, positive signal input port INP, inversion signal input port INM, bias current inputs mouth BIAS,
Positive sampled signal output port SAMP, reverse phase sampled signal output port SAMM.
6. on piece signal monitoring system as claimed in claim 5, which is characterized in that
The source electrode of the lower end connection metal-oxide-semiconductor M18 of upper end connection the power supply VCC, resistance R3 of resistance R3；The grid connection of metal-oxide-semiconductor M18
The drain electrode of the drain electrode connection metal-oxide-semiconductor M20 of positive signal input port INP, metal-oxide-semiconductor M18；The upper end connection power supply VCC of resistance R4,
The source electrode of the lower end connection metal-oxide-semiconductor M19 of resistance R4；Grid connection inversion signal the input port INM, metal-oxide-semiconductor M19 of metal-oxide-semiconductor M19
Drain electrode connection metal-oxide-semiconductor M20 drain electrode；The grid connection bias current inputs mouth BIAS of metal-oxide-semiconductor M20, the source of metal-oxide-semiconductor M20
Pole is grounded；The lower end of the grid connection resistance R3 of source electrode connection the power supply VCC, metal-oxide-semiconductor M21 of metal-oxide-semiconductor M21, the leakage of metal-oxide-semiconductor M21
The drain electrode of pole connection metal-oxide-semiconductor M22；The drain electrode connection reverse phase sampled signal output port SAMM of metal-oxide-semiconductor M22, the grid of metal-oxide-semiconductor M22
The grid of pole connection metal-oxide-semiconductor M20, the source electrode ground connection of metal-oxide-semiconductor M22；The source electrode connection power supply VCC of metal-oxide-semiconductor M23, metal-oxide-semiconductor M23's
The lower end of grid connection resistance R4, the drain electrode of the drain electrode connection metal-oxide-semiconductor M24 of metal-oxide-semiconductor M23；The drain electrode connection positive of metal-oxide-semiconductor M24
The grid of the grid connection metal-oxide-semiconductor M22 of sampled signal output port SAMP, metal-oxide-semiconductor M24, the source electrode ground connection of metal-oxide-semiconductor M24.
7. on piece signal monitoring system as described in claim 1, which is characterized in that 10 analog to digital conversion circuits, including：
5 bit stream pipeline analog-to-digital converters, 6 bit stream pipeline analog-to-digital converters, residue amplifier and digital encoder.
8. on piece signal monitoring system as claimed in claim 7, which is characterized in that
Positive sampled analogue signals samp and reverse phase sampled analogue signals samm be input to simultaneously 5 bit stream pipeline analog-to-digital converters and
In 6 bit stream pipeline analog-to-digital converters；5 bit stream pipeline analog-to-digital converters export 5 sampled digital signal data5,6 bit stream waterline moulds
Number converter exports 6 sampled digital signal data6；5 sampled digital signal data5 and 6 sampled digital signal data6 are same
When be input in digital encoder；Digital encoder is by 1 redundant code that two production line analog-digital converters generate to sampling
Digital signal is corrected, and exports 10 sampled digital signal datas.
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