CN108055202A - A kind of message processor and method - Google Patents
A kind of message processor and method Download PDFInfo
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- CN108055202A CN108055202A CN201711288346.6A CN201711288346A CN108055202A CN 108055202 A CN108055202 A CN 108055202A CN 201711288346 A CN201711288346 A CN 201711288346A CN 108055202 A CN108055202 A CN 108055202A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/66—Layer 2 routing, e.g. in Ethernet based MAN's
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a kind of message processor and method, for the processing by carrying out message based on CPU+FPGA heterogeneous systems.The equipment includes central processor CPU and at least one on-site programmable gate array FPGA；The list item configuration information for configuring the list item for configuring list item for FPGA, and is sent to the FPGA by the CPU；The storage address of the list item is carried in the list item configuration information；At least one FPGA, for receiving the list item configuration information and clear text, intercept the header field of the clear text, and the keyword tabled look-up is extracted from header field, it is tabled look-up according to the list item that the keyword and the storage address store, the clear text is handled according to checking result, it will treated message is sent to equipment corresponding with treated the message；Wherein, the keyword is corresponding with the list item that the storage address stores.
Description
Technical field
The present invention relates to network technique field, more particularly to a kind of message processor and method.
Background technology
At present, the framework of the network equipment is mainly integrated circuit (Application Specific Integrated
Circuit, ASIC) framework or for based on special network processor (Network Processor, NP) framework or be base
In multi-core central processing unit (Central Processing Unit, CPU) framework.
Wherein, ASIC frameworks are since just for specific business scenario, function is comparatively fixed, therefore performance is higher,
But also just because of the relatively cured characteristic of function, the programmability of ASIC frameworks is not high, can not meet the needs of changeable business.
And NP frameworks are made of multiple microcode processors and multiple hardware co-processors, multiple microcode processors are in internal parallel fortune
Row by microcode (microcode) prepared in advance come control process flow, therefore has stronger programmability, but valency
Lattice are costly.In addition, multiple nuclear CPU framework can realize business function on multi-core CPU using software programming, have very strong
Programmability, but the performance of multiple nuclear CPU framework compares other frameworks and is in inferior position.Therefore, the frame of the current network equipment
Structure it is more or less all there are this some defect so that being based on field programmable gate array (Field-
Programmable Gete Array, FPGA) framework gradually starts to be used.Wherein, FPGA has extremely strong programmability,
And also there is very strong advantage in time delay, throughput etc..But at present for the network equipment of FPGA architecture, there is no one
The general development model of kind or relatively fixed network message processing method, so it is all to redesign to develop ninety-nine times out of a hundred,
And module interface is different, and reusability is low, only when developer is familiar with processing frame, Message processing logic
Energy complete design, and for only needing to verify some algorithm, the agreement even developer of some cell processing logic,
Building complete network message processing frame needs to consume the substantial amounts of time, and development efficiency is low.
The content of the invention
The embodiment of the present invention provides a kind of message processor and method, for by be based on CPU+FPGA heterogeneous systems into
The processing of row message.
In a first aspect, providing a kind of message processor, which includes central processor CPU and at least one scene can
Program gate array FPGA；
The list item configuration information for configuring the list item for configuring list item for the FPGA, and is sent to institute by the CPU
State FPGA；The storage address of the list item is carried in the list item configuration information；
At least one FPGA, for receiving the list item configuration information and clear text, interception is described pending
The header field of message, and extracted from the header field for the keyword tabled look-up, according to the keyword
And the list item of the storage address storage is tabled look-up, and the clear text is handled according to checking result, will be located
Message after reason is sent to equipment corresponding with treated the message；Wherein, the keyword is deposited with the storage address
The list item of storage is corresponding.
Optionally, any one FPGA includes multiple functional units, the multiple function list at least one FPGA
Member specifically includes：
Message receives RX units, for receiving clear text；
Message bag splits Decap units, for intercepting the header field of the clear text, and waits to locate by described
Other fields in reason message in addition to the header field are sent to the packet buffer that the FPGA includes
PacketBuffer units are stored；
Packet parsing Parser units, for determining the type of the clear text according to the header field,
When it is protocol massages that definitive result, which shows the clear text, then transmitted to CPU mark is added in the header field
Will；Wherein, the transmitted to CPU mark demonstrates the need for the clear text being sent to the CPU；
Keyword extraction Fetch units, for extracting the keyword in the header field；
It tables look-up engine unit, for being tabled look-up according to the list item of the keyword and storage address storage, and
It is modified according to the checking result to the header field；
Message encapsulates Encap units, for determining the need for waiting to locate by described according to amended header field
Reason message is packaged；If it is determined that it needs the clear text being packaged, then by the amended header word
Other in section and the PacketBuffer units in the clear text that stores in addition to the header field
Field is packaged；
Message sends TX units, for determining whether include the transmitted to CPU mark in the message after encapsulation；If it is determined that knot
Fruit is yes, then by CPU described in the message up sending after the encapsulation.
Optionally, the engine unit of tabling look-up includes at least one engine of tabling look-up, and each engine of tabling look-up includes：
Match subelements are matched, the keyword root for the keyword extraction Fetch units to be extracted is tabled look-up described in
The form that the list item Table subelements that engine includes can identify is formatted；
The list item Table subelements, for the table according to formatted keyword and storage address storage
Item is tabled look-up, and exports the checking result；Wherein, store to table look-up in the list item Table subelements tables look-up
Algorithm；
Action subelements are changed, for modifying according to the checking result to the header field.
Optionally, each described engine of tabling look-up further includes：
List item manages TableMng subelements, for configuring the table in same query engine according to the list item configuration information
The list item that item Table subelements can be inquired about.
Optionally, the CPU includes main management Host Main units and the first control unit, the multiple functional unit
The second control unit is further included,
The main management Host Main units, for generating control signal；The multiple work(is carried in the control signal
The ID for one of functional unit that energy unit includes；Wherein, the difference at least one FPGA in any one FPGA
The ID of functional unit is different；
First control unit, for the control signal to be sent to second control unit；
Second control unit for receiving the control signal, and the control signal is transmitted to and the ID
Corresponding functional unit；Wherein, at least one FPGA can be based on the control signal and control work(corresponding with the ID
The unlatching of energy unit realization of functions and/or parameter setting.
Optionally, the CPU further includes packet sending and receiving unit；The multiple functional unit further includes direct memory access list
Member, the direct memory access unit receives RX units with the message and the message sends TX units and is connected；
The packet sending and receiving unit, for clear text to be stored in memory, and to the direct memory access list
Member sends the storage address of the clear text；Alternatively, it receives in the carrying that the direct memory access unit is sent
The storage address of the message of CPU marks is sent, and is taken according to obtaining the storage address of the message of the carrying transmitted to CPU mark
Message with transmitted to CPU mark；
The direct memory access unit, for receiving the storage address of the clear text, according to described pending
The storage address of message reads the clear text, and read clear text is sent to the message to receive RX mono-
Member；Alternatively, receiving the message that the message sends the carrying transmitted to CPU mark that TX units are sent, will be sent in the carrying
The packet storage of CPU marks is sent to the report in memory, and by the storage address of the message of the carrying transmitted to CPU mark
Literary Transmit-Receive Unit.
Optionally, the CPU further includes the first list item dispensing unit；The multiple functional unit further includes the second list item and matches somebody with somebody
Unit is put, the second list item dispensing unit manages TableMng subelement phases with the list item in each engine of tabling look-up
Even；
The main management Host Main units are additionally operable to generation list item configuration information；
The first list item dispensing unit configures list for the list item configuration information to be sent to second list item
Member；
The second list item dispensing unit, for receiving the list item configuration information, and according to the list item configuration information
The list item configuration information is transmitted to main management TableMng subelements corresponding with the type by the type of the list item of configuration.
Optionally, the CPU further includes message source MAC address learning unit；
The message source MAC address learning unit, for the pass included to the message for carrying the transmitted to CPU mark
Key word is stored, and storage address is sent to the second list item dispensing unit.
Optionally, any one FPGA is further included at least one FPGA：
Message transmissions passage, is used for transmission message；
Header transmission channel is used for transmission header field；
Header control field transmission channel, is used for transmission header control field；
List item configuration information transmission channel is used for transmission the list item configuration information；
Req/ack signal paths are used for transmission req/ack signals；
Wherein, any one functional unit in the multiple functional unit carries out data transmission to other functional units
When, any one described functional unit can call passage corresponding with the type of the data to be transmitted to be transmitted.
Second aspect provides a kind of message processing method, and the method is applied in message processor, at the message
Managing equipment includes CPU and at least one FPGA, the described method includes：
At least one FPGA receives the list item configuration information for the list item that CPU is itself configuration；The list item matches somebody with somebody confidence
The storage address of the list item is carried in breath；
At least one FPGA receives the list item configuration information and clear text, intercepts the clear text
Header field, and extracted from the header field for the keyword tabled look-up, according to the keyword and institute
The list item for stating storage address storage is tabled look-up, and the clear text is handled according to checking result, by treated
Message is sent to equipment corresponding with treated the message；Wherein, the keyword and the table of storage address storage
Item is corresponding.
Optionally, the method further includes：
At least one FPGA receives clear text；
At least one FPGA intercepts the header field of the clear text, and will be in the clear text
Other fields in addition to the header field are stored；
At least one FPGA determines the type of the clear text according to the header field, is determining knot
Fruit show the clear text be protocol massages when, then in the header field add transmitted to CPU mark；Wherein,
The transmitted to CPU mark demonstrates the need for the clear text being sent to the CPU；
At least one FPGA extracts the keyword in the header field；
At least one FPGA tables look-up according to the list item that the keyword and the storage address store, and root
It modifies according to the checking result to the header field；
At least one FPGA is determined the need for according to amended header field by the clear text
It is packaged；If it is determined that it needs the clear text being packaged, then by the amended header field and institute
State other fields in the clear text stored in PacketBuffer units in addition to the header field into
Row encapsulation；
At least one FPGA determines whether include the transmitted to CPU mark in the message after encapsulation；If it is determined that result
It is yes, then by CPU described in the message after the encapsulation.
Optionally, at least one FPGA is looked into according to the list item that the keyword and the storage address store
Table, and modified according to the checking result to the header field, including：
At least one FPGA carries out the form that the keyword root of extraction can be identified according at least one FPGA
It formats；
At least one FPGA is looked into according to the list item that formatted keyword and the storage address store
Table, and export the checking result；Wherein, at least one FPGA stores the inquiring arithmetic tabled look-up；
At least one FPGA modifies to the header field according to the checking result.
Optionally, the method further includes：
The table that at least one FPGA can be inquired about according to list item configuration information configuration at least one FPGA
.
Optionally, the method further includes：
At least one FPGA receives the control signal that the CPU is sent；Wherein, at least one FPGA includes more
A functional unit, and the ID of the different function units in any one FPGA is different；It is carried in the control signal the multiple
The ID for one of functional unit that functional unit includes；
The control signal is sent to functional unit corresponding with the ID by least one FPGA；Wherein, it is described
FPGA can control the unlatching of functional unit realization of functions corresponding with the ID and/or parameter to set based on the control signal
It puts.
Optionally, the method further includes：
At least one FPGA receives the storage address for the clear text that the CPU is sent；And it waits to locate according to described
The storage address for managing message reads the clear text；
Alternatively,
At least one FPGA carries the packet storage of transmitted to CPU mark in memory, and by the carrying transmitted to CPU
The storage address of the message of mark is sent to the CPU.
Optionally, the method further includes：
At least one FPGA receives the list item configuration information that the CPU is sent；
At least one FPGA configures list item according to the list item configuration information.
Optionally, any one FPGA is further included at least one FPGA：
Message transmissions passage, is used for transmission message；
Header transmission channel is used for transmission header field；
Header control field transmission channel, is used for transmission header control field；
List item configuration information transmission channel is used for transmission the list item configuration information；
Req/ack signal paths are used for transmission req/ack signals；
Wherein, any one functional unit in the multiple functional unit carries out data transmission to other functional units
When, any one described functional unit can call passage corresponding with the type of the data to be transmitted to be transmitted.
The third aspect provides a kind of message processing method, and the method is applied in message processor, at the message
Managing equipment includes CPU and FPGA, the described method includes：
The CPU generates list item configuration information；The list item configuration information is used to configure list item for the FPGA, and described
The storage address of the list item is carried in list item configuration information；
The list item configuration information for configuring the list item is sent to the FPGA by the CPU.
Optionally, the method further includes：
The CPU generates control signal；One of functional unit that the FPGA includes is carried in the control signal
ID；
The control signal is sent to the FPGA by the CPU, is believed so that the FPGA can be based on the control
The unlatching of number corresponding with the ID functional unit realization of functions of control and/or parameter setting.
Optionally, the method further includes：
Clear text is stored in memory by the CPU, and the storage of the clear text is sent to the FPGA
Address；
Alternatively,
The CPU receives the storage address of the message for the carrying transmitted to CPU mark that the FPGA is sent, and according to institute
It states storage address and reads the message for carrying transmitted to CPU mark.
Optionally, the message for carrying transmitted to CPU mark is being read according to the storage address, the method is also afterwards
Including：
The keyword that the CPU includes the message for carrying the transmitted to CPU mark stores；
Storage address is sent to the FPGA by the CPU.
In embodiments of the present invention, message processor is the equipment based on CPU+FPGA heterogeneous systems, wherein, CPU is used
Controlled and managed in function to FPGA etc., and FPGA is used to carry out the specific processing and forwarding of message, by CPU and
The collaborative work of FPGA realizes the processing to universal network message, disclosure satisfy that the verification of network message Processing Algorithm, network association
The requirement of the application scenarios such as view unloading realization, and the embodiment of the present invention has built a kind of CPU+ for Message processing
FPGA heterogeneous systems provide frame foundation for subsequent exploitation, save the time of subsequent development.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, it will make below to required in the embodiment of the present invention
Attached drawing is briefly described, it should be apparent that, attached drawing described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structure diagram of message processor provided in an embodiment of the present invention；
Fig. 2 is a kind of structure of the message processor provided in an embodiment of the present invention including CPU and FPGA
Schematic diagram；
Fig. 3 is a kind of structural representation of the message processor provided in an embodiment of the present invention for being used to handle two layer message
Figure；
Fig. 4 is the flow diagram of message processing method provided in an embodiment of the present invention.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described.
The technical background of the embodiment of the present invention is described below.
At present, due to the extremely strong programmability of FPGA, and also there are very strong advantage, base in time delay, throughput etc.
Gradually start to be used in the network equipment of FPGA architecture.But at present for the network equipment of FPGA architecture, there is no a kind of
General development model or relatively fixed network message processing method, so it is all to redesign to develop ninety-nine times out of a hundred, and
And module interface is different, reusability is low, could only when developer is familiar with processing frame, Message processing logic
Complete design, and for only needing to verify some algorithm, the agreement even developer of some cell processing logic, it takes
Building complete network message processing frame needs to consume the substantial amounts of time, and development efficiency is low.
In consideration of it, the embodiment of the present invention provides a kind of message processor, which is based on CPU+FPGA heterogeneous systems
Equipment, wherein, CPU is for being controlled and managed to function of FPGA etc., and FPGA is used to carry out the specific processing of message
And forwarding, by the collaborative work of CPU and FPGA, the processing to universal network message is realized, disclosure satisfy that at network message
The requirement of the application scenarios such as proof of algorithm, procotol unloading realization is managed, and the embodiment of the present invention has built a kind of use
In the CPU+FPGA heterogeneous systems of Message processing, frame foundation is provided for subsequent exploitation, saves the time of subsequent development.
Technical solution provided in an embodiment of the present invention is introduced below in conjunction with the accompanying drawings.
Fig. 1 is referred to, one embodiment of the invention provides a kind of message processor 10, which includes CPU and at least one
A FPGA, CPU are total by external equipment interconnection (Peripheral Component Interconnect express, PCIe)
Line is connected with the FPGA.Wherein, due to the process that Message processing is carried out in each FPGA be it is identical, below will be with
It is illustrated exemplified by one of FPGA, and one of FPGA can be any one in above-mentioned at least one FPGA,
One of FPGA is referred to as FPGA directly below.
In embodiments of the present invention, FPGA can be used for the forwarding capability for carrying data surface, i.e., for message
It manages and forwards.Specifically, the clear text that FPGA can receive other equipment or CPU is sent, and extract clear text
Header field and header field is parsed, tabled look-up according to header field, and according to tabling look-up
As a result message is handled, and then message is sent to corresponding equipment by treated.
In embodiments of the present invention, CPU can be used for the function of carrying control plane and chain of command, that is, be used to configure for FPGA
List item and the opening and closing of the function of FPGA are managed and parameter during to the work of FPGA is configured.
Wherein, list item when list item is tabled look-up for the FPGA keywords included according to message, such as can be media access control
(Media Access Control, MAC) address list item, address resolution protocol (Address Resolution Protocol,
ARP) list item and Internet protocol address (Internet Protocol Address, IP) address list item etc., it is, of course, also possible to
Including other possible list items, the embodiment of the present invention is without limitation.
Fig. 2 is referred to, is a kind of structure diagram of FPGA provided in an embodiment of the present invention and CPU.Wherein, FPGA can be with
Including multiple functional units.The functional unit included for FPGA is described in detail below, meanwhile, in following description
In, it can also be related to each functional unit that CPU includes.
Message receives (Receiver, RX) unit, and message receives RX units and can be used for receiving clear text.Specifically
, when clear text reaches message processor, typically connect by the physics Ethernet interface on the message processor
Clear text is received, therefore message reception RX units then can receive clear text from the physics Ethernet interface.In addition, CPU
The interface of a reception clear text is can also be used as, therefore, after CPU receives clear text, message receives RX
Unit can also receive the clear text that CPU is forwarded.
Message bag splits (Decap) unit, and message bag splits Decap units and can be used for receiving the reception of RX units in message
To after clear text, message receives the clear text that RX units are sent.Since in a message, the head word of message
Section has contained all information for message forward process, then only needs to handle header field.
Therefore, after message bag splits Decap units reception clear text, the header word of the clear text can be intercepted
Section, using header field as the object of Message processing, and other in clear text in addition to header field
Field need not be handled, therefore can be stored in the buffer.Therefore, FPGA can also include packet buffer
(PacketBuffer) unit, for storing other fields in above-mentioned clear text in addition to header field.It is logical
For often, the preceding 128B of a message includes all information for message forward process, therefore message bag is split here
Decap units can be using the preceding 128B in clear text as header field, and in clear text after 128B
Other fields are then stored in packet buffer PacketBuffer units.
Packet parsing (Parser) unit, can be used for the type that clear text is determined according to header field.Tool
Body, when clear text is protocol massages, then transmitted to CPU mark is added in header field, then will be amended
Header field is sent to keyword extraction (Fetch) unit and is handled, and transmitted to CPU mark is demonstrated the need for the pending report
Text is sent to CPU；When clear text is not protocol massages, then header field is routed directly to keyword extraction
Fetch units are handled.In addition, packet parsing Parser units can also record the quantity of different type of messages.
Keyword extraction Fetch units can be used for receiving the amended message that packet parsing Parser units are sent
Header fields or header field, and extract including keyword, and the keyword of extraction feeding is tabled look-up engine
Unit.Wherein, for keyword for tabling look-up, keyword for example can be the MAC Address, source MAC, destination IP carried in message
Address, source IP address or virtual LAN (Virtual Local Area Network, VLAN) mark (Identity,
ID) etc..
It tables look-up engine unit, for the keyword that is extracted according to keyword extraction Fetch units and is the engine list of tabling look-up
The list item of member configuration is tabled look-up, and is modified according to the checking result to the header field.
Specifically, engine unit of tabling look-up can also include multiple engines of tabling look-up, and each engine of tabling look-up can also include
Multiple subelements.Wherein, multiple engines of tabling look-up can be sequentially connected, and each content that engine is tabled look-up of tabling look-up can be not
Together.Such as engine unit of tabling look-up includes two engines of tabling look-up, one of them tables look-up engine for being looked by two layer MAC address
Table, and another engine of tabling look-up can be used for tabling look-up by three layers of IP address.Although the content that engine of tabling look-up is tabled look-up can be with
Difference, but each is tabled look-up, the structure of engine can be similar, thus below by taking the structure of an engine of tabling look-up as an example into
Row description.
Specifically, engine of tabling look-up can include：
(Match) subelement is matched, for the keyword root that extracts keyword extraction Fetch units it is investigated that table engine bag
The form that list item (Table) subelement included can identify is formatted.Wherein, keyword extraction Fetch units extract
Keyword is only to extract keyword from header field, but may not be list item Table subelement energy
The form enough identified, therefore matching Match subelements then need keyword being combined, then again by the keyword after combination
It is sent to list item Table subelements.For example, when carrying out MAC Address entry lookup, what list item Table subelements can identify
The form of keyword is preceding according to VLAN ID, and the posterior order of target MAC (Media Access Control) address is combined, then keyword extraction
After Fetch units extract VLAN ID and target MAC (Media Access Control) address respectively, then matching Match subelements needs according to VLAN
Preceding, the posterior form of target MAC (Media Access Control) address is combined ID, then the keyword after combination is sent to list item Table subelements.
List item Table subelements, for tabling look-up according to formatted keyword, obtain checking result.Wherein, table
A variety of inquiring arithmetics can be encapsulated in item Table subelements, and list item Table subelements can also access storage in memory
List item, then list item Table subelements formatted keyword can be looked into list item by corresponding inquiring arithmetic
Table.Specifically, the inquiring arithmetic encapsulated in list item Table subelements can include direct index algorithm, Hash (Hash) algorithm,
More hash algorithms, Hi-Cuts algorithms and longest prefix match (Long Prefix Matching, LPM) algorithm etc..Certainly, also
It can include other possible algorithms, the embodiment of the present invention is without limitation.The list item that Table subelements can access is logical
Cross what CPU was configured, this is described in detail in rear extended meeting, and details are not described herein.Memory mentioned here can be static
Random access memory (Static random access memory, SRAM)；It can also be the storage of Double Data Rate synchronous dynamic random
Device (Double Data Rate, DDR), it is of course also possible to be other possible memories, the embodiment of the present invention does not limit this
System.
(Action) subelement is changed, for being modified according to checking result to header field, then will be after modification
Header field be sent to subsequent engine or the subsequent functional unit of tabling look-up.In addition, also may be used in header field
To carry lookup result.For example, when being tabled look-up by target MAC (Media Access Control) address and source MAC, if source MAC is tabled look-up
During miss, then Action subelements can add transmitted to CPU mark in header field, so as to the message is sent
Message study is carried out to CPU；If target MAC (Media Access Control) address is hit, then the addition forwarding (Forward, FW) in header field
Mark, and by checking result message forwarding outlet addition in message control field, if but target MAC (Media Access Control) address do not order
In, then it is directly added in header field and abandons (Drop) mark.
In the embodiment of the present invention, engine of tabling look-up can also include list item management (TableMng) subelement, list item management
TableMng subelements are in list item Table of same engine of tabling look-up for configuring with list item management TableMng subelements
The list item that unit can access.
After header field after engine unit output modifications of tabling look-up, amended header field can input
(Encap) unit is encapsulated to message.Wherein, message encapsulation Encap units are used to be determined according to amended header field
Whether need the clear text being packaged.Specifically, if Drop is not carried in amended header field
Indicate, then message encapsulation Encap units take out the remaining field being stored in packet buffer PackeBuffer units, and will
The residue field is packaged with amended header field, and the message after encapsulation is sent to message and is sent
(Transmitter, TX) unit；If Drop marks are carried in amended header field, then by the amended report
Literary header fields directly abandon, and delete the remaining field being stored in packet buffer PackeBuffer units.
Message sends (TX) unit, after the message after encapsulation is received, is carried according in the message after encapsulation
Mark, the message after this is encapsulated is sent to corresponding equipment.If specifically, encapsulation after message in carry transmitted to CPU
Mark, then be sent to CPU by the message after encapsulating；If in the message after the encapsulation carry FW mark, then according to encapsulation after
Message in carry message outlet the message after encapsulating is forwarded.
In the embodiment of the present invention, except being used for the functional unit to Message processing in FPGA, some special work(are further included
Energy unit, correspondingly, also including corresponding functional unit in CPU, for completing the interaction of PFGA and CPU, to assist to complete
Message processing flow.
Wherein, packet sending and receiving unit can be included in CPU, correspondingly, internal storage access (Direct can also be included in FPGA
Memory Access, DMA) unit, which can be connected with above-mentioned multiple functional units, such as can
It is connected with receiving RX units with message transmission TX units and message.Specifically, packet sending and receiving unit can receive new treat in CPU
After handling message, clear text storage in memory, then by the storage address of the clear text is sent in FPGA
Direct memory access unit, direct memory access unit can then receive the storage address, and be read according to the storage address
The clear text stored in memory, then the message that clear text is sent in FPGA receive RX units, follow-up to carry out
Message processing.
In addition, when carrying transmitted to CPU mark during message sends the message after TX units determine encapsulation, this can also be encapsulated
Message afterwards is sent to direct memory access unit, direct memory access unit again by the packet storage after encapsulation in memory,
And storage address is sent to the packet sending and receiving unit in CPU, packet sending and receiving unit then can be according to carrying transmitted to CPU mark
The storage address of message obtains the message for carrying transmitted to CPU mark.
After message after the packet sending and receiving unit in CPU receives encapsulation, the message after the encapsulation can also be determined
The reason for middle carrying transmitted to CPU mark, such as reason can be that the message is protocol massages or the message for miss of tabling look-up.Its
In, protocol massages are used to carry out the transmission of agreement, it is therefore desirable to be sent to CPU processing；The message needs for miss of tabling look-up
The message source MAC address learning unit being forwarded in CPU carries out the study of message.Such as if source MAC is not when tabling look-up
Hit, then message source MAC address learning unit can then learn the source MAC, and the list item for learning generation is deposited
It is stored in memory, while also needs to the information of newly-generated list item being sent to FPGA, so that FPGA energy when tabling look-up next time
Enough successful hits.
Main management (Host Main) unit is further included in the embodiment of the present invention, in CPU, for according to message source MAC
The learning outcome generation list item configuration information of unit.For example, new table is generated in message source MAC address learning modular learning
, it is necessary to notify the relevant information of newly-generated list item to FPGA after, then then needed at this time through main management Host
Main units generate list item configuration information, and the storage address of newly-generated list item is carried in list item configuration information.
In order to which list item configuration information is sent to FPGA, the first list item configuration (Table can also be included in CPU
Config) unit, the first list item dispensing unit can be used for above-mentioned list item configuration information being sent to FPGA.First list item configures
Unit can also be initialized except the list item configuration information of the newly-increased list item learnt is sent to FPGA in message processor
When, the list item configuration information for forwarding the packet relevant list item is sent to FPGA；Furthermore it is also possible to it is used for FPGA transmissions
Delete the list item configuration information of part list item.
It is corresponding, in FPGA can also include the second list item dispensing unit, the second list item dispensing unit can with it is each
The management TableMng subelements of the list item in engine of tabling look-up are connected.Wherein, the second list item dispensing unit can receive the first list item
The list item configuration information that dispensing unit is sent to can carry the class for being used to indicate newly-generated list item in the list item configuration information
The type information of type, then the list item configuration information can be sent to accordingly by the second list item dispensing unit according to the type information
List item management TableMng subelements.In addition, when list item is larger, the second list item dispensing unit can also be responsible for removing for list item
Fortune, such as list item is carried in batches from the DMA cachings of CPU.
In the embodiment of the present invention, CPU can also control the function and parameter of FPGA.Specifically, the supervisor in CPU
Reason Host Main units can be also used for generation control signal (Control Signal), which is then used for FPGA
The dynamic configuration of functional unit, real-time management, register read-write etc. controlled.Specifically, in order to which FPGA is receiving the control
After signal processed, can correctly control the specific functional unit in the FPGA achieved function carry out control and/
Or parameter setting, therefore the control signal can carry the ID for the functional unit that FPGA includes, in this way, receiving control letter in FPGA
After number, then can more accurately it be controlled.Wherein, the ID of the different functional units in FPGA is different.
In order to send control signals to FPGA, the first control unit can also be included in CPU, the first control unit can
For sending control signals to FPGA.
Certainly, main management Host Main cell processings can be generated outside control signal and list item configuration information, can be with
The other information of generation, such as can also be that a functional unit in generation scheduling FPGA performs the scheduling letter of corresponding function
Breath etc., the embodiment of the present invention is without limitation.Correspondingly, other information can also be transmitted to by the first control unit
FPGA。
In order to receive the control signal of CPU transmissions, the second control unit can also be included in FPGA, the second control unit can
For receiving control signal, and the control signal is transmitted to by function corresponding with the ID according to the ID carried in control signal
Unit, so that corresponding functional unit is able to carry out the action of control signal instruction.For example, control signal can be used
In the receiving velocity that message is set to receive RX units, then message is received after RX units receive the control signal, then can be according to
The receiving velocity of control signal instruction carries out the reception of clear text；Alternatively, control signal can also be for control table
The message learning functionality of item Table subelements is turned on or off, wherein, CPU can open list item by control signal
The message learning functionality of Table subelements, in this way, FPGA then can directly learn the message for miss of tabling look-up, and nothing
CPU need to be sent to；Correspondingly, CPU can also close the message learning functionality of list item Table subelements by control signal.
In the embodiment of the present invention, what the interaction between CPU and FPGA can be provided by the production firm of FPGA opens fortune
It realizes main channel (Host Channel) in language (Open Computing Language, the OpenCL) system of calculation.Such as
When the second control unit that the first control unit in CPU wants into FPGA sends control signal, then it can pass through the first control
Cell call Host Channel processed are sent.
In addition, some configurable functional units can also be reserved in CPU, needs other functions in CPU are used to implement
Some functions that unit does not possess, these units can configured during practice.Such as control Message processing
Unit, for handling control message.
In the embodiment of the present invention, in FPGA, data below transmission channel can be included：
(1) message transmissions passage is used for transmission message；
(2) header transmission (pkt) passage, is used for transmission header field；
(3) header control field transmission (packet head control, phc) passage, is used for transmission header
Control field；Message forwarding control information, such as the head bias value or IP of MAC layer are carried in header control field
The deviant on head be either used to indicate the information for the mark whether message abandons or be used to indicate message whether mirror image
The information of mark.
(4) message transmission (message, msg) passage, is used for transmission the information such as the list item configuration information；
(5) req/ack signal paths are used for transmission req/ack signals；Req/ack signals are between two functional units
Handshake, between two functional units according to the two functional units arrange protocol mode communicate.
Above-mentioned data transmission channel can be realized by Channel that OpenCL systems provide.Wherein, message transmissions
The bit wide of passage and pkt passages can use 128B, i.e., the transmission when carrying out message transmissions or header transmits can per beat
Transmit 128B；The bit wide of phc passages can use 64B or 32B；The bit wide of msg passages can use 32B or 16B；Req/ack signals
The bit wide of passage can use 8B or 4B.Certainly, other possible data transmission channels can also be included in FPGA, the present invention is implemented
Example is without limitation.
Wherein, when the two of which functional unit in the FPGA needs to carry out data transmission, it can call and want
The corresponding passage of type of the data of transmission is transmitted.Specifically, above-mentioned data transmission channel can also possess data buffer storage
Ability, when carrying out data transmission, if the beat of the functional unit at both ends is not meanwhile, it is capable to play buffer action.For example, work as
When message receives rate that RX units receive and splits Decap units to the processing capacity of message higher than message bag, then message connects
The message that receipts RX units pass to message bag fractionation Decap units can not then be processed in time, then then message be needed to connect at this time
The data transmission channel that RX units and message bag are split between Decap units is received not locate message bag fractionation Decap units in time
The message of reason is cached.
Be shown in FIG. 2 the data transmission channel that may be called between functional unit, for example, message receive RX units and
Message bag split between Decap units may transmitting message header fields, message either header control field or other
Information, therefore message receives RX units and pkt passages, phc passages or msg passages can be called mono- to message bag fractionation Decap
Member sends data.Wherein, the second list item dispensing unit is in forwarding-table item configuration information, and when list item is smaller, the second list item is matched somebody with somebody
Putting unit can be by calling req/ack signal paths to be configured；When list item is larger, then can be configured by the second list item
Unit directly invokes msg passages and is configured.The method of calling of remaining functional unit is similar, is then no longer repeated one by one at this.
Certainly, the calling of passage shown in Fig. 2 is only used for illustrating, therefore it is also possible to there are other possible calling situations, this hairs
Bright embodiment is without limitation.
Fig. 3 is referred to, for the message processor provided in an embodiment of the present invention for the processing of Ethernet two layer message
Structure diagram.It is described by below with the Message processing flow of message processor shown in Fig. 3.
In the embodiment of the present invention, CPU can send message by the second control unit of first control unit into FPGA
Receiving velocity (Packet Rate Limit) signal, and the message carried in the signal in FPGA receives the ID of RX units,
The signal can be then transmitted to message reception RX units by the second control unit after receiving Packet Rate Limit signals,
Message receives RX units also will receive message according to the message receiving velocity of Packet Rate Limit signal designations.
After RX units have received clear text, then message can be sent to message bag and split Decap units.Message
Bag splits header field of the preceding 128B fields as clear text in Decap units interception clear text, then will
Header field is sent to packet parsing Parser units, and the remaining field in addition to this 128B is stored in message buffering
In PacketBuffer units.
Packet parsing Parser units judge the type of message according to header field, if it is judged that showing that this is treated
Processing message is protocol massages, then transmitted to CPU mark is added in header field, then by amended header field
It is sent to MAC Address extraction Fetch units；If it is judged that showing that the clear text is not protocol massages, then directly will
Header field is sent to MAC Fetch units.Wherein, MAC Address extraction Fetch units are the spies in two layer message processing
Order member.Packet parsing Parser units can also count the quantity of the message of oneself processing and different types of message
Quantity, and pass through the second control unit and be sent to CPU.
MAC Address extraction Fetch units extract target MAC (Media Access Control) address and source MAC in header field, are sent into ground
Location forwarding table (Forwarding DataBase, FDB) engine of tabling look-up.
The matching Match subelements that FDB tables look-up in engine to hash table Hash Table subelements with sending purpose MAC
Location inquiry request and source MAC inquiry request.Hash table Hash Table subelements show to be looked by hash algorithm
Table.Hash table Hash Table subelements calculate cryptographic Hash according to target MAC (Media Access Control) address and source MAC, further according to cryptographic Hash
It tables look-up, and checking result is sent to modification Action subelements.When source MAC miss, if CPU passes through
One control unit is configured with source MAC for hash table Hash Table subelements and learns (Auto Learn) function automatically,
Then hash table Hash Table subelements can automatically save source MAC, if closing Auto Learn functions, then change
Action subelements add transmitted to CPU mark in header field.When checking result shows target MAC (Media Access Control) address miss,
Action subelements then add Drop marks for header field, when checking result shows target MAC (Media Access Control) address hit, modification
Message is then exported deposit message control field by Action subelements, and in header field addition FW marks.
Message encapsulate Encap units receive amended header field that modification Action subelements send it
Afterwards, if the amended header field includes Drop marks, then the header field is directly abandoned, and emptied
The corresponding remaining field for being stored in message buffering PacketBuffer units of the header field.If the amended report
Drop marks are not carried in literary header fields, then from the remaining field in message buffering PacketBuffer units, then this are remained
Remaining field and header field are packaged, and the message after encapsulation is sent to message and sends TX units.
If carrying transmitted to CPU mark in the message after encapsulation, then message sends TX units and passes through the message after encapsulation
Direct memory access unit is sent to CPU；If carrying FW marks in the message after encapsulation, then message sends TX units and will encapsulate
Message afterwards is sent to corresponding equipment by the message outlet carried in the message after encapsulation.
In the embodiment of the present invention, after the message of source MAC miss is sent to CPU by FPGA, the message in CPU
Transmit-Receive Unit receives the message, and the message is sent to master management unit, and master management unit forwards the packet to message source
MAC address learning unit is learnt, and the list item of message source MAC address learning modular learning generation is sent to master management unit,
Master management unit stores list item into memory, and generates list item configuration information, by the first list item dispensing unit by list item
Configuration information is sent to the second list item dispensing unit in FPGA.
List item configuration information is transmitted to hash table management Hash TableMng subelements by the second list item dispensing unit,
And then hash table management Hash TableMng subelements can manage Hash according to the list item configuration information for hash table
Table subelements configure list item.
In conclusion message processor is the equipment based on CPU+FPGA heterogeneous systems, wherein, CPU is used for FPGA
Function etc. controlled and managed, and FPGA is used to carry out the specific processing and forwarding of message, passes through the collaboration of CPU and FPGA
Work, realizes the processing to universal network message, disclosure satisfy that the verification of network message Processing Algorithm, procotol unloading are realized
The requirement of application scenarios is waited, and the embodiment of the present invention has built a kind of CPU+FPGA isomeries system for Message processing
System provides frame foundation for subsequent exploitation, saves the time of subsequent development.
Fig. 4 is referred to, based on same inventive concept, one embodiment of the invention provides a kind of message processing method, this method
Applied in message processor, message processor, which includes CPU and at least one FPGA, this method, to be included：
Step 401：At least one FPGA receives the list item configuration information for the list item that CPU is itself configuration；List item matches somebody with somebody confidence
The storage address of list item is carried in breath；
Step 402：At least one FPGA receives list item configuration information and clear text, intercepts the message of clear text
Header fields, and extraction for the keyword tabled look-up, is stored according to keyword and storage address from header field
List item is tabled look-up, and clear text is handled according to checking result, will treated that message is sent to and treated
The corresponding equipment of message；Wherein, keyword is corresponding with the list item that storage address stores.
One embodiment of the invention also provides a kind of message handling system, which includes CPU and at least one
FPGA；Wherein, any one FPGA at least one FPGA for example can be the FPGA in embodiment shown in Fig. 2, CPU
Such as can be the CPU in embodiment shown in Fig. 2.Specifically, FPGA can be used in carrying out the processing of message, CPU can be right
Each functional unit that FPGA includes is scheduled, and the parameter of each functional unit is configured and managed, with to FPGA
The process for carrying out Message processing is controlled.
In the embodiment of the present invention, each functional unit in CPU can be based on Thread, then the function list in CPU
The realization of member can be the Thread codes write by C++；Each functional unit in FPGA can be based on Kernel,
Realizing for each functional unit in so FPGA can be by Kernel codes that OpenCL language is write.In both sides generation
After the completion of code is all write, Kernel codes can be compiled by OpenCL compilers, and Thread codes can be compiled by GCC
It translates device to be compiled, then the Kernel codes after compiling is burnt in FPGA, and Thread codes are loaded by CPU, so as to
Function more than realization.
In embodiments of the present invention, it should be understood that disclosed device and method, it can be real by another way
It is existing.For example, apparatus embodiments described above are only schematical, for example, the division of the unit or unit, is only
A kind of division of logic function, can there is an other dividing mode in actual implementation, for example, multiple units or component can combine or
Person is desirably integrated into another system or some features can be ignored or does not perform.Another, shown or discussed is mutual
Between coupling, direct-coupling or communication connection can be INDIRECT COUPLING or communication link by some interfaces, equipment or unit
It connects, can be electrical or other forms.
Each functional unit in embodiments of the present invention can be integrated in a processing unit or unit also may be used
To be independent physical module.
If the integrated unit is realized in the form of SFU software functional unit and is independent production marketing or use
When, it can be stored in a computer read/write memory medium.Based on such understanding, the technical solution of the embodiment of the present invention
All or part can be embodied in the form of software product, which is stored in a storage medium
In, it is used including some instructions so that a computer equipment, such as can be personal computer, server or network are set
Standby etc. or processor (processor) performs all or part of the steps of the method according to each embodiment of the present invention.It is and foregoing
Storage medium includes：General serial bus USB (Universal Serial Bus flash drive), mobile hard disk, only
Read memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disc
Or the various media that can store program code such as CD.
The above, above example are only described in detail to the technical solution to the application, but above implementation
The explanation of example is only intended to help the method for understanding the embodiment of the present invention, should not be construed as the limitation to the embodiment of the present invention.This
The change or replacement that those skilled in the art can readily occur in, should all cover the embodiment of the present invention protection domain it
It is interior.
Claims (10)
1. a kind of message processor, which is characterized in that including central processor CPU and at least one field programmable gate array
FPGA；
The CPU for configuring list item at least one FPGA, and the list item configuration information for configuring the list item is sent
To at least one FPGA；The storage address of the list item is carried in the list item configuration information；
At least one FPGA for receiving the list item configuration information and clear text, intercepts the clear text
Header field, and extracted from the header field for the keyword tabled look-up, according to the keyword and
The list item of the storage address storage is tabled look-up, and the clear text is handled according to checking result, after processing
Message be sent to equipment corresponding with treated the message；Wherein, the keyword and storage address storage
List item is corresponding.
2. equipment as described in claim 1, which is characterized in that any one FPGA includes multiple at least one FPGA
Functional unit, the multiple functional unit specifically include：
Message receives RX units, for receiving clear text；
Message bag splits Decap units, for intercepting the header field of the clear text, and by the pending report
Other fields in text in addition to the header field are sent to the packet buffer in the multiple functional unit
PacketBuffer units are stored；
Packet parsing Parser units, for determining the type of the clear text according to the header field, true
Determine the result shows that when the clear text is protocol massages, then to add transmitted to CPU mark in the header field；Its
In, the transmitted to CPU mark demonstrates the need for the clear text being sent to the CPU；
Keyword extraction Fetch units, for extracting the keyword in the header field；
It tables look-up engine unit, for being tabled look-up according to the list item of the keyword and storage address storage, and according to
The checking result modifies to the header field；
Message encapsulates Encap units, for being determined the need for according to amended header field by the pending report
Text is packaged；If it is determined that need the clear text is packaged, then will the amended header field with
Other fields in the clear text stored in the PacketBuffer units in addition to the header field
It is packaged；
Message sends TX units, for determining whether include the transmitted to CPU mark in the message after encapsulation；If it is determined that result is
It is, then by CPU described in the message up sending after the encapsulation.
3. equipment as claimed in claim 2, which is characterized in that the engine unit of tabling look-up includes at least one engine of tabling look-up,
And each engine of tabling look-up includes：
Match subelements are matched, for tabling look-up engine described in the keyword root evidence of extract the keyword extraction Fetch units
Including the form that can identify of list item Table subelements be formatted；
The list item Table subelements, for according to formatted keyword and the storage address storage list item into
Row is tabled look-up, and exports the checking result；Wherein, the inquiring arithmetic tabled look-up is stored in the list item Table subelements；
Action subelements are changed, for modifying according to the checking result to the header field.
4. equipment as claimed in claim 3, which is characterized in that each described engine of tabling look-up further includes：
List item manages TableMng subelements, for configuring the list item in same query engine according to the list item configuration information
The list item that Table subelements can be inquired about.
5. equipment as claimed in claim 4, which is characterized in that the CPU includes main management Host Main units and the first control
Unit processed, the multiple functional unit further include the second control unit,
The main management Host Main units, for generating control signal；The multiple function list is carried in the control signal
The ID for one of functional unit that member includes；Wherein, the difference in functionality at least one FPGA in any one FPGA
The ID of unit is different；
First control unit, for the control signal to be sent to second control unit；
Second control unit for receiving the control signal, and the control signal is transmitted to corresponding with the ID
Functional unit；Wherein, at least one FPGA can be based on the control signal and control function list corresponding with the ID
The unlatching of first realization of functions and/or parameter setting.
6. equipment as claimed in claim 3, which is characterized in that the CPU further includes packet sending and receiving unit；The multiple function
Unit further includes direct memory access unit, and the direct memory access unit receives RX units and the message with the message
TX units are sent to be connected；
The packet sending and receiving unit for clear text to be stored in memory, and is sent out to the direct memory access unit
Send the storage address of the clear text；Alternatively, receive the carrying transmitted to CPU that the direct memory access unit is sent
The storage address of the message of mark, and obtained according to the storage address of the message of the carrying transmitted to CPU mark in the carrying
The message that CPU is sent to indicate；
The direct memory access unit, for receiving the storage address of the clear text, according to the clear text
Storage address read the clear text, and read clear text is sent to the message and receives RX units；
Alternatively, the message that the message sends the carrying transmitted to CPU mark that TX units are sent is received, by the carrying transmitted to CPU
The packet storage of mark is sent to the message in memory, and by the storage address of the message of the carrying transmitted to CPU mark
Transmit-Receive Unit.
7. equipment as claimed in claim 5, which is characterized in that the CPU further includes the first list item dispensing unit；It is the multiple
Functional unit further includes the second list item dispensing unit, the second list item dispensing unit with it is described in each engine of tabling look-up
List item management TableMng subelements are connected；
The main management Host Main units are additionally operable to generation list item configuration information；
The first list item dispensing unit, for the list item configuration information to be sent to the second list item dispensing unit；
The second list item dispensing unit for receiving the list item configuration information, and is configured according to the list item configuration information
The type of list item the list item configuration information be transmitted to corresponding with type list item manage TableMng subelements.
8. equipment as claimed in claim 6, which is characterized in that any one FPGA is further included at least one FPGA：
Message transmissions passage, is used for transmission message；
Header transmission channel is used for transmission header field；
Header control field transmission channel, is used for transmission header control field；
List item configuration information transmission channel is used for transmission the list item configuration information；
Req/ack signal paths are used for transmission req/ack signals；
Wherein, any one functional unit in the multiple functional unit to other functional units carry out data transmission when,
Any one described functional unit can call passage corresponding with the type of the data to be transmitted to be transmitted.
9. a kind of message processing method, which is characterized in that the method is applied in message processor, and the Message processing is set
It is standby to include CPU and at least one FPGA；Including：
At least one FPGA receives the list item configuration information for the list item that CPU is itself configuration；In the list item configuration information
Carry the storage address of the list item；
At least one FPGA receives the list item configuration information and clear text, intercepts the message of the clear text
Header fields, and being extracted from the header field for the keyword tabled look-up according to the keyword and described are deposited
The list item of storage address storage is tabled look-up, and the clear text is handled according to checking result, will treated message
It is sent to equipment corresponding with treated the message；Wherein, the list item phase that the keyword is stored with the storage address
It is corresponding.
10. method as claimed in claim 9, which is characterized in that at least one FPGA is according to the keyword and institute
The list item for stating storage address storage is tabled look-up, and the clear text is handled according to checking result, including：
At least one FPGA is by the keyword root of extraction according to the form that at least one FPGA can be identified into row format
Change；
At least one FPGA tables look-up according to the list item that formatted keyword and the storage address store, and
Export the checking result；Wherein, at least one FPGA stores the inquiring arithmetic tabled look-up；
At least one FPGA modifies to the header field according to the checking result.
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