CN108054081A - A kind of wafer bonding method based on pretreating process - Google Patents
A kind of wafer bonding method based on pretreating process Download PDFInfo
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- CN108054081A CN108054081A CN201711242797.6A CN201711242797A CN108054081A CN 108054081 A CN108054081 A CN 108054081A CN 201711242797 A CN201711242797 A CN 201711242797A CN 108054081 A CN108054081 A CN 108054081A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 235000012431 wafers Nutrition 0.000 claims abstract description 122
- 238000001312 dry etching Methods 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 8
- 239000002253 acid Substances 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 230000002000 scavenging effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 102000052666 B-Cell Lymphoma 3 Human genes 0.000 claims description 3
- 108700009171 B-Cell Lymphoma 3 Proteins 0.000 claims description 3
- 101150072667 Bcl3 gene Proteins 0.000 claims description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- 239000000908 ammonium hydroxide Substances 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 238000003801 milling Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 206010040844 Skin exfoliation Diseases 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000004767 nitrides Chemical group 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
The present invention provides a kind of wafer bonding method based on pretreating process, belongs to technical field of manufacturing semiconductors, including：By pretreating process, a piece of or two wafers are pre-processed to remove the residual on wafer；Step S2, by bonding technology, two wafers are carried out with bonding processing so that two panels wafer bonding；In step S1, pretreating process specific steps include：Step S11, wafer is covered by a protective cover and exposure remains, dry etch process is used to carry out dry etching to the residual in chamfering to remove residual；Step S12, protective cover is removed, cleaning treatment at least once is carried out to wafer by an acid solution.Beneficial effects of the present invention：The residual generated before can removing in making technology avoids the residual peeling in bonding technology from forming bonding defects after making wafer bonding to crystal column surface, so as to reduce wafer bonding cavity blemish rate, improves product yield, improve properties of product.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of wafer bonding sides based on pretreating process
Method.
Background technology
In integrated circuit technology, three-dimensionally integrated is a kind of raising chip performance while prior art node is kept
Solution.By the way that the identical or different chip of two or more functions is carried out the three-dimensionally integrated performance for improving chip, together
When metal interconnection between functional chip can also be greatly shortened, reduce fever, power consumption and delay.
In three-dimensionally integrated technique, the bonding technology of wafer and wafer is core emphasis, wherein wafer bonding cavity blemish
Rate is to weigh the core parameter of wafer bonding technique.
Wafer bonding cavity blemish rate in three-dimensionally integrated technique is an important factor for influencing product general defect rate, with the back of the body
Exemplified by illuminated CMOS image sensor, wafer bonding cavity blemish can continue to generate grain defect in follow-up process, influence to produce
Product optical property, properties of product can be effectively improved by improving bonding defects.
Wafer needs first to complete preceding making technology before bonding technology is carried out, as shown in Figure 1, by taking a kind of wafer as an example, it should
Wafer has wafer frontside 1, wafer rear 2, wafer side 3, step surface 4, extended surface 5, the first inclined surface 6 and the second inclined surface
7,4 and first inclined surface 6 of step surface forms chamfering.As shown in Figure 1, after preceding making technology, film can be generated at wafer chamfer
Or the residual 8 of chemicals；As shown in Fig. 2, after the technique of surface activation in wafer bonding, above-mentioned residual 8 (residue)
It can peel off to wafer frontside 1；As shown in figure 3, after the completion of wafer bonding processing procedure, these residue positions can form bonding
Defect 9.
From Fig. 1-3, in three-dimensionally integrated technique, wafer bonding cavity blemish is frequently occurred at crystal round fringes, main
If there is the generation of surface particles defect during due to bonding at crystal round fringes；Surface particles defect at these crystal round fringes is main
From residual of the preceding making technology at wafer chamfer, can be peeled off in bonding process to wafer frontside edge.
The subsequent bonding technology of the remaining influence generated in preceding making technology how is avoided, becomes technology urgently to be resolved hurrily
Problem.
The content of the invention
For problems of the prior art, the present invention relates to a kind of wafer bonding methods based on pretreating process.
The present invention adopts the following technical scheme that：
A kind of wafer bonding method based on pretreating process, the wafer bonding method are suitable for passing through preceding processing procedure respectively
Two wafers of technique processing, controlling the edge of at least a piece of wafer has a chamfering, has in the chamfering described in passing through
The residual generated after preceding making technology processing；The wafer bonding method includes：
Step S1, by pretreating process, the wafer with the chamfering is pre-processed to remove the crystalline substance
The residual on circle；
Step S2, by bonding technology, bonding processing is carried out to two wafer so that the two panels wafer bonding；
In the step S1, the specific steps of the pretreating process include：
Step S11, the wafer and the exposure residual are covered by a protective cover, using dry etch process to described
The residual in chamfering carries out dry etching to remove the residual；
Step S12, the protective cover is removed, cleaning treatment at least once is carried out to the wafer by an acid solution.
Preferably, the wafer has wafer frontside, the wafer rear opposite and parallel with the wafer frontside, positioned at institute
It states between wafer frontside and the wafer rear and the step surface parallel with the wafer frontside, the connection wafer frontside and institute
State step surface extended surface, with the wafer side of river source front vertical, be connected the step surface and the wafer side
First inclined surface；
The step surface forms the chamfering with first inclined surface, and the residual is located at first inclined surface
On.
Preferably, the wafer also has the second inclined surface for connecting the wafer side and the wafer rear；
First inclined surface and second inclined surface are symmetrical on the vertical center line of the wafer side.
Preferably, it is default using one when carrying out dry etching to the residual in the chamfering in the step S11
Mixed gas, the default mixed gas is mixed by Ar with pre-mixed gas to be formed；
The pre-mixed gas include CF4 and/or CHF3 and/or C4F8 and/or SF6 and/or CL2 and/or BCL3.
Preferably, it is default using one when carrying out dry etching to the residual in the chamfering in the step S11
Pressure；
The scope of the preset pressure is (5mT, 100mT).
Preferably, it is default using one when carrying out dry etching to the residual in the chamfering in the step S11
Etch period；
The scope of the default milling time is (10s, 300s).
Preferably, it is default using one when carrying out dry etching to the residual in the chamfering in the step S11
Etch power；
The scope of the default etching power is (100W, 4000W).
Preferably, in the step S12, the acid solution includes hydrofluoric acid and/or hydrochloric acid and/or hydrogen peroxide and/or ammonium hydroxide
And/or deionized water.
Preferably, in the step S12, the cleaning treatment is using a default scavenging period；
The scope of the default scavenging period is (5s, 240s).
Beneficial effects of the present invention：By after preceding making technology and adding pretreating process before bonding technology, can go
Except the residual generated in preceding making technology, the residual peeling in bonding technology is avoided to form key after making wafer bonding to crystal column surface
Defect is closed, so as to reduce wafer bonding cavity blemish rate, product yield is improved, improves properties of product.
Description of the drawings
Fig. 1-3 is flow diagram of two wafers in bonding by the processing of preceding making technology in the prior art；
Fig. 4 is the flow chart of the wafer bonding method based on pretreating process in a preferred embodiment of the present invention；
Fig. 5 is the flow chart of step S1 in a preferred embodiment of the present invention；
Fig. 6-8 is in a preferred embodiment of the present invention, and the flow of the wafer bonding method based on pretreating process is shown
It is intended to.
Specific embodiment
It should be noted that in the case where there is no conflict, following technical proposals can be mutually combined between technical characteristic.
The specific embodiment of the present invention is further described below in conjunction with the accompanying drawings：
As Figure 4-8, a kind of wafer bonding method based on pretreating process, which is characterized in that above-mentioned wafer bonding
Method is suitable for being respectively provided at the edge of the above-mentioned wafer of a piece of or two panels by two wafers of preceding making technology processing respectively
One chamfering has the residual 8 ' generated after above-mentioned preceding making technology processing in above-mentioned chamfering；Above-mentioned wafer bonding method bag
It includes：
Step S1, by pretreating process, the above-mentioned wafer of a piece of or two panels is pre-processed to remove on above-mentioned wafer
Above-mentioned residual 8 '；
Step S2, by bonding technology, bonding processing is carried out to above-mentioned two wafer so that above-mentioned two panels wafer bonding；
In above-mentioned steps S1, the specific steps of above-mentioned pretreatment are carried out by above-mentioned pretreating process to be included：
Step S11, above-mentioned wafer and the above-mentioned residual 8 ' of exposure are covered by a protective cover 9 ', using dry etch process pair
Above-mentioned residual 8 ' in above-mentioned chamfering carries out dry etching to remove above-mentioned residual 8 ' and will not remove wafer；
Step S12, above-mentioned protective cover 9 ' is removed, cleaning treatment at least once is carried out to above-mentioned wafer by an acid solution.
In the present embodiment, by after preceding making technology and adding pretreating process before bonding technology, before can removing
The residual 8 ' generated in making technology, avoids remaining in bonding technology after 8 ' peelings make wafer bonding to crystal column surface and forms key
Defect is closed, so as to reduce wafer bonding cavity blemish rate, product yield is improved, improves properties of product.
Further, for it is different the defects of source making choice property process parameter optimizing can improve wafer in various degree
Cavity blemish rate is bonded, promotes properties of product.
It can be adapted for different three-dimensionally integrated wafer bonding technique (Si substrates and oxide bond, oxide and oxidation
Object bonding, oxide are bonded with nitride, metal and metal bonding etc.), reach the low bonding defects rate of three-dimensionally integrated technique
It is required that.
In preferred embodiment, above-mentioned wafer has wafer frontside 1 ', the crystalline substance opposite and parallel with above-mentioned wafer frontside 1 '
The circle back side 2 ', between above-mentioned wafer frontside 1 ' and above-mentioned wafer rear 2 ' and the step surface parallel with above-mentioned wafer frontside 1 '
4 ', connect the extended surface 5 ' of above-mentioned wafer frontside 1 ' and above-mentioned step surface 4 ' and the wafer side 3 ' of above-mentioned river source front vertical,
Connect the first inclined surface 6 ' of above-mentioned step surface 4 ' and above-mentioned wafer side 3 '；
Above-mentioned step surface 4 ' forms above-mentioned chamfering with above-mentioned first inclined surface 6 ', and above-mentioned residual 8 ' is inclined positioned at above-mentioned first
On inclined-plane 6 '.
In preferred embodiment, above-mentioned wafer also has connect above-mentioned wafer side 3 ' and above-mentioned wafer rear 2 ' second
Inclined surface 7 '；
Above-mentioned first inclined surface 6 ' and above-mentioned second inclined surface 7 ' are symmetrical on the vertical center line of above-mentioned wafer side 3 '.
In preferred embodiment, in above-mentioned steps S11, when carrying out dry etching to the above-mentioned residual 8 ' in above-mentioned chamfering,
Using a default mixed gas, above-mentioned default mixed gas is mixed by Ar with pre-mixed gas to be formed；
Above-mentioned pre-mixed gas include CF4 and/or CHF3 and/or C4F8 and/or SF6 and/or CL2 and/or BCL3.
In preferred embodiment, in above-mentioned steps S11, when carrying out dry etching to the above-mentioned residual 8 ' in above-mentioned chamfering,
Using a preset pressure；
The scope of above-mentioned preset pressure is (5mT, 100mT).
In preferred embodiment, in above-mentioned steps S11, when carrying out dry etching to the above-mentioned residual 8 ' in above-mentioned chamfering,
Using a default etch period；
The scope of above-mentioned default milling time is (10s, 300s).
In preferred embodiment, in above-mentioned steps S11, when carrying out dry etching to the above-mentioned residual 8 ' in above-mentioned chamfering,
Using a default etching power；
The scope of above-mentioned default etching power is (100W, 4000W).
In preferred embodiment, in above-mentioned steps S12, above-mentioned acid solution includes hydrofluoric acid and/or hydrochloric acid and/or hydrogen peroxide
And/or ammonium hydroxide and/or deionized water.
In preferred embodiment, in above-mentioned steps S12, above-mentioned cleaning treatment is using a default scavenging period；
The scope of above-mentioned default scavenging period is (5s, 240s).
By explanation and attached drawing, the exemplary embodiments of the specific structure of specific embodiment are given, it is smart based on the present invention
God can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.It is weighing
The scope and content of any and all equivalence, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (9)
- A kind of 1. wafer bonding method based on pretreating process, which is characterized in that the wafer bonding method is suitable for difference By two wafers that preceding making technology is processed, the edge of at least a piece of wafer has a chamfering, has in the chamfering The residual generated after the preceding making technology processing；It is characterized in that, the wafer bonding method includes：Step S1, by pretreating process, the wafer with the chamfering is pre-processed to remove on the wafer The residual；Step S2, by bonding technology, bonding processing is carried out to two wafer so that the two panels wafer bonding；In the step S1, the specific steps of the pretreating process include：Step S11, the wafer and the exposure residual are covered by a protective cover, using dry etch process to the chamfering On the residual carry out dry etching to remove the residual；Step S12, the protective cover is removed, cleaning treatment at least once is carried out to the wafer by an acid solution.
- 2. wafer bonding method according to claim 1, which is characterized in that the wafer has wafer frontside and the wafer Positive opposite and parallel wafer rear is put down between the wafer frontside and the wafer rear and with the wafer frontside Capable step surface, the extended surface for connecting the wafer frontside and the step surface, with the wafer side of river source front vertical, Connect the first inclined surface of the step surface and the wafer side；The step surface forms the chamfering with first inclined surface, and the residual is located on first inclined surface.
- 3. wafer bonding method according to claim 2, which is characterized in that the wafer also have connect the wafer side and Second inclined surface of the wafer rear；First inclined surface and second inclined surface are symmetrical on the vertical center line of the wafer side.
- 4. wafer bonding method according to claim 2, which is characterized in that in the step S11, described in the chamfering When residual carries out dry etching, using a default mixed gas, the default mixed gas is by Ar and pre-mixed gas mixing structure Into；The pre-mixed gas include CF4 and/or CHF3 and/or C4F8 and/or SF6 and/or CL2 and/or BCL3.
- 5. wafer bonding method according to claim 2, which is characterized in that in the step S11, described in the chamfering When residual carries out dry etching, using a preset pressure；The scope of the preset pressure is (5mT, 100mT).
- 6. wafer bonding method according to claim 2, which is characterized in that in the step S11, described in the chamfering When residual carries out dry etching, using a default etch period；The scope of the default milling time is (10s, 300s).
- 7. wafer bonding method according to claim 2, which is characterized in that in the step S11, described in the chamfering When residual carries out dry etching, using a default etching power；The scope of the default etching power is (100W, 4000W).
- 8. wafer bonding method according to claim 2, which is characterized in that in the step S12, the acid solution includes hydrofluoric acid And/or hydrochloric acid and/or hydrogen peroxide and/or ammonium hydroxide and/or deionized water.
- 9. wafer bonding method according to claim 2, which is characterized in that in the step S12, the cleaning treatment uses one Default scavenging period；The scope of the default scavenging period is (5s, 240s).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711242797.6A CN108054081A (en) | 2017-11-30 | 2017-11-30 | A kind of wafer bonding method based on pretreating process |
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| CN201711242797.6A CN108054081A (en) | 2017-11-30 | 2017-11-30 | A kind of wafer bonding method based on pretreating process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493099A (en) * | 2018-04-11 | 2018-09-04 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method |
| CN109950267A (en) * | 2019-03-26 | 2019-06-28 | 德淮半导体有限公司 | The production method of imaging sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050215056A1 (en) * | 2004-03-29 | 2005-09-29 | Patrick Morrow | Bonded wafer processing method |
| JP2006216662A (en) * | 2005-02-02 | 2006-08-17 | Sumco Corp | Process for producing bonding soi wafer, and the bonding soi wafer |
| CN102640267A (en) * | 2009-12-17 | 2012-08-15 | 朗姆研究公司 | Method and apparatus for processing bevel edge |
-
2017
- 2017-11-30 CN CN201711242797.6A patent/CN108054081A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050215056A1 (en) * | 2004-03-29 | 2005-09-29 | Patrick Morrow | Bonded wafer processing method |
| JP2006216662A (en) * | 2005-02-02 | 2006-08-17 | Sumco Corp | Process for producing bonding soi wafer, and the bonding soi wafer |
| CN102640267A (en) * | 2009-12-17 | 2012-08-15 | 朗姆研究公司 | Method and apparatus for processing bevel edge |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493099A (en) * | 2018-04-11 | 2018-09-04 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method |
| CN109950267A (en) * | 2019-03-26 | 2019-06-28 | 德淮半导体有限公司 | The production method of imaging sensor |
| CN109950267B (en) * | 2019-03-26 | 2021-03-30 | 德淮半导体有限公司 | Method for manufacturing image sensor |
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