CN108037951A - The interruption fast switch over method and device of a kind of DTP processors - Google Patents
The interruption fast switch over method and device of a kind of DTP processors Download PDFInfo
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- CN108037951A CN108037951A CN201711450043.XA CN201711450043A CN108037951A CN 108037951 A CN108037951 A CN 108037951A CN 201711450043 A CN201711450043 A CN 201711450043A CN 108037951 A CN108037951 A CN 108037951A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
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Abstract
Interruption fast switch over method and device, this method the invention discloses a kind of DTP processors include：Interrupt signal is received, the interrupt signal is switched to the general interrupt modes of IRQ including DTP processors by user model, or is switched to SWI traps patterns by user model, or is switched to WATCH monitoring points interrupt mode by user model；According to interrupt signal, numerical value in CPSR registers under user model is copied into the SPSR registers under the general interrupt modes of IRQ, the SPSR registers under SWI traps patterns or the SPSR registers under WATCH monitoring points interrupt mode respectively, completes the switching of general interrupt mode, SWI traps pattern or WATCH debugging modes from user model to IRQ.The present invention solves the problems, such as that traditional polycaryon processor interrupts switching judging complicated condition, is conducive to improve the treatment effeciency of risc processor.
Description
Technical field
The present invention relates to the interruption fast switch over method and device of a kind of DTP processors.
Background technology
RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) is two kinds of frameworks of current CPU.It
Difference lies in different CPU design theories and method.
The CPU of early stage is entirely CISC architecture, its purpose of design is to complete with minimum machine language instruction
The calculating task needed.For example for multiplying, on the CPU of CISC architecture, you may need such instruction：MUL
ADDRA can be multiplied and result is stored in ADDRA by ADDRA, ADDRB with the number in ADDRB.By ADDRA, ADDRB
In data read in register, the operation for being multiplied and resulting back into memory all relies on the logic that is designed in CPU to realize.
This framework can increase the complexity of CPU structures and the requirement to CPU techniques, but the exploitation for compiler is highly beneficial.Than
Such as above example, a*=b in c program can direct compilation be a multiplying order.There was only Intel and its compatibility today
CPU is also using CISC architecture.
RISC Architecture requires software to specify each operating procedure.If above example will be realized on RISC Architecture,
By ADDRA, the data in ADDRB read in register, and the operation for being multiplied and resulting back into memory must all be realized by software,
Such as：MOV A,ADDRA；MOV B,ADDRB；MUL A,B；STR ADDRA,A.This framework can reduce the complexity of CPU
And allow to produce CPU with better function under same technological level, but it is designed with wanting for higher for compiler
Ask.
At present, it is embedded in order to more adapt to as the performance and processing speed of multimedia chip is continuously improved in people
Multimedia processing requirement of handling up in real time, Reduced Instruction Set Computer risc processor have obtained rapid popularization and hair at full speed
Exhibition, the development of RISC technologies have reached its maturity and perfect, and application of the in the market to risc processor is very more.But in RISC
The design method being switched fast of breaking is also less.
Number of patent application is the Chengdu Jia Nahaiwei science and technology limited Company patents of invention of " CN201611027899.1 "
Apply " a kind of restructural signal processor ASIC frameworks and its reconstructing method ", restructural signal processor ASIC frameworks,
By RISC CPU by working status register described in bus access, for confirming the work shape of current RISC instruction resolver
State, when working status register is idle condition, the RISC CPU send configuration-direct to RISC instruction resolver, wait to refer to
By corresponding configuration information storage to configuration register after order parsing.The patent only provides the method that control is interrupted, but does not interrupt
The solution method of rapid translating.
Number of patent application is the hair of the Qingdao Hisense Mobile Communication Technology Co., Ltd. of " CN201610395264.0 "
Bright patent application " method and apparatus for distributing interruption in a kind of multi-core processor system ", it is directed to interrupt in polycaryon processor and asks
Summation distribution is interrupted, and realizes the interruption distribution flow under optimization polycaryon processor environment, and the processing for improving polycaryon processor is interrupted
Efficiency.Although giving the determination methods and switching flow for interrupting switching, just for polycaryon processor, monokaryon is not provided
Interruption switching method under processor environment, and judge to interrupt handoff procedure complexity, therefore be not suitable for common situation.
In conclusion existing technology for the problem of how being switched fast interrupted in risc processor, still lacks effective
Solution.
The content of the invention
For the deficiencies in the prior art, solve how quickly existing technology to cut for being interrupted in risc processor
The problem of changing, the present invention provides the interruption fast switch over method and device of a kind of DTP processors.
The first object of the present invention is to provide a kind of interruption fast switch over method of DTP processors.
To achieve these goals, the present invention is using a kind of following technical solution：
A kind of interruption fast switch over method of DTP processors, including：
Interrupt signal is received, the interrupt signal is switched to IRQ by user model including DTP processors and generally interrupts mould
Formula, or SWI traps patterns are switched to by user model, or WATCH monitoring points interrupt mode is switched to by user model；
According to interrupt signal, the numerical value in CPSR registers under user model is copied into the general interrupt modes of IRQ respectively
Under SPSR registers, the SPSR registers under SWI traps patterns or the SPSR under WATCH monitoring points interrupt mode deposit
Device, completes the switching of general interrupt mode, SWI traps pattern or WATCH debugging modes from user model to IRQ.
As further preferred solution, the CPSR registers or SPSR registers have current DTP processor modes
Flag bit, the flag bit include 00,01,10 and 11 4 kind of pattern, correspond to user model respectively, WATCH monitoring points interrupt mould
The general interrupt mode of formula, IRQ and SWI traps patterns.
As further preferred solution, this method further includes：After receiving interrupt signal, the interruption in interrupt signal is judged
Response condition, if meeting the general interrupt response conditions of IRQ, the general interrupt modes of IRQ are switched to by user model；If meet
SWI traps response conditions, then be switched to SWI traps patterns by user model；If meet WATCH monitoring points interrupt response bar
Part, then be switched to WATCH monitoring points interrupt mode by user model；Otherwise, program continues normal perform；
The general interrupt response conditions of IRQ is enable interruption and IRQ pins can use；The SWI traps respond bar
Part instructs to perform SWI；The WATCH monitoring points interrupt response condition for enable monitoring point and it is special monitoring point triggered.
As further preferred solution, under the user model, the SPSR register inaccessibles of DTP processors, if
The return value for putting SPSR registers is 0.
It is described to be switched to the general interrupt modes of IRQ, SWI traps moulds from user model as further preferred solution
When formula or WATCH debugging modes, using under stack pointer, link register, shift register or the general interrupt modes of IRQ, SWI
SPSR registers under under traps pattern or WATCH monitoring points interrupt mode.
As further preferred solution, the interrupt mode general from user model to IRQ, SWI traps pattern or
The specific steps of the switching of WATCH debugging modes include：
According to interrupt signal, forbid the transmitting of subsequent instructions signal；
Numerical value in CPSR registers under user model is copied under the general interrupt modes of IRQ respectively, SWI traps moulds
SPSR registers under under formula or WATCH monitoring points interrupt mode, preserve breakpoint address；
Identify the interruption source of interrupt signal, obtain stroke interrupt vector address；
Preserve the interruption clothes under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode
Each content of registers to be used in program of being engaged in；
Open interruption so that interrupting can be nested；
Perform the interruption clothes under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode
The substantive processing for program of being engaged in.
As further preferred solution, this method further include from the general interrupt modes of IRQ, SWI traps pattern or
WATCH debugging modes to user model switching, perform the general interrupt modes of IRQ under, under SWI traps patterns or WATCH prison
Include after the substantive processing of interrupt service routine under control point interrupt mode：
The Central Shanxi Plain is broken, and ensures that in-situ FTIR spectroelectrochemitry process is no longer interrupted signal interruption；
Recover the interruption clothes under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode
The content of registers used in business program, and recover to preserve the scene under user model by hardware；
DTP processors are by under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode
Under content in SPSR registers is stored to user model again in CPSR registers, complete from the general interrupt modes of IRQ, SWI
Traps pattern or WATCH debugging modes return to the breakpoint succession execution for being interrupted program to the switching of user model.
As further preferred solution, four instruction depth are further included in the DTP processors prefetches buffering area, is used for
Branch prediction.
The second object of the present invention is to provide a kind of computer-readable recording medium.
To achieve these goals, the present invention is using a kind of following technical solution：
A kind of computer-readable recording medium, is stored with a plurality of instruction, and described instruction is loaded by processor and performed following
Processing：
Interrupt signal is received, the interrupt signal is switched to IRQ by user model including DTP processors and generally interrupts mould
Formula, or SWI traps patterns are switched to by user model, or WATCH monitoring points interrupt mode is switched to by user model；
According to interrupt signal, the numerical value in CPSR registers under user model is copied into the general interrupt modes of IRQ respectively
Under SPSR registers, the SPSR registers under SWI traps patterns or the SPSR under WATCH monitoring points interrupt mode deposit
Device, completes the switching of general interrupt mode, SWI traps pattern or WATCH monitoring points interrupt mode from user model to IRQ.
The third object of the present invention is to provide a kind of interruption apparatus for fast switching of DTP processors.
To achieve these goals, the present invention is using a kind of following technical solution：
A kind of interruption apparatus for fast switching of DTP processors, including DTP processors, are used for realization each instruction；And storage
Device, for storing a plurality of instruction, it is characterised in that described instruction is loaded by DTP processors and performs following processing：
Interrupt signal is received, the interrupt signal is switched to IRQ by user model including DTP processors and generally interrupts mould
Formula, or SWI traps patterns are switched to by user model, or WATCH monitoring points interrupt mode is switched to by user model；
According to interrupt signal, the numerical value in CPSR registers under user model is copied into the general interrupt modes of IRQ respectively
Under SPSR registers, the SPSR registers under SWI traps patterns or the SPSR under WATCH monitoring points interrupt mode deposit
Device, completes the switching of general interrupt mode, SWI traps pattern or WATCH monitoring points interrupt mode from user model to IRQ.
Beneficial effects of the present invention：
1st, the interruption fast switch over method and device of a kind of DTP processors of the present invention, solves traditional multinuclear
Processor interrupts the problem of switching judging complicated condition, is conducive to improve the treatment effeciency of risc processor.
2nd, the interruption fast switch over method and device of a kind of DTP processors of the present invention, only with DTP processors
Interruption is switched fast, and across the judgement of the complex external condition such as RISC instruction resolver, is conducive to improve transfer efficiency.
Brief description of the drawings
Fig. 1 is flow chart of the method for the present invention.
Embodiment：
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment, belongs to the scope of protection of the invention.
It is noted that described further below is all illustrative, it is intended to provides further instruction to the application.It is unless another
Indicate, all technical and scientific terms that the present embodiment uses have and the application person of an ordinary skill in the technical field
Normally understood identical meanings.
It should be noted that term used herein above is merely to describe embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is also intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " bag
Include " when, it indicates existing characteristics, step, operation, device, component and/or combinations thereof.
It should be noted that the flow chart and block diagram in attached drawing show method according to various embodiments of the present disclosure and
Architectural framework in the cards, function and the operation of system.It should be noted that each square frame in flow chart or block diagram can represent
A part for one module, program segment or code, the module, program segment or a part of of code can include one or more
A executable instruction for being used for realization the logic function of defined in each embodiment.It should also be noted that at some alternately
Realization in, the function that is marked in square frame can also occur according to the order different from being marked in attached drawing.For example, two connect
The square frame even represented can essentially perform substantially in parallel, or they can also be performed in a reverse order sometimes,
This depends on involved function.It should also be noted that each square frame and flow chart in flow chart and/or block diagram
And/or the combination of the square frame in block diagram, it can be come using the dedicated hardware based system of functions or operations as defined in execution
Realize, or can be realized using the combination of specialized hardware and computer instruction.
In the case where there is no conflict, the feature in the embodiment and embodiment in the application can be mutually combined.Tie below
Closing attached drawing, the invention will be further described with embodiment.
Embodiment 1：
The purpose of the present embodiment 1 is to provide a kind of interruption fast switch over method of DTP processors.
To achieve these goals, the present invention is using a kind of following technical solution：
As shown in Figure 1,
A kind of interruption fast switch over method of DTP processors, including：
Step (1)：Receive interrupt signal, the interrupt signal includes DTP processors, and by user model to be switched to IRQ general
Interrupt mode, or SWI traps patterns are switched to by user model, or WATCH monitoring points are switched to by user model and interrupt mould
Formula；
Step (2)：According to interrupt signal, it is general that the numerical value in CPSR registers under user model is copied into IRQ respectively
Under SPSR registers under interrupt mode, the SPSR registers under SWI traps patterns or WATCH monitoring points interrupt mode
SPSR registers, complete cutting for from user model to IRQ general interrupt mode, SWI traps pattern or WATCH debugging modes
Change.
The DTP processor overall architectures of the present invention are as follows：
DTP processor architectures are based on Reduced Instruction Set Computer (RISC) principle.Its core includes a three-level stream
Waterline is so as to efficiently process instruction.DTP processors are a scalar processors.Instruction width is 16 bit wides.Internal storage data road
Footpath is 32 bit wides, it allows to obtain two instructions in a main memory cycle.
DTP processors have 16 general registers.One in 16 general registers is program counter, and one is chain
Connect register.General register is 32 bit wides.16 32 general registers can use at any time.
The specific function that general register in DTP processors has：R15 is program counter；R14 is stack pointer；
R13 is link register.
DTP processors support multiple modes of operation, including the general interrupt mode of user model, IRQ, SWI traps patterns
With WATCH monitoring points interrupt mode.
Wherein, user model for user's normal procedure perform state, the general interrupt modes of IRQ, SWI traps pattern and
WATCH monitoring points interrupt mode is interrupt status.
The input mode of each operator scheme is as follows：
1. after system replacement, DTP processors enter user model；
2. enabling interruption and IRQ pins can use, DTP processors enter IRQ patterns；
3. when SWI is instructed and performed, DTP processors enter SWI patterns；
4. enabling monitoring point and special monitoring point having triggered, DTP processors enter WATCH patterns.
When DTP is switched to a kind of interrupt mode (in the general interrupt modes of IRQ, SWI traps pattern or WATCH monitoring points
Disconnected pattern) when, suitable " banked " register (stack pointer/link register), rather than user's mould of standard will be used
Formula register., using under stack pointer, link register, shift register or the general interrupt modes of IRQ, SWI traps patterns
SPSR registers under lower or WATCH monitoring points interrupt mode.Table 1 is the core register of private code stream handle, in table
Shadow register shows that register is " banked " type.,
Table 1
Except under shift register, CPSR registers and the general interrupt modes of IRQ, under SWI traps patterns or WATCH prison
Outside SPSR registers under control point interrupt mode, all internal registers are all 32 bit wides.Shift register is 5 bit wides
, each of CPSR registers and SPSR registers include 11 information.
In the present embodiment, the CPSR registers or SPSR registers have current DTP processor modes flag bit, institute
Stating flag bit includes 00,01,10 and 11 4 kind of pattern, and it is general to correspond to user model, WATCH monitoring points interrupt mode, IRQ respectively
Interrupt mode and SWI traps patterns.
The reset value of all status registers for " 00001-00000 " (user model, prediction enable, interrupt disabling, it is assumed that
Backward branch receives, it is assumed that obtains data access, and all Status Flags in advance as 0).The form of CPSR/SPSR registers
Such as table 2.
Table 2
The general interrupt response conditions of IRQ is enable interruption and IRQ pins can use；The SWI traps respond bar
Part instructs to perform SWI；The WATCH monitoring points interrupt response condition for enable monitoring point and it is special monitoring point triggered.
Under the user model, the SPSR register inaccessibles of DTP processors, set SPSR registers return value be
0。
In the present embodiment, the specific steps of the interrupt processing include：From user model to IRQ general interrupt mode,
The switching of SWI traps pattern or WATCH debugging modes, after performing interrupt routine, from the general interrupt modes of IRQ, SWI traps
The switching of pattern or WATCH debugging modes to user model.
Step (2-1)：DTP processors receive interrupt signal after, judge in interrupt signal interrupt response condition (shielding,
Priority), if meeting the general interrupt response conditions of IRQ, the general interrupt modes of IRQ are switched to by user model；If meet SWI
Traps response condition, then be switched to SWI traps patterns by user model；If meeting WATCH monitoring points interrupt response condition,
WATCH monitoring points interrupt mode is then switched to by user model；Otherwise, program continues normal perform.
Step (2-2)：According to interrupt signal, forbid the transmitting of subsequent instructions signal；It will be performed with the interrupt instruction of transmitting
Complete.
Step (2-3)：Numerical value in CPSR registers under user model is copied under the general interrupt modes of IRQ respectively,
SPSR registers under SWI traps patterns or under WATCH monitoring points interrupt mode, preserve breakpoint address；, with preserving breakpoint
Location.
Step (2-4)：Identify the interruption source of interrupt signal, obtain stroke interrupt vector address
Step (2-5)：Preserve under the general interrupt modes of IRQ, under SWI traps patterns or WATCH monitoring points interrupt mode
Under interrupt service routine in each content of registers to be used.
Step (2-6)：Open interruption so that interrupting can be nested；
Step (2-7)：Perform under the general interrupt modes of IRQ, under SWI traps patterns or WATCH monitoring points interrupt mode
Under interrupt service routine substantive processing.
Step (2-8)：The Central Shanxi Plain is broken, and ensures that in-situ FTIR spectroelectrochemitry process is no longer interrupted signal interruption
Step (2-9)：Recover under the general interrupt modes of IRQ, under SWI traps patterns or WATCH monitoring points interrupt mode
Under interrupt service routine in the content of registers that uses, and recover to preserve the scene under user model by hardware.
Step (2-10)：DTP processors by under the general interrupt modes of IRQ, under SWI traps patterns or WATCH monitoring points
Under the content in SPSR registers under interrupt mode is stored to user model again in CPSR registers, complete general from IRQ
Interrupt mode, SWI traps pattern or WATCH debugging modes to the switching of user model, return be interrupted the breakpoint of program after
It is continuous to perform.
In the present embodiment, four instruction depth are further included in the DTP processors prefetches buffering area, pre- for branch
Survey.Prediction is that the hypothesis forward or backward carried out on static basis is set.Branch prediction may be completely disabled.Instruction set quilt
It is designed to support a complete downlink storehouse.
Embodiment 2：
The purpose of the present embodiment 2 is to provide a kind of computer-readable recording medium.
To achieve these goals, the present invention is using a kind of following technical solution：
A kind of computer-readable recording medium, is stored with a plurality of instruction, and described instruction is loaded by processor and performed following
Processing：
Interrupt signal is received, the interrupt signal is switched to IRQ by user model including DTP processors and generally interrupts mould
Formula, or SWI traps patterns are switched to by user model, or WATCH monitoring points interrupt mode is switched to by user model；
According to interrupt signal, the numerical value in CPSR registers under user model is copied into the general interrupt modes of IRQ respectively
Under SPSR registers, the SPSR registers under SWI traps patterns or the SPSR under WATCH monitoring points interrupt mode deposit
Device, completes the switching of general interrupt mode, SWI traps pattern or WATCH monitoring points interrupt mode from user model to IRQ.
Embodiment 3：
The purpose of the present embodiment 3 is to provide a kind of interruption apparatus for fast switching of DTP processors.
To achieve these goals, the present invention is using a kind of following technical solution：
A kind of interruption apparatus for fast switching of DTP processors, including DTP processors, are used for realization each instruction；And storage
Device, for storing a plurality of instruction, it is characterised in that described instruction is loaded by DTP processors and performs following processing：
Interrupt signal is received, the interrupt signal is switched to IRQ by user model including DTP processors and generally interrupts mould
Formula, or SWI traps patterns are switched to by user model, or WATCH monitoring points interrupt mode is switched to by user model；
According to interrupt signal, the numerical value in CPSR registers under user model is copied into the general interrupt modes of IRQ respectively
Under SPSR registers, the SPSR registers under SWI traps patterns or the SPSR under WATCH monitoring points interrupt mode deposit
Device, completes the switching of general interrupt mode, SWI traps pattern or WATCH monitoring points interrupt mode from user model to IRQ.
It should be noted that in embodiment 2 and embodiment 3, computer program product can include computer-readable deposit
Storage media, containing the computer-readable program instructions for performing various aspects of the disclosure.Computer-readable storage medium
Matter can keep and store the tangible device that the instruction that equipment uses is performed by instruction.Computer-readable recording medium example
Such as can be-- but be not limited to-- storage device electric, magnetic storage apparatus, light storage device, electromagnetism storage device, semiconductor
Storage device or above-mentioned any appropriate combination.More specifically example (the non exhaustive row of computer-readable recording medium
Table) include：Portable computer diskette, hard disk, random access memory (RAM), read-only storage (ROM), erasable type may be programmed
Read-only storage (EPROM or flash memory), static RAM (SRAM), Portable compressed disk read-only storage (CD-
ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical coding equipment, the punch card for being for example stored thereon with instruction or
Groove internal projection structure and above-mentioned any appropriate combination.Computer-readable recording medium used herein above is not solved
It is interpreted as instantaneous signal in itself, the electromagnetic wave of such as radio wave or other Free propagations, pass through waveguide or other transmission mediums
The electromagnetic wave (for example, the light pulse for passing through fiber optic cables) of propagation or the electric signal transmitted by electric wire.
Computer-readable program instructions described herein can be downloaded to from computer-readable recording medium it is each calculate/
Processing equipment, or outer computer or outer is downloaded to by network, such as internet, LAN, wide area network and/or wireless network
Portion's storage device.Network can include copper transmission cable, optical fiber is transmitted, is wirelessly transferred, router, fire wall, interchanger, gateway
Computer and/or Edge Server.Adapter or network interface in each calculating/processing equipment are received from network to be counted
Calculation machine readable program instructions, and the computer-readable program instructions are forwarded, for the meter being stored in each calculating/processing equipment
In calculation machine readable storage medium storing program for executing.
Computer program instructions for performing present disclosure operation can be assembly instruction, instruction set architecture (ISA)
Instruction, machine instruction, machine-dependent instructions, microcode, firmware instructions, condition setup data or with one or more program
The source code or object code that any combination of language is write, programming language of the programming language including object-oriented-such as
C++ etc., and conventional procedural programming languages-such as " C " language or similar programming language.Computer-readable program refers to
Order fully can on the user computer be performed, partly performed on the user computer, the software kit independent as one
Perform, part performs or completely on remote computer or server on the remote computer on the user computer for part
Perform.In the situation of remote computer is related to, remote computer can be by the network of any kind-include LAN
(LAN) or wide area network (WAN)-subscriber computer is connected to, or, it may be connected to outer computer (such as utilize internet
Service provider passes through Internet connection).In certain embodiments, believe by using the state of computer-readable program instructions
Breath comes personalized customization electronic circuit, such as programmable logic circuit, field programmable gate array (FPGA) or programmable logic
Array (PLA), the electronic circuit can perform computer-readable program instructions, so as to fulfill various aspects in the present disclosure.
It should be noted that although being referred to some modules or submodule of equipment in detailed descriptions above, but it is this
Division is merely exemplary rather than enforceable.In fact, in accordance with an embodiment of the present disclosure, two or more above-described moulds
The feature and function of block can embody in a module.Conversely, the feature and function of an above-described module can be with
It is further divided into being embodied by multiple modules.
Beneficial effects of the present invention：
1st, the interruption fast switch over method and device of a kind of DTP processors of the present invention, solves traditional multinuclear
Processor interrupts the problem of switching judging complicated condition, is conducive to improve the treatment effeciency of risc processor.
2nd, the interruption fast switch over method and device of a kind of DTP processors of the present invention, only with DTP processors
Interruption is switched fast, and across the judgement of the complex external condition such as RISC instruction resolver, is conducive to improve transfer efficiency.
The foregoing is merely the preferred embodiment of the application, the application is not limited to, for the skill of this area
For art personnel, the application can have various modifications and variations.It is all within spirit herein and principle, made any repair
Change, equivalent substitution, improvement etc., should be included within the protection domain of the application.
Claims (10)
- A kind of 1. interruption fast switch over method of DTP processors, it is characterised in that including：Interrupt signal is received, the interrupt signal is switched to the general interrupt modes of IRQ including DTP processors by user model, or SWI traps patterns are switched to by user model, or WATCH monitoring points interrupt mode is switched to by user model；According to interrupt signal, the numerical value in CPSR registers under user model is copied under the general interrupt modes of IRQ respectively SPSR registers, the SPSR registers under SWI traps patterns or the SPSR registers under WATCH monitoring points interrupt mode, it is complete Into the switching of general interrupt mode, SWI traps pattern or WATCH debugging modes from user model to IRQ.
- 2. according to the method described in claim 1, it is characterized in that, the CPSR registers or SPSR registers have currently DTP processor mode flag bits, the flag bit include 00,01,10 and 11 4 kind of pattern, correspond to user model, WATCH respectively The general interrupt mode of monitoring point interrupt mode, IRQ and SWI traps patterns.
- 3. according to the method described in claim 1, it is characterized in that, this method further includes：After receiving interrupt signal, judge to interrupt Interrupt response condition in signal, if meeting the general interrupt response conditions of IRQ, is switched to IRQ by user model and generally interrupts Pattern；If meeting SWI traps response conditions, SWI traps patterns are switched to by user model；If meeting, WATCH is monitored Point interrupt response condition, then be switched to WATCH monitoring points interrupt mode by user model；Otherwise, program continues normal perform；The general interrupt response conditions of IRQ is enable interruption and IRQ pins can use；The SWI traps response condition is Perform SWI instructions；The WATCH monitoring points interrupt response condition for enable monitoring point and it is special monitoring point triggered.
- 4. according to the method described in claim 3, it is characterized in that, under the user model, the SPSR registers of DTP processors Inaccessible, the return value for setting SPSR registers are 0.
- 5. according to the method described in claim 3, it is characterized in that, it is described from user model be switched to the general interrupt modes of IRQ, When SWI traps pattern or WATCH debugging modes, using stack pointer, link register, shift register or IRQ it is general in Under disconnected pattern, the SPSR registers under SWI traps patterns or under WATCH monitoring points interrupt mode.
- 6. according to the method described in claim 3, it is characterized in that, the interrupt mode general from user model to IRQ, SWI The specific steps of the switching of traps pattern or WATCH debugging modes include：According to interrupt signal, forbid the transmitting of subsequent instructions signal；Numerical value in CPSR registers under user model is copied under the general interrupt modes of IRQ respectively, under SWI traps patterns Or the SPSR registers under WATCH monitoring points interrupt mode, preserve breakpoint address；Identify the interruption source of interrupt signal, obtain stroke interrupt vector address；Preserve the interruption service journey under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode Each content of registers to be used in sequence；Open interruption so that interrupting can be nested；Perform the interruption service journey under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode The substantive processing of sequence.
- 7. according to the method described in claim 6, it is characterized in that, this method further include it is soft from the general interrupt modes of IRQ, SWI Interrupt mode or WATCH debugging modes are performed under the general interrupt modes of IRQ, under SWI traps patterns to the switching of user model Or include after the substantive processing of the interrupt service routine under WATCH monitoring points interrupt mode：The Central Shanxi Plain is broken, and ensures that in-situ FTIR spectroelectrochemitry process is no longer interrupted signal interruption；Recover the interruption service journey under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode The content of registers used in sequence, and recover to preserve the scene under user model by hardware；DTP processors are by the SPSR under the general interrupt modes of IRQ, under SWI traps patterns or under WATCH monitoring points interrupt mode Under content in register is stored to user model again in CPSR registers, complete from the general interrupt modes of IRQ, SWI are soft Disconnected pattern or WATCH debugging modes return to the breakpoint succession execution for being interrupted program to the switching of user model.
- 8. according to the method described in claim 1, it is characterized in that, the pre- of four instruction depth is further included in the DTP processors Buffering area is taken, for branch prediction.
- 9. a kind of computer-readable recording medium, it is characterised in that be stored with a plurality of instruction, described instruction is loaded simultaneously by processor Perform such as claim 1-8 any one of them methods.
- 10. a kind of control device, including processor, are used for realization each instruction；And storage device, for storing a plurality of instruction, It is characterized in that, described instruction is loaded by processor and performed such as claim 1-8 any one of them methods.
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