CN108021386B - Server with node latching function and node latching method thereof - Google Patents
Server with node latching function and node latching method thereof Download PDFInfo
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- CN108021386B CN108021386B CN201711237814.7A CN201711237814A CN108021386B CN 108021386 B CN108021386 B CN 108021386B CN 201711237814 A CN201711237814 A CN 201711237814A CN 108021386 B CN108021386 B CN 108021386B
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Abstract
The invention discloses a server with a node latching function, which comprises a first storage medium, a second storage medium, an information transmitter, an information controller and a multiplexer. The first storage medium and the second storage medium are respectively used for storing the updating firmware data and the current firmware data of the processor. The information transmitter is electrically connected to the output node of the processor and used for outputting the processing signal. The information controller is used for sending firmware updating information. The multiplexer is used for outputting a control signal to the output node according to the processing signal when receiving the firmware updating information, so that the output node returns a feedback signal to the multiplexer and the information transmitter according to the control signal to latch the potential of the output node. The invention also discloses a node latching method.
Description
Technical Field
The present invention relates to a server with a node latching function and a node latching method thereof, and more particularly, to a server with a node latching function and a node latching method thereof for firmware update of a processor.
Background
Generally, a system with very high real-time requirement, such as a data center, a storage system, a core network switching system, etc., needs to be in an operating state at any time, and cannot be powered off and restarted. Therefore, the currently important core systems are all prone to online upgrade functionality of firmware. For a system that is processing a service, an upgrade processor (e.g., a complex programmable logic device) is required to add a new function or perform debugging after the system is brought online.
However, since the processor mainly plays a role in power timing control, power management, reset control, management, and the like of the system in the system, it is very difficult to achieve the purpose that the system does not power down and the service of the system in operation (i.e., the hetless upgrade) is not affected when the firmware of the processor is upgraded. After most processors are upgraded, the new firmware is effective only after the system is powered off and restarted. In view of this, how to implement the firmware upgrade function of the processor without affecting the system operation is one of the important issues in the related art.
Disclosure of Invention
The invention provides a server with a node latching function and a node latching method thereof, which can realize firmware upgrade of a processor under the condition of not influencing the current operation of a system by latching the potential of a node of the processor.
The invention discloses a server with a node latching function, which comprises a first storage medium, a second storage medium, an information transmitter, an information controller and a multiplexer. The first storage medium is used for storing updated firmware data about a processor in the server. The second storage medium is used for storing the current firmware data of the processor. The information transmitter is electrically connected to the output node of the processor and used for outputting the processing signal. The information controller is electrically connected with the information transmitter and is used for transmitting normal operation information or firmware updating information. The multiplexer is electrically connected with the information transmitter and the information controller. The multiplexer is used for outputting a control signal to the output node according to the processing signal when receiving the firmware updating information, so that the output node returns a feedback signal to the multiplexer and the information transmitter according to the control signal to latch the potential of the output node, and the processor extracts the updating firmware data from the first storage medium according to the updating command to overwrite the current firmware data in the second storage medium, so that the processor operates by updating the firmware data. Before the multiplexer receives the firmware updating information, the processor runs with the current firmware data, and after the processor runs for a period of time with the updating firmware data, the information controller sends normal operation information to unlock the potential of the output node.
The invention discloses a node latching method of a server, which comprises the following steps: transmitting the updated firmware data associated with the processor in the server through a transmission path and storing the updated firmware data in a first storage medium; sending firmware update information to the information transmitter and the multiplexer by the information controller; outputting a control signal to an output node of the processor by the multiplexer according to the processing signal, and enabling the output node to return a feedback signal to the multiplexer and the information transmitter according to the control signal so as to latch the potential of the output node; after the output node is latched, the processor extracts the updating firmware data from the first storage medium according to the updating command to overwrite the current firmware data in the second storage medium of the processor, so that the processor operates by the updating firmware data; after the processor runs for a period of time by updating the firmware data, the information controller sends normal operation information to the information transmitter and the multiplexer so as to unlock the potential of the output node.
In summary, in the server with node latching function and the node latching method of the server according to the present invention, the multiplexer is mainly used in combination with the information controller, so that when the server needs to update the firmware of the internal processor, the potential of the output node of the processor can be latched, thereby achieving the purpose of completing the firmware update of the processor without affecting the current operation of the server system.
The foregoing summary of the invention, as well as the following detailed description of the embodiments, is provided to illustrate and explain principles of the invention and to provide further explanation of the invention as claimed.
Drawings
Fig. 1 is a system architecture diagram of a server with node latching function according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating a method for node latching of a server according to an embodiment of the invention.
Wherein, the reference numbers:
1 Server
10 processor
101 information transmitter
103 information controller
105 multiplexer
NS normal operation information
HS firmware update information
PS processing signals
CS control signal
FS feedback signal
0. 1 channel
IOC output module
N1 output node
Detailed Description
The detailed features and advantages of the present invention are described in detail in the embodiments below, which are sufficient for anyone skilled in the art to understand the technical contents of the present invention and to implement the present invention, and the related objects and advantages of the present invention can be easily understood by anyone skilled in the art according to the disclosure of the present specification, the protection scope of the claims and the attached drawings. The following examples further illustrate aspects of the present invention in detail, but are not intended to limit the scope of the invention in any way.
Referring to fig. 1, fig. 1 is a system architecture diagram of a server with a node latching function according to an embodiment of the present invention. As shown in fig. 1, the server 1 includes a processor 10 having a first storage medium and a second storage medium (not shown), an information transmitter 101, an information controller 103, and a multiplexer 105. The first storage medium is used for storing updated firmware data related to the processor 10. The second storage medium is used to store current firmware data for the processor 10. In practice, the processor 10 is a Complex Programmable Logic Device (CPLD) disposed inside the server 1, the first storage medium is a flash memory (flash memory) of the processor 10, and the second storage medium is a Random Access Memory (RAM) of the processor 10.
The information transmitter 101 is electrically connected to the output node N1 in the output module IOC of the processor 10 and is configured to output the processing signal PS. The information controller 103 is electrically connected to the information transmitter 101 and the multiplexer 105, and the information controller 103 is configured to selectively transmit the normal operation information NS or the firmware update information HS. In one example, information controller 103 interfaces or I through JTAG2The C interface sends the normal operation information or the firmware update information to the information transmitter 101 and the multiplexer 105. The multiplexer 105 is electrically connected to the information transmitter 101 and the information controller 103. The multiplexer 105 is configured to output the control signal CS to the output node N1 according to the processing signal PS when receiving the firmware update information HS, so that the output node N1 returns the feedback signal FS to the multiplexer 105 and the information transmitter 101 according to the control signal CS to latch the potential of the output node N1.
Specifically, in a normal state (i.e. no firmware update is performed), when the multiplexer 105 has not received the firmware update information HS, the processor 10 operates with the current firmware data, and the multiplexer 105 turns on the channel 1 to transmit the control signal CS to the output node N1 of the processor 10 through the channel 1 according to the processing signal PS of the information transmitter 101 to control/manage other components inside the server 1. When the server 1 needs to update the firmware of the internal processor 10, the information controller 103 first sends the firmware update information HS to notify the information transmitter 101 and the multiplexer 105 that the firmware update procedure of the processor 10 is about to be performed.
After receiving the firmware update information HS, the multiplexer 105 outputs the control signal CS to the output node N1 according to the current processing signal PS and switches the transmission channel from channel 1 to channel 0, and then the output node N1 returns the feedback signal FS to the channel 0 of the multiplexer 105 and the information transmitter 101 according to the control signal CS. At this time, since the channel 0 of the multiplexer 105 is in the on state, the potential of the control signal CS output from the channel 0 of the multiplexer 105 is substantially the same as the potential of the feedback signal FS of the output node N1. Thereby, the potential of the output node N1 can be latched. When the voltage level at the output node N1 is latched, the processor 10 in the server 1 retrieves the firmware update data from the first storage medium according to an update command, and overwrites the current firmware data in the second storage medium with the firmware update data, so that the processor 10 operates with the firmware update data. After the processor 10 runs for a period of time with the updated firmware data, the information controller 103 sends the normal operation information NS to unlock the potential of the output node N1, thereby completing the firmware update of the processor 10.
In other words, the processor 10 in the server 1 according to the present invention switches the multiplexer 105 such that the voltage level inputted to the channel 0 of the multiplexer 105 is substantially the same as the voltage level of the output node N1, thereby keeping the voltage level of the output node N1 consistent during the firmware upgrade process. Thereby, the firmware update program of the processor 10 can be completed without powering off the server 1 system. In one embodiment, the level of the processing signal PS is determined by the normal operation information NS or the firmware update information HS sent by the information controller 103. Specifically, the information transmitter 101 determines the level of the output processing signal PS according to the received normal operation information NS or the firmware update information HS.
In one embodiment, when the information transmitter 101 and the multiplexer 105 both receive the normal operation information NS, the processing signal PS has a different potential than the feedback signal FS. On the contrary, in another embodiment, when the information transmitter 101 and the multiplexer 105 both receive the firmware update information HS, the processing signal PS has substantially the same level as the feedback signal FS. That is, the information transmitter 101 does not use the feedback signal FS as the processing signal PS before the firmware update of the processor 10 is performed, so the potential of the processing signal PS is different from the potential of the feedback signal FS. On the other hand, if the information transmitter 101 receives the firmware update information HS and starts updating the firmware of the processor 10, the information transmitter 101 uses the feedback signal FS of the output node N1 as the processing signal PS, and therefore the potential of the processing signal PS matches the potential of the feedback signal FS. When the firmware update is completed, the message controller 103 then sends the normal operation message NS to unlock the output node N1. At this point, multiplexer 105 switches back to channel 1 to conduct. In the foregoing embodiment, assuming that the processor 10 is originally an eight-bit binary adder and is upgraded to an eight-bit binary subtractor by the upgrade procedure, since the initial state of the processor 10 is controlled by the feedback signal FS, if the processor 10 serving as the adder before the upgrade is increased by 1 each time to 100, the processor 10 serving as the subtractor after the upgrade is sequentially decreased by 1 from 100.
Referring to fig. 1 and fig. 2 together, fig. 2 is a flowchart illustrating a method for node latching of a server according to an embodiment of the present invention. The node latch method shown in fig. 2 is applicable to the server 1 of fig. 1. As shown in the figure, in step S201, the firmware update data associated with the processor 10 in the server 1 is transmitted via a transmission path and stored in the first storage medium. In thatIn practice, the transmission path may be JTAG interface or I2C interface, and the first storage medium may be a flash memory (flash memory). In step S203, the firmware update information HS is sent to the information transmitter 101 and the multiplexer 105 by the information controller 103. In step S205, the multiplexer 105 outputs the control signal CS to the output node N1 of the processor 10 according to the processing signal PS, so that the output node N1 returns the feedback signal FS to the multiplexer 105 and the information transmitter 101 according to the control signal CS to latch the potential of the output node N1. In other words, before the firmware update, the multiplexer 105 is turned on the channel 1, and the processing signal PS output by the information transmitter and the control signal CS output by the multiplexer 105 are controlled by the processor 10 itself to control and manage other external components through the output node N1. When the multiplexer 105 receives the firmware update information HS, the channel 0 is turned on, and the input voltage level of the channel 0 is the same as the voltage level of the output node N1, so that the voltage level of the output node N1 can be kept the same to achieve the purpose of node voltage latching. The processing signal PS output from the information controller 101 also has the same potential as the feedback signal FS.
In one embodiment, the level of the processing signal PS is determined by the normal operation information NS or the firmware update information HS sent by the information controller 103. That is, the information transmitter 101 determines the potential of the output processing signal PS according to the received normal operation information NS or the firmware update information HS. In one example, when the information transmitter 101 and the multiplexer 105 both receive the normal operation information NS, the processing signal PS has a different potential from the feedback signal FS. In another example, when the information transmitter 101 and the multiplexer 105 both receive the firmware update information HS, the processing signal PS has substantially the same potential as the feedback signal FS. In detail, the information transmitter 101 does not use the feedback signal FS as the processing signal PS before the firmware update, so the potential of the processing signal PS is not the same as the potential of the feedback signal FS. If the firmware is updated, the information transmitter 101 uses the feedback signal FS of the output node N1 as the processing signal PS, and therefore the processing signal PS has the same potential as the feedback signal FS.
In step S207, after the output node N1 is latched, the processor 10 fetches the update firmware data from the first storage medium according to the update command to overwrite the current firmware data in the second storage medium of the processor 10, so that the processor 10 operates with the update firmware data. Since the output node N1 is latched, the firmware update process of the processor 10 does not affect the tasks being performed by other components within the server 1. Next, in step S209, after the processor 10 runs for a period of time with the updated firmware data, the message controller 103 sends the normal operation message NS to the message transmitter 101 and the multiplexer 105 to unlock the voltage level of the output node N1. At this time, the server 1 returns to the normal operation state, and the internal processor 10 can then perform the original tasks, such as power management, power timing control, etc.
In summary, in the server with node latching function and the node latching method of the server according to the present invention, the multiplexer is mainly used in combination with the information controller, so that when the server needs to update the firmware of the internal processor, the multiplexer is switched to keep the potentials of the output nodes of the processor consistent, thereby achieving the latching effect, and thus the server system is powered off and the firmware update of the processor is completed without affecting the current operation of the server system.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A server having a node latch function, comprising:
a first storage medium for storing an update firmware data related to a processor in the server;
a second storage medium for storing a current firmware data associated with the processor;
the information transmitter is electrically connected with an output node of the processor and is used for outputting a processing signal;
the information controller is electrically connected with the information transmitter and used for transmitting normal operation information or firmware update information; and
a multiplexer electrically connected to the information transmitter and the information controller, the multiplexer outputting a control signal to the output node according to the processing signal when receiving the firmware update information, so that the output node returns a feedback signal to the multiplexer and the information transmitter according to the control signal, so that the potential of the control signal is substantially the same as the feedback signal, thereby latching the potential of the output node, and the processor extracting the update firmware data from the first storage medium according to an update command to overwrite the current firmware data in the second storage medium, so that the processor operates with the update firmware data;
before the multiplexer receives the firmware updating information, the processor runs with the current firmware data, and after the processor runs with the updating firmware data for a period of time, the information controller sends the normal operation information to unlock the potential of the output node.
2. The server according to claim 1, wherein the level of the processing signal is determined by the normal operation information or the firmware update information sent by the information controller.
3. The server according to claim 2, wherein the processing signal is at the same potential as the feedback signal when the information transmitter and the multiplexer both receive the firmware update information.
4. The server according to claim 3, wherein the processing signal is not at the same level as the feedback signal when the message transmitter and the multiplexer both receive the normal operation message.
5. The server of claim 1, wherein the message controller is configured to communicate with the client via a JTAG interface or an I2The C interface sends the normal operation information or the firmware updating information to the information transmitter and the multiplexer.
6. A node latching method of a server, comprising:
transmitting updated firmware data associated with a processor in the server through a transmission path, and storing the updated firmware data in a first storage medium;
sending a firmware update message to an information transmitter and a multiplexer by an information controller;
outputting a control signal to an output node of the processor by the multiplexer according to the processing signal, and enabling the output node to return a feedback signal to the multiplexer and the information transmitter according to the control signal so as to enable the electric potential of the control signal to be substantially the same as that of the feedback signal, and further latching the electric potential of the output node;
after the output node is latched, the processor extracts the updating firmware data from the first storage medium according to an updating command to overwrite current firmware data in a second storage medium of the processor, so that the processor operates with the updating firmware data; and
when the processor runs for a period of time with the updated firmware data, the information controller sends a normal operation information to the information transmitter and the multiplexer to unlock the potential of the output node.
7. The node latching method according to claim 6, wherein the level of the processing signal is determined by the normal operation information or the firmware update information sent by the information controller.
8. The node latching method according to claim 7, wherein when the information transmitter and the multiplexer both receive the firmware update information, the processing signal has the same potential as the feedback signal.
9. The node latching method according to claim 7, wherein when the information transmitter and the multiplexer both receive the normal operation information, the processing signal and the feedback signal are different in potential.
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| FI972843A (en) * | 1996-07-05 | 1998-01-06 | Nec Corp | computer Systems |
| CN101727333A (en) * | 2008-10-31 | 2010-06-09 | 英业达股份有限公司 | Method for updating firmware in microprocessor and firmware updating system |
| CN103064477A (en) * | 2013-01-25 | 2013-04-24 | 浪潮电子信息产业股份有限公司 | Method for designing server motherboard |
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