CN108010906A - A kind of package structure of semiconductor device and method for packing - Google Patents
A kind of package structure of semiconductor device and method for packing Download PDFInfo
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- CN108010906A CN108010906A CN201711224791.6A CN201711224791A CN108010906A CN 108010906 A CN108010906 A CN 108010906A CN 201711224791 A CN201711224791 A CN 201711224791A CN 108010906 A CN108010906 A CN 108010906A
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- chipset
- side wall
- slide glass
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- lead
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000012856 packing Methods 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims description 50
- 239000011521 glass Substances 0.000 claims description 45
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000002360 preparation method Methods 0.000 abstract description 6
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 17
- 238000005538 encapsulation Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000206 moulding compound Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
Abstract
The present invention provides a kind of package structure of semiconductor device and method for packing, wherein, which includes：Chipset；The chipset is arranged in encapsulated layer, and the chipset includes the multiple chips that connect in vertical direction, and the lead of each chips in the multiple chips is respectively positioned on the side wall of the chipset, and the side wall is exposed to outside the encapsulated layer.The lead of each chips in chipset is connected on the side wall of chipset from pad, lead is interconnected from side wall afterwards, reduce chip chamber circuit spacing, so that signal transmission is quicker, a variety of TSV double-side technologies are avoided, this semiconductor device reliability is high, package dimension is small, overall performance is good, and preparation process is simple, and production efficiency is high.
Description
Technical field
The present invention relates to wafer level packaging field, and in particular to a kind of package structure of semiconductor device and method for packing.
Background technology
At present, recombinating wafer method includes the semiconductor chip of well cutting being placed on being disposed on frame (frame)
Opening (opening) in, form restructuring wafer by the way that moulding compound (mold compound) is filled into opening, mold
Material is formed on chip circumference, the small pieces (finished die) of completion is formed in restructuring wafer, by the small pieces and frame of completion
Frame separates.
Chip-stacked is that two or more chips is stacked in the Z-direction, and the interconnection mode between chip is usually to draw
Line bonding (Wire Bonding, be abbreviated as WB), upside-down mounting (Flip Chip, be abbreviated as FC) and silicon hole (Through
Silicon Via, are abbreviated as TSV).
Stacked relative to being assembled after single-chip package, various chips heap poststack is recombinated into wafer level packaging, it is few with flow, into
The advantages of this is low, and encapsulation volume is small, but since technological process needed for the interconnection between multi-chip is more complicated, cost is higher so that
The restructuring wafer packaging structure complex manufacturing technology of multi-chip stacking, production cost are high.
The content of the invention
Therefore, the technical problem to be solved in the present invention is to overcome the restructuring wafer of multi-chip stacking of the prior art to seal
Assembling structure complex manufacturing technology, the defects of production cost is high.
For this reason, the present invention provides following technical solution：
The present invention provides a kind of package structure of semiconductor device, including：Chipset；The chipset is arranged at encapsulated layer
Interior, the chipset includes the multiple chips connected in vertical direction, and each chips in the multiple chips draw
Line is respectively positioned on the side wall of the chipset, and the side wall is exposed to outside the encapsulated layer.
Alternatively, each chipset is by being vertically placed on multiple chipsets above slide glass cut
Arrive；Wherein, the side wall is connected with the slide glass.
Alternatively, the side wall that the multiple chips have lead is located at same level.
Alternatively, the upper surface of the encapsulated layer is concordant with the upper surface of the chipset.
Alternatively, further include：Layer is rerouted, is arranged on the side wall and the encapsulated layer, with drawing on the side wall
Line connects；Salient point, is arranged on the rewiring layer, is connected with the rewiring layer.
The present invention also provides a kind of semiconductor packages method, it is characterised in that includes the following steps：Above slide glass
Place one or more chipset vertically, the chipset includes the multiple chips connected in vertical direction, described more
The lead of each chips in chip is led on the side wall of the chipset, and the side wall is connected with the slide glass；
It is packaged on the slide glass, forms encapsulated layer；Remove the slide glass.
Alternatively, before described the step of placing one or more chipset vertically above slide glass, further include：To be more
The lead of each chips in chips leads to side wall；The multiple chips are subjected to vertical direction connection, form chip
Group, the lead of each chips in the chipset are respectively positioned on the side wall of the chipset.
Alternatively, before described the step of placing one or more chipset vertically above slide glass, further include：Institute
State and adhesive layer is formed on slide glass.
Alternatively, after the step of removing the slide glass, further include：Weight cloth is prepared on the side wall and the encapsulated layer
Line layer and salient point, the rewiring layer are connected with the lead on the side wall, are also connected with the salient point.
Alternatively, after the step of removing the slide glass, further include：The encapsulated layer is cut, is formed multiple only
Vertical package structure of semiconductor device.
The present invention also provides a kind of package structure of semiconductor device, the package structure of semiconductor device uses any of the above-described
Method for packing is prepared.
Technical solution of the present invention, has the following advantages that：
1. package structure of semiconductor device provided by the invention, including：Chipset；The chipset is arranged in encapsulated layer
, the chipset includes the multiple chips that connect in vertical direction, the lead of each chips in the multiple chips
It is respectively positioned on the side wall of the chipset, the side wall is exposed to outside the encapsulated layer.Each chips in chipset draw
Line is connected on the side wall of chipset from pad, is afterwards interconnected lead from side wall, is reduced between chip chamber circuit
Away from so that signal transmission is quicker, avoids a variety of TSV double-side technologies so that technological process is few, processing procedure difficult point is few, production
Cost is low.This semiconductor device reliability is high, and package dimension is small, and overall performance is good, and preparation process is simple, production efficiency
It is high.
2. semiconductor packages method provided by the invention, includes the following steps：It is vertical above slide glass to place one
It is each in the multiple chips or multiple chipsets, the chipset include the multiple chips that connect in vertical direction
The lead of chips is led on the side wall of the chipset, and the side wall is connected with the slide glass；It is enterprising in the slide glass
Row encapsulation, forms encapsulated layer；Remove the slide glass.The pad for the chip for needing to encapsulate is led to side by the method for packing by lead
Wall, carries out multi-chip connection in vertical direction afterwards, forms chipset, chipset is vertically placed on slide glass and is sealed
Dress, removes slide glass, this method for packing reduces chip chamber circuit spacing after encapsulation so that signal transmission is quicker, avoids
A variety of TSV double-side technologies so that technological process is few, processing procedure difficult point is few, production cost is low, and the utilization rate of slide glass is high.
Brief description of the drawings
, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution of the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in describing below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
Put, other attached drawings can also be obtained according to these attached drawings.
Fig. 1 is the structure chart of a specific example of package structure of semiconductor device in the embodiment of the present invention 1；
Fig. 2 is the structure chart of another specific example of package structure of semiconductor device in the embodiment of the present invention 1；
Fig. 3 is the flow chart of a specific example of semiconductor packages method in the embodiment of the present invention 2；
Fig. 4 is the flow chart of another specific example of semiconductor packages method in the embodiment of the present invention 2；
Fig. 5-Figure 18 is the schematic diagram of the specific steps of semiconductor packages method in the embodiment of the present invention 2.
Reference numeral：
The first wafers of 01-；The first chips of 1-；The first pads of 11-；The first grooves of 12-；The second chips of 2-；21- second is welded
Disk；The 3rd chips of 3-；The 3rd pads of 31-；The first leads of 41-；The second leads of 42-；The 3rd leads of 43-；The first bonded layers of 012-；
The second bonded layers of 023-；5- chipsets；6- slide glasses；7- adhesive layers；8- encapsulated layers；9- reroutes layer；10- salient points.
Embodiment
Technical scheme is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's all other embodiments obtained without making creative work, belong to the scope of protection of the invention.
In the description of the present invention, it is necessary to explanation, term " " center ", " on ", " under ", "left", "right", " vertical ",
The orientation or position relationship of the instruction such as " level ", " interior ", " outer " be based on orientation shown in the drawings or position relationship, merely to
Easy to describe the present invention and simplify description, rather than instruction or imply signified device or element must have specific orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" the 3rd " is only used for description purpose, and it is not intended that instruction or hint relative importance.
In the description of the present invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or be electrically connected；It can be directly connected, can also be indirectly connected by intermediary, can be with
It is the connection inside two elements, can is wireless connection or wired connection.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As long as in addition, technical characteristic involved in invention described below different embodiments non-structure each other
It can be combined with each other into conflict.
Embodiment 1
The present embodiment provides a kind of package structure of semiconductor device, as shown in Figure 1, including：Chipset 5, chipset 5 are set
In in encapsulated layer 8, chipset 5 includes the multiple chips connected in vertical direction, each chips in multiple chips
Lead is respectively positioned on the side wall of chipset 5, and side wall is exposed to outside encapsulated layer 8；Layer 9 is rerouted, is arranged at side wall and encapsulated layer 8
On, it is connected with the lead on side wall；Salient point 10, is arranged at and reroutes on layer 9, is connected with rerouting layer 9.Each chipset 5 is
By what is cut to being vertically placed on multiple chipsets above slide glass, wherein, side wall is connected with slide glass.At this
In embodiment, chipset 5 includes a chipset, as shown in Figure 1；Certainly, in other embodiments, chipset 5 can also wrap
Multiple chipsets are included, such as two chipsets, as shown in Fig. 2, rationally setting as needed.
In the present embodiment, chipset 5 includes the first chip 1, the second chip 2, the 3rd chip 3 and for by the first core
The first bonded layer 012 that 1 and second chip 2 of piece is attached, for the second chip 2 and the 3rd chip 3 are attached
Two bonded layers 023, the lead of the first chip 1, the second chip 2 and the 3rd chip 3 are respectively positioned on the side wall of chipset 5；Certainly, exist
In other embodiments, the chip number that chipset 5 is included can also be two, four or even more, as needed rationally
Setting.In the present embodiment, three chips are different chips, certainly, in other embodiments, or identical
Chip, is rationally set as needed.
In the present embodiment, the side wall that the first chip 1, the second chip 2 and the 3rd chip 3 have lead is located at same water
Plane, the upper surface of encapsulated layer 8 is concordant with the upper surface of chipset 5, certainly, in other embodiments, the side wall of different chips
Can be located at different horizontal planes, the upper surface of encapsulated layer may be set to be with the upper surface of chipset it is not concordant, according to need
Rationally to set.
Above-mentioned semiconductor device encapsulating structure have package dimension is small, reliability is high, overall performance is good, it is simple to prepare and
The advantages of production cost is low.
Embodiment 2
The present embodiment provides a kind of semiconductor packages method, flow chart are as shown in Figure 3；One as the present embodiment
Preferred solution, flow chart is as shown in figure 4, include the following steps：
S1：The lead of each chips in multiple chips is led into side wall.In the present embodiment, multiple chips three
, the first chip 1, the second chip 2 and the 3rd chip 3 are followed successively by, the first chip 1 is cut by the first wafer 01 and formed, the second core
Piece 2 is formed by the cutting of the second wafer, and the 3rd chip 3 is formed by the cutting of the 3rd wafer；Certainly, in other embodiments, chip
Number can also be two, four or even more, rationally set as needed.In the present embodiment, three chips are
Different chips, certainly, in other embodiments, or identical chip, is rationally set as needed.
Illustrated so that the cutting of the first wafer 01 obtains the first chip 1 as an example, some first cores are included on the first wafer 01
Piece 1, as shown in Figure 5；First pad 11 of each the first chip 1 is led to the side wall of the first chip 1 by the first lead 41
On, concretely comprise the following steps, the first groove 12 first prepared on the first wafer 01, as shown in fig. 6, afterwards in the first groove 12 and
The surface filling conductive material of first chip 1, the first pad 11 is connected by conductive material with conductive material, conductive material formation the
One lead 41, as shown in fig. 7, then being cut to the first wafer 01, obtains some first chips 1, the side wall of the first chip 1
Expose the first lead 41, as shown in Figure 8.In the present embodiment, the first chip 1 includes first pad 11, the first pad 11
It is consistent with the number of the first groove 12, first groove 12 is prepared, the depth of the first groove 12 is less than the thickness of the first wafer 01
Degree, certainly, in other embodiments, the number of the first pad 11, the number of the first groove 12, the shape of the first groove 12 and
First groove, 12 depth office can rationally be set as needed.The preparation process of second chip 2 and the 3rd chip 3 and the first chip 1
Preparation process it is similar, details are not described herein, and the structure diagram of the second chip 2 is as shown in figure 9, including the second pad 21 and
Two leads 42；The structure diagram of 3rd chip 3 is as shown in Figure 10, including the 3rd pad 31 and the 3rd lead 43.
S2：Multiple chips are subjected to vertical direction connection, form chipset, the lead of each chips in chipset is equal
On the side wall of chipset.In the present embodiment, as shown in figure 11, the first chip 1 and the second chip 2 pass through the first bonded layer
012 connection, the second chip 2 and the 3rd chip 3 are connected by the second bonded layer 023, the first chip 1, the second chip 2 and the 3rd core
There is piece 3 side wall of lead to be located at same level, form chipset 5；Certainly, in other embodiments, the side of different chips
Wall can not also be located at same level, as shown in figure 12, rationally set as needed.
S3：In order to chipset be positioned on slide glass operation it is more convenient and place after chipset and slide glass between
Fixation is more firm, and adhesive layer 7 is formed on slide glass 6, as shown in figure 13, certainly, in other embodiments, can not also be formed
Adhesive layer 7, is rationally set as needed.
S4：Place one or more chipset 5 vertically above slide glass 6, chipset 5 includes connecting in vertical direction
Multiple chips, the lead of each chips of multiple chips led on the side wall of chipset 5, and side wall is connected with slide glass 6.
In the present embodiment, as shown in figure 14, two chipsets 5, the tool of chipset 5 are placed on the adhesive layer 7 above slide glass 6 vertically
Leaded side wall is connected with slide glass 6；Certainly, in other embodiments, the number of chipset 5 can also be one, three very
To more, the spacing between specific number and the thickness of chipset 5, the size of slide glass 6 and adjacent chips group 5 is related, root
Rationally set according to needs.
S5：It is packaged on slide glass 6, forms encapsulated layer 8, as shown in figure 15, the thickness of encapsulated layer 8 is reasonable as needed
Setting.
S6：Slide glass 6 is removed, exposes the lead on side wall, as shown in figure 16.
S7：Prepared on side wall and encapsulated layer and reroute layer 9 and salient point 10, rerouted layer 9 and be connected with the lead on side wall,
Also it is connected with salient point 10, as shown in figure 17.
S8：Encapsulated layer 8 is cut, forms multiple independent package structure of semiconductor device, single semiconductor devices
Encapsulating structure is as shown in figure 18.
Above-mentioned restructuring wafer packaging method, it would be desirable to which the pad of the chip of encapsulation leads to side wall by lead, is hanging down afterwards
Nogata carries out multi-chip connection upwards, forms chipset, chipset is vertically placed on slide glass and is packaged, is removed after encapsulation
Slide glass, and preparation reroutes layer on the side wall with lead and salient point, this method for packing reduce chip chamber circuit spacing,
So that signal transmission is quicker, a variety of TSV double-side technologies are avoided, technological process is few, processing procedure difficult point is few, production cost is low,
And the utilization rate of slide glass is high.
In addition, also providing a kind of package structure of semiconductor device in the present embodiment, it is prepared using above-mentioned method for packing,
The semiconductor devices prepared by above-mentioned method for packing, reliability is high, and package dimension is small, and overall performance is good, and preparation process
Simply, production efficiency is high.
Obviously, the above embodiments are merely examples for clarifying the description, and the restriction not to embodiment.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of change or
Change.There is no necessity and possibility to exhaust all the enbodiments.And the obvious change thus extended out or
Among changing still in the protection domain of the invention.
Claims (10)
- A kind of 1. package structure of semiconductor device, it is characterised in that including：Chipset；The chipset is arranged in encapsulated layer, and the chipset includes the more cores connected in vertical direction Piece, the lead of each chips in the multiple chips are respectively positioned on the side wall of the chipset, and the side wall is exposed to institute State outside encapsulated layer.
- 2. package structure of semiconductor device according to claim 1, it is characterised in that each chipset is by right It is vertically placed on what multiple chipsets above slide glass were cut；Wherein, the side wall is connected with the slide glass.
- 3. package structure of semiconductor device according to claim 1, it is characterised in that the multiple chips have lead Side wall is located at same level.
- 4. package structure of semiconductor device according to claim 1, it is characterised in that the upper surface of the encapsulated layer and institute The upper surface for stating chipset is concordant.
- 5. according to any package structure of semiconductor device of claim 1-4, it is characterised in that further include：Layer is rerouted, is arranged on the side wall and the encapsulated layer, is connected with the lead on the side wall；Salient point, is arranged on the rewiring layer, is connected with the rewiring layer.
- A kind of 6. semiconductor packages method, it is characterised in that include the following steps：Place one or more chipset vertically above slide glass, the chipset includes more connected in vertical direction Chip, the lead of each chips in the multiple chips are led on the side wall of the chipset, the side wall with it is described Slide glass is connected；It is packaged on the slide glass, forms encapsulated layer；Remove the slide glass.
- 7. semiconductor packages method according to claim 6, it is characterised in that described to be placed vertically above slide glass Before the step of one or more chipset, further include：The lead of each chips in multiple chips is led into side wall；The multiple chips are subjected to vertical direction connection, form chipset, the lead of each chips in the chipset It is respectively positioned on the side wall of the chipset.
- 8. semiconductor packages method according to claim 6, it is characterised in that described to be placed vertically above slide glass Before the step of one or more chipset, further include：Adhesive layer is formed on the slide glass.
- 9. semiconductor packages method according to claim 6, it is characterised in that the step of removing the slide glass it Afterwards, further include：Prepared on the side wall and the encapsulated layer and reroute layer and salient point, it is described to reroute layer and the lead on the side wall Connection, is also connected with the salient point.
- 10. according to any semiconductor packages methods of claim 6-9, it is characterised in that remove the slide glass After step, further include：The encapsulated layer is cut, forms multiple independent package structure of semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711224791.6A CN108010906A (en) | 2017-11-29 | 2017-11-29 | A kind of package structure of semiconductor device and method for packing |
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| CN110010494A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of system in package interconnection architecture production method of the side wall with pad |
| CN110010495A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of high density side wall interconnected method |
| CN110993518A (en) * | 2019-12-19 | 2020-04-10 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
| CN111863792A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| WO2022037754A1 (en) * | 2020-08-17 | 2022-02-24 | Huawei Technologies Co., Ltd. | A method for manufacturing a die assembly |
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| CN110010494A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of system in package interconnection architecture production method of the side wall with pad |
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| WO2022037754A1 (en) * | 2020-08-17 | 2022-02-24 | Huawei Technologies Co., Ltd. | A method for manufacturing a die assembly |
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Application publication date: 20180508 |