CN107994071A - A kind of hetero-junctions channel insulation grid-type field-effect tube - Google Patents
A kind of hetero-junctions channel insulation grid-type field-effect tube Download PDFInfo
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- 238000009413 insulation Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 193
- 210000000746 body region Anatomy 0.000 claims abstract description 29
- 239000002210 silicon-based material Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 27
- 239000004020 conductor Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 3
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 claims 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 15
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- 239000000377 silicon dioxide Substances 0.000 abstract description 12
- 229910018540 Si C Inorganic materials 0.000 abstract description 11
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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Abstract
The invention discloses a kind of hetero-junctions channel insulation grid-type field-effect tube, belong to semiconductor power device technology field.The present invention using silicon materials by the channel body region of traditional Si C UMOS devices and source region by replacing hetero-junctions UMOS devices, utilize the low energy gap of interfacial state and silicon materials good between silicon and silica, while ensureing reversely pressure-resistant, reduce conducting resistance, improve forward current, and in additional grid voltage channel MOS capacitance is reduced rapidly, after grid voltage reaches threshold voltage, reverse transfer capacitance reduces, so as to be improved the switching speed of device, the switching loss of device is reduced.And by rationally setting protection zone and JFET areas; solve the problems, such as since SiC and Si interface potential barriers damage device forward conduction performance and since voltage endurance is insufficient caused by trench gate structure bottom electric field concentration effect, gate oxide stability difference and the low energy gap of silicon the problem of so that device has good reverse voltage endurance capability.
Description
Technical field
The invention belongs to semiconductor power device technology field, more particularly to a kind of hetero-junctions channel insulation grid-type field-effect
Pipe.
Background technology
Semiconductor material with wide forbidden band carborundum (SiC) is the ideal material for preparing high voltage electric and electronic device, compared to silicon
Material, SiC material have breakdown field strength height (4 × 106V/cm), carrier saturation drift velocity height (2 × 107Cm/s it is), hot
The advantages that conductance height and good heat endurance, therefore particularly suitable for making high-power, high pressure, high temperature and radiation-resistant electronics device
Part.The U-type groove grid-type field-effect transistor (SiC UMOS) made of SiC material is the best power of current development prospect
One of MOS device, relative to other two kinds of representative vertical power MOS (Metal Oxide Semiconductor) devices --- VVMOS and VDMOS, UMOS solve VVMOS
V-groove corrosion present in device is difficult to, and gate oxide exposure, threshold voltage is unstable, the not high problems of reliability；At the same time
JFET effects existing for VDMOS are it also avoid, therefore compares both VVMOS, VDMOS and possesses relatively low ON resistance and lower
Power consumption penalty；Further, since UMOS has less cellular size, therefore it is advantageously implemented the gully density of higher.
However, one problem of SiC MOS devices generally existing, i.e. carrier channels mobility are very low.The root of this problem
This reason is：SiC/SiO2The high interfacial state at interface.For SiC MOS devices, the high interfacial state capture electric charge meeting at raceway groove
A large amount of scattering centers are formed, the transmission of the carrier in raceway groove are upset, so as to substantially reduce the average drift of inversion layer carrier
Speed and mobility.On the one hand, since in the case where ignoring the ohmic contact resistance of electrode, the forward conduction of UMOS devices is electric
Resistance is mainly that drift zone resistance adds channel resistance, because channel electron mobility causes raceway groove well below body mobility
Resistance is far longer than drift zone resistance, therefore channel electron mobility is to influence the main factor of conducting resistance.By low raceway groove
The problem of device on-resistance is excessive caused by carrier mobility, has become the maximum that SiC MOS devices are faced and asks
Topic, and the technical problem that those skilled in the art are urgently to be resolved hurrily.On the other hand, high interfacial state and broad stopband width can also be brought
The problem of channel capacitance is larger, and then cause the switching speed of device slack-off, loss increase.
The content of the invention
In view of the deficiency present in the prior art, goal of the invention of the invention is：Moved for SiC MOS device carriers
The problems such as shifting rate is low and channel capacitance is larger, it is proposed that a kind of hetero-junctions channel insulation grid-type field-effect tube, by by traditional Si C
The channel body region of UMOS devices is replaced with source region using silicon materials, utilizes interfacial state and silicon good between silicon and silica
The low energy gap width of material, achievees the purpose that to increase device forward current, reduce reverse transfer capacitance and reduce switching loss.
The present invention is as follows for the used technical solution that solves the above problems：A kind of hetero-junctions channel insulation grid-type field-effect
Pipe, including：First conductive type semiconductor drain ohmic contact area 8, its front and back are equipped with the first conduction type half successively
Conductor drift region 7 and drain electrode 9, the top central of the first conductive type semiconductor drift region 7 has to be set along device vertical direction
The groove put, is equipped with gate electrode 1 in groove, is equipped with gate oxide 2 between gate electrode 1 and trench wall, and the first of groove both sides
The top layer of conductive type semiconductor drift region 7 is respectively equipped with the second conductive type semiconductor raceway groove being in contact with gate oxide 2
Body area 6, the top layer of the second conductive type semiconductor channel body region 6 are equipped with the first conduction type half being in contact with gate oxide 2
Conductor source region 3, the first conductive type semiconductor source region 3 and the second conductive type semiconductor channel body region 6 with the side of being provided thereon
4 equipotential of source electrode；It is characterized in that：First conductive type semiconductor source region 3 and the second conductive type semiconductor channel body
The material in area 6 is silicon materials, the first conductive type semiconductor drift region 7 and the first conductive type semiconductor drain ohmic contact area
8 material is carborundum.
It is further to be led in the present invention between the second conductive type semiconductor channel body region 6 and source electrode 4 by second
Electric type semiconductor source electrode ohmic contact regions 5, which are connected, realizes equipotential.
It is further, in order to avoid the electric field in 2 and second conductive type semiconductor channel body region of gate oxide, 6 raceway groove
Excessive, the present invention is provided with the second conductive type semiconductor protection zone 10 to electricity in the first conductive type semiconductor drift region 7
Field is shielded, and the second conductive type semiconductor protection zone 10 is located at below channel bottom.
It is further, in order to avoid the second conductive type semiconductor protection zone 10 and the first conductive type semiconductor drift about
The potential barrier sector width that area 7 forms PN junction is excessive so as to form JEFT effects, and the present invention drifts about in the first conductive type semiconductor
The first conductive type semiconductor JFET areas 11 being in contact with the second conductive type semiconductor protection zone 10 are provided with area 7 with guarantor
Device forward characteristic is demonstrate,proved, specifically, the doping concentration in the first conductive type semiconductor JFET areas 11 is more than the first conduction type half
The doping concentration of conductor drift region 7；The first conductive type semiconductor JFET areas 11 are located at the second conductive type semiconductor guarantor
Protect between the top and/or the second conductive type semiconductor protection zone 10 in area 10.
Specifically, the first conductive type semiconductor is N-type semiconductor in the present invention, and the second conductive type semiconductor is p-type
The first conductive type semiconductor is P-type semiconductor in semiconductor or the present invention, and the second conductive type semiconductor is partly led for N-type
Body.
It is preferred that the doping concentration of P-type semiconductor channel body region 6 is 1 × 10 in the present invention17cm-3, N-type partly leads
Body drift region 7 is 4 × 1015cm-3。
It is preferred that 10 thickness of P-type semiconductor protection zone is 1.5 μm in the present invention, doping concentration is 1 × 1018cm-3；
It is preferred that the second conductive type semiconductor protection zone 10 is groove-like so that source electrode 4 extends into
In two conductive type semiconductor protection zones 10, the width of source electrode 4 is 0.6 μm, it gos deep into the depth of P-type semiconductor protection zone 10
For 1.2 μm.
It is preferred that the thickness in N-type semiconductor JFET areas 11 is 1.5 μm, doping concentration is 2 × 1016cm-3。
Technical solution of the present invention is in order to solve existing SiC UMOS devices since gate oxide and the second conduction type are partly led
The too low caused device on-resistance of carrier mobility in the channel inversion layer at contact interface between bulk channel body area 6
This excessive problem, forming interface using silicon materials and gate oxide material, that is, silica has good interface characteristic, raceway groove
The bed boundary density of states is very low, therefore the carrier mobility of raceway groove is half of silicon materials body mobility or so, far above existing
The carrier mobility of carborundum and silicon dioxide interface under technique, so as to effectively reduce conducting resistance, and then increases device
The forward current of part；Furthermore since silicon materials energy gap is small so that the channel carrier density under equal grid voltage carries significantly
Height, while reduce rapidly in additional grid voltage effect lower channel mos capacitance so that after grid voltage reaches threshold voltage, reverse transfer electricity
Hold and reduce, so as to obtain more preferable switching characteristic；In addition, accumulation layer is formed in carborundum side using additional grid voltage, can be with
Drop, so that the electronic barrier that both electron affinity different materials of silicon and carborundum are formed at interface narrows, leads to
Carrier (electronics or hole) is crossed under the action of quantum tunneling effect by above-mentioned electronic barrier, and then is avoided to device just
Harmful effect is brought to characteristic.
Compared with prior art, the beneficial effects of the invention are as follows：
The hetero-junctions UMOS devices that SiC provided by the invention is formed with Si both materials, ensure it is reversely pressure-resistant same
When, conducting resistance is reduced, improves forward current, and in additional grid voltage channel MOS capacitance is reduced rapidly, grid voltage reaches
To after threshold voltage, reverse transfer capacitance reduces, so as to be improved the switching speed of device, reduces the switch damage of device
Consumption.
Brief description of the drawings
Fig. 1 is the structure diagram of the U-shaped channel insulation grid-type field-effect tube of traditional Si C (referred to as SiC UMOS).
Fig. 2 is that the U-shaped channel insulation grid-type field-effect tube of SiC/Si hetero-junctions that the embodiment of the present invention 1 provides (is referred to as
SiC/Si UMOS) structure diagram.
Fig. 3 is the structural representation for the U-shaped channel insulation grid-type field-effect tube of SiC/Si hetero-junctions that the embodiment of the present invention 2 provides
Figure.
Fig. 4 is the structural representation for the U-shaped channel insulation grid-type field-effect tube of SiC/Si hetero-junctions that the embodiment of the present invention 3 provides
Figure.
Fig. 5 is the reverse pressure-resistant contrast for the SiC/Si UMOS that traditional Si C UMOS structures are provided with the embodiment of the present invention 3
Figure.
Fig. 6 is the forward conduction resistance pair for the SiC/Si UMOS that traditional SIC UMOS structures are provided with the embodiment of the present invention 3
Than figure.
Fig. 7 is the band structure and tunneling effect schematic diagram at the heterojunction boundary of SiC/Si UMOS provided by the invention.
Fig. 8 is that (position is with x coordinate as schemed for the conduction band contrast of heterojunction boundary not plus in the case of grid voltage and additional positive grid voltage
In 2 shown in arrow).
The mobility distribution that Fig. 9 is the SiC/Si UMOS that traditional Si C UMOS structures are provided with the embodiment of the present invention 3 contrasts
Figure.
Figure 10 is the SiC/Si UMOS that the embodiment of the present invention 3 provides and does not use the DTMOS structures of SiC/Si hetero-junctions
Switch comparison diagram.
Figure 11 is to increase P-type semiconductor protection zone, Electric Field Simulation result figure when reverse drain voltage is 1200V.
Figure 12 is that reverse breakdown is special in the case of not increasing P-type semiconductor protection zone and increasing by two kinds of P-type semiconductor protection zone
The comparison diagram of property.
Figure 13 is not increase N-type JFET areas and the comparison diagram of forward conduction resistance in the case of increase N-type JFET areas.
Embodiment
The principle and characteristic of the technical program are further illustrated with reference to the embodiment of the present invention and Figure of description, with
Help understand the technique effect of technical problem, technological means used and acquirement that present inventive concept is solved：
By taking N-channel UMOS devices as an example, those skilled in the art pass through examples provided below on this basis
Simple replacement can draw the operation principle and performance of P-channel UMOS devices, and details are not described herein by the present invention.
Embodiment 1：
A kind of hetero-junctions channel insulation grid-type field-effect tube provided in this embodiment is illustrated in figure 2, including：First is conductive
Type semiconductor drain ohmic contact area 8, its front and back are equipped with the first conductive type semiconductor drift region 7 and electric leakage successively
Pole 9, the top central of the first conductive type semiconductor drift region 7 have the groove set along device vertical direction, are set in groove
There is gate electrode 1, gate oxide 2, the first conductive type semiconductor drift of groove both sides are equipped between gate electrode 1 and trench wall
The top layer in area 7 is respectively equipped with the second conductive type semiconductor channel body region 6 being in contact with gate oxide 2, the second conduction type
The top layer in semiconductor channel body area 6 is equipped with the first conductive type semiconductor source region 3 being in contact with gate oxide 2 and is led with first
The second conduction type source electrode ohmic contact regions 5 that electric type semiconductor source region 3 is in contact, the first conductive type semiconductor source region 3
It is connected with the top of the second conduction type source electrode ohmic contact regions 5 with source electrode 4；It is characterized in that：First conduction type is partly led
The material of 3 and second conductive type semiconductor channel body region 6 of body source region is silicon materials, the first conductive type semiconductor drift region 7
Material with the first conductive type semiconductor drain ohmic contact area 8 is carborundum.
The first conductive type semiconductor is N-type semiconductor in the present embodiment, and the second conductive type semiconductor is partly led for p-type
Body.
Idea of the invention is according to above technical scheme：By the SiC/SiO of traditional Si C MOS devices2Replace
Into Si/SiO2Raceway groove, to reduce the forward conduction resistance of device, it is known to those skilled in the art that：Reduce UMOS devices
Conducting resistance must just increase raceway groove at the contact interface of 2 and first conductive type semiconductor channel body region 6 of gate oxide
The mobility of carrier in inversion layer, and the principal element for influencing Inversion Layer Carrier Mobility at present is rooted in SiC and SiO2
High interfacial state at contact interface, this interfacial state are limited to existing process level, under existing process level, SiC and SiO2Connect
The carrier mobility of tactile interface is very low, and the heterojunction structure that the present invention is formed using Si/SiC, by UMOS devices
The first conductive type semiconductor source region 3 and the second conductive type semiconductor channel body region 6 use Si materials, so as to avoid
The high interfacial state problem of SiC channel layers, the channel carrier mobility of device can reach half of body mobility or so, with regard to N
For raceway groove UMOS devices, compared to Si and SiO2Electron mobility at contact interface, SiC and SiO2Electronics at contact interface moves
Shifting rate highest be also only capable of reaching its 1/10th or so；And the Si materials of low energy gap are as raceway groove, it is possible to increase ditch
Road inversion carriers density, therefore, the conducting resistance of Si/SiC hetero-junctions UMOS devices are far below traditional SiC UMOS.This
Outside, the low energy gap and interface state of Si materials so that channel MOS capacitance reduces rapidly under the action of additional grid voltage, when
After grid voltage reaches threshold voltage, reverse transfer capacitance is obviously reduced, so as to obtain more preferable switching characteristic.
However, while improving to reach carrier mobility using Si and SiC heterojunction structures, there is also some problems
Need to solve, to take into account the lifting of forward and reverse performance, particular problem is as follows：
Problem one：Since SiC and Si interface potential barriers have a negative impact device forward conduction；
Problem two：The gate oxide of trench gate bottom punctures in advance and the second conductive type semiconductor channel body region carries
Preceding breakdown.
In view of above-mentioned two problems, the present invention proposes the technical solution as disclosed in embodiment 2 and embodiment 3.
Embodiment 2：
A kind of hetero-junctions channel insulation grid-type field-effect tube provided in this embodiment is illustrated in figure 3, including：First is conductive
Type semiconductor drain ohmic contact area 8, its front and back are equipped with the first conductive type semiconductor drift region 7 and electric leakage successively
Pole 9, the top central of the first conductive type semiconductor drift region 7 have the groove set along device vertical direction, are set in groove
There is gate electrode 1, gate oxide 2, the first conductive type semiconductor drift of groove both sides are equipped between gate electrode 1 and trench wall
The top layer in area 7 is respectively equipped with the second conductive type semiconductor channel body region 6 being in contact with gate oxide 2, the second conduction type
The top layer in semiconductor channel body area 6 is equipped with the first conductive type semiconductor source region 3 being in contact with gate oxide 2 and is led with first
The second conduction type source electrode ohmic contact regions 5 that electric type semiconductor source region 3 is in contact, the first conductive type semiconductor source region 3
It is connected with the top of the second conduction type source electrode ohmic contact regions 5 with source electrode 4；It is characterized in that：First conduction type is partly led
Also there is the second conductive type semiconductor protection zone 10 for realizing electric field shielding, second conduction type half in body drift region 7
Conductor protection zone 10 is located at the lower section at channel bottom both ends；Further, also set in the first conductive type semiconductor drift region 7
The first conductive type semiconductor JFET areas 11 for being in contact with the second conductive type semiconductor protection zone 10 have been put to ensure device
Forward characteristic, specifically, the doping concentration in the first conductive type semiconductor JFET areas 11 are floated more than the first conductive type semiconductor
The doping concentration in area 7 is moved, the first conductive type semiconductor JFET areas 11 are located at the second conductive type semiconductor protection zone 10
Top and/or the second conductive type semiconductor protection zone 10 between；First conductive type semiconductor source region 3 and the second conductive-type
The material in type semiconductor channel body area 6 is silicon materials, the first conductive type semiconductor drift region 7 and the first conductive type semiconductor
The material in drain ohmic contact area 8, the second conductive type semiconductor protection zone 10 and the first conductive type semiconductor JFET areas 11
For carborundum.
The first conductive type semiconductor is N-type semiconductor in the present embodiment, and the second conductive type semiconductor is partly led for p-type
Body；
The design of the present embodiment can solve the device caused by U-shaped trench gate structure and Si material properties and puncture in advance
The problem of, specifically, the situation that electric field is concentrated occurs in the 2 bottom sharp corner of gate oxide of U-shaped trench gate structure, so as to cause
Gate oxide 2 easily punctures in advance；And Si materials are since energy gap is relatively narrow, so the SiC of resistance to pressure ratio order of magnitude lower, thus
Two conductive type semiconductor channel body regions 6 also easily puncture in advance.The present invention is by the first conductive type semiconductor drift region 7
Increase by the second conductive type semiconductor protection zone 10, so that by most of electric field controls in the first conductive type semiconductor drift region
In 7：Second conductive type semiconductor protection zone 10 forms P+N knots with the first conductive type semiconductor drift region 7 below, outside
When adding backward voltage, P+N knots are reverse-biased, and the barrier region of P+N knots can undertake most reversed electric field, so as to substantially reduce grid oxygen
Change the electric field strength of layer 2 and second conductive type semiconductor channel body region 6, avoid this at two and puncture in advance, breakdown region is limited
Make in the first conductive type semiconductor drift region 7 below the second conductive type semiconductor protection zone 10, therefore this structure
Breakdown area is the barrier region of P+N knots, and depends primarily upon the concentration and thickness of the first conductive type semiconductor drift region 7
Degree；Meanwhile the P+N knots can form wider barrier region in N-type region domain, barrier region is wide to allow conductive channel to narrow very
To pinch off, forward current size is influenced, therefore, the present invention increases in the top of the second conductive type semiconductor protection zone 10, both sides
Add the first conductive type semiconductor JFET areas of a higher-doped, so the barrier region can be allowed to narrow, avoid the formation of JEFT
Effect, and then reduce its influence to forward current.
Embodiment 3：
A kind of hetero-junctions channel insulation grid-type field-effect tube provided in this embodiment is illustrated in figure 4, including：First is conductive
Type semiconductor drain ohmic contact area 8, its front and back are equipped with the first conductive type semiconductor drift region 7 and electric leakage successively
Pole 9, the top central of the first conductive type semiconductor drift region 7 have the groove set along device vertical direction, are set in groove
There is gate electrode 1, gate oxide 2, the first conductive type semiconductor drift of groove both sides are equipped between gate electrode 1 and trench wall
The top layer in area 7 is respectively equipped with the second conductive type semiconductor channel body region 6 being in contact with gate oxide 2, the second conduction type
The top layer in semiconductor channel body area 6 is equipped with the first conductive type semiconductor source region 3 being in contact with gate oxide 2, and first is conductive
3 and second conductive type semiconductor channel body region 6 of type semiconductor source region is connected with source electrode 4；It is characterized in that：The source
The lower section of electrode 4 and part the second conductive type semiconductor channel body region 6 is equipped with the second conductive type semiconductor protection zone 10, real
The second conductive type semiconductor protection zone 10 can be made as groove-like in border, so that source electrode 4 extends to the second conductive-type
In type semiconductor protection area 10；The lower section of gate oxide 2 is equipped with the first conductive type semiconductor JFET areas 11, and described first is conductive
Type semiconductor JFET areas 11 are between both sides the second conductive type semiconductor protection zone 10 and are attached thereto；First conductive-type
The material of type semiconductor source region 3 and the second conductive type semiconductor channel body region 6 is silicon materials, and the first conductive type semiconductor floats
It is conductive to move 7 and first conductive type semiconductor drain ohmic contact area 8 of area, the second conductive type semiconductor protection zone 10 and first
The material in type semiconductor JFET areas 11 is carborundum；
The first conductive type semiconductor is N-type semiconductor in the present embodiment, and the second conductive type semiconductor is partly led for p-type
Body.
The position of second conductive type semiconductor protection zone 10 and the second conductive type semiconductor protection zone 11, size and mix
Miscellaneous concentration can all influence the forward and reverse characteristic of Si/SiC UMOS devices, and the present embodiment is determined such as parameter by emulation：
Device widths are 4 μm, its thickness is 9 μm；
The depth of gate electrode 1 and its oxide layer 2 is 1 μm；
The width of N-type semiconductor source region 3 is 0.7 μm, its thickness is 0.2 μm, and the doping concentration of N-type semiconductor source region 3 is 1
×1020cm-3；
The width of P-type semiconductor channel body region 6 is 0.7 μm, its thickness is 0.6 μm, and P-type semiconductor channel body region 6 is mixed
Miscellaneous concentration is 1 × 1017cm-3。
P-type semiconductor protection zone 10 is located inside away from the drift region below channel region, and size is 0.7 μm of 1.5 μ m, doping
Concentration is 1 × 1018cm-3；
N-type semiconductor JFET areas thickness is that 1.5 μm of its doping concentrations are 2 × 1016cm-3；
When device is opened, the accumulation layer of formation in N-type semiconductor JFET areas 11, its longitudinal size is 0.2 μm.
The data and physical principle obtained below in conjunction with emulation, produce beneficial technique effect to the present embodiment and carry out in detail
Subdivision analysis：
(1), structure of the present invention can ensure the reverse resistance to pressure of traditional Si C UMOS, and Fig. 5 is the Si/ that emulation obtains
The reverse breakdown curve comparison figure of SiC UMOS structures and traditional Si C UMOS structures, it can thus be seen that breakdown voltage is close.Together
When, the present invention can also substantially reduce device on-resistance, and Fig. 6 is that the Si/SiC UMOS structures that emulation obtains are tied with tradition UMOS
The curve map that the ratio conducting resistance of structure changes with gate source voltage, it is 7V to 15V to take excursion, which is shown in Fig. 3
Carried out under the conditions of close breakdown voltage.Wherein, curve 31 is traditional Si C UMOS, and curve 32 is hetero-junctions UMOS, from figure
It can be seen that：The forward direction of two kinds of structures is more identical with the trend that gate source voltage changes than conducting resistance, is reduced with increase, and
The speed of reduction gradually slows down, and with the case of, the ratio conducting resistance of hetero-junctions UMOS is all significantly lower than traditional Si C UMOS.
In SiC MOS devices, the main factor for determining conducting electric current size is the height of carrier channels mobility,
And the reason for causing channel layer carrier mobility to drastically reduce is SiC/SiO2The high interfacial state of interface can bring a large amount of fall into
Trap, these traps can greatly influence the directed movement of carrier；As long as it therefore can solve the problems, such as the high interfacial state of channel layer, just
The conducting electric current of SiC UMOS can be greatly improved, reduces its conducting resistance.
It is noted herein that：As shown in fig. 7, in the second conductive type semiconductor channel body region 6 and the first conductive-type
Type semiconductor JFET areas 11 contact Si/SiC heterojunction boundaries at, due to two kinds of materials electron affinity, that is, conduction band energy not
Together, interface potential barrier can be formed, bending occurs in conduction band in interface, in Si sides the second conductive type semiconductor channel body region 6
It is curved under the conduction band of side, electron accumulation layer is formed, it is curved on 7 side conduction band of SiC sides drift region, so as to form being highly Δ Ec
Electronic barrier, which can hinder the movement of electronics, increase conducting resistance, substantially reduce the electron mobility of interface.
The present embodiment by rationally designing structure, using 2 and first conductive type semiconductor drift region 7 of gate oxide or
The region of first conductive type semiconductor JFET areas 11 contact can form the accumulation layer of heavy doping under grid voltage effect so that should
Region can be with declining, so as to form the band structure of similar Ohmic contact in heterojunction boundary, the width of potential barrier of heterogenous junction becomes
Very narrow, according to quantum tunneling effect, probability and barrier width that electronics passes through the potential barrier are the relation of high negative correlation, therefore
When barrier width is very narrow, electronics is easy to pass through the potential barrier, therefore in the positive unlatching of device, the potential barrier of heterogenous junction is to device
Forward characteristic be nearly free from infringement.It is illustrated in figure 8 that to provide having of obtaining of device structure simulation based on embodiment 3 additional
Positive grid voltage and without the hetero-junctions conduction band comparison diagram in the case of additional positive grid voltage, position and direction as shown in x arrows in Fig. 4,
The conduction band curve that wherein curve 91 obtains in the case of being additional positive grid voltage 15V, and curve 92 is then without additional grid voltage situation
Under obtain.As can be seen from the figure：In the case of without additional grid voltage, hetero-junctions conduction band structure is pN abnormal shape hetero-junctions, boundary
Face barrier width is wider, and carrier is difficult to by being tunneled through the interface；And after additional positive grid voltage, there occurs following two
Change：One is the channel inversion of Si sides, hetero-junctions becomes nN homotype hetero-junctions, and another is that SiC sides form accumulation
Layer so that conduction band declines, thus potential barrier of heterogenous junction width substantially reduces, and carrier is easily by being tunneled through the interface potential barrier.
Conducting resistance can be reduced based on technical measure, significantly improve the forward current of UMOS devices, such as Fig. 9 institutes
The mobility distribution comparison diagram for the SiC/Si UMOS that traditional Si C UMOS structures are provided with the embodiment of the present invention 3 is shown as, is additional
Obtained in the case of grid voltage 15V, it can be seen that be Si/SiC UMOS of the present invention channel mobility it is left in 660cm/V-s
The right side, and tradition UMOS is then very low, only 20cm/V-s or so, interface carrier mobility is about that the half of material bodies mobility is left
The right side, far above SiC/SiO2Interface carrier mobility.
(2), the present invention utilizes the low energy gap and interface state of Si materials so that channel MOS capacitance is in additional grid voltage
Under the action of reduce rapidly, after grid voltage reaches threshold voltage, reverse transfer capacitance is obviously reduced, so as to obtain preferably opening
Close characteristic.It is the switch of DTMOS structure of the DTMOS structures of SiC/Si matter knot of the present invention with not using hetero-junctions as shown in Figure 10
Comparison diagram, is not referred to except not using hetero-junctions but in 3 He of the first conductive type semiconductor source region using the DTMOS of hetero-junctions
Second conductive-type semiconductor channel body area 6 is the same as using the SiC material identical with remaining region, the doping concentration and ruler of regional
Very little structure all consistent with HDTMOS.Switching characteristic can also be optimized to a certain extent due to adding P-shield areas, so logical
Cross such can clearly find out effect of optimization of the heterojunction structure to switching characteristic to Bizet.Wherein：Scheme (a), (b), (c),
(d) it is respectively HDTMOS opening processes, turn off process, opening process, the turn off process of DTMOS, Grey curves are switching process
Middle drain-source voltage change procedure, black are leakage current change procedure.It can be seen that compared to tradition without heterojunction structure
DTMOS, the opening time of HDTMOS of the invention substantially reduce, and the turn-off time remains basically stable, and it is left that master switch loss reduces by 30%
It is right.
(3), the present invention forms the second conduction type half in the first conductive type semiconductor drift region 7 by ion implanting
10 and first conductive type semiconductor JFET areas 11 of conductor protection zone.The second conductive type semiconductor protection zone 10 with below
The P+N knots that N- areas are formed are reverse-biased under reverse drain voltage, there is very strong electric field in its barrier region, assume responsibility for most of drain electrode
Voltage, therefore the second conductive type semiconductor protection zone 10 plays the role of good electric field shielding, is as shown in figure 11 increase P
Type semiconductor protection area, Electric Field Simulation result figure when reverse drain voltage is 1200V, the increase of this structure cause gate oxidation
2 and second electric field in conductive type semiconductor channel body region 6 of layer greatly reduces, and prevents this from puncturing in advance at two, thus will breakdown
Area has been limited in inside SiC, thus the present invention possess with traditional Si C UMOS similar in voltage endurance capability.As shown in figure 12, curve
71 be without increase P-type semiconductor protection zone 10 when reverse breakdown curve, curve 72 be add P-type semiconductor protection zone 10
Reverse breakdown curve afterwards, it can be seen that when not adding P-type semiconductor protection zone 10, device just punctures in advance in 300V or so
, and device maintains the characteristic of SiC device high voltage after adding.But also can in-between during P-type semiconductor protection zone 10
P+N knots are formed with N- drift regions 7, and the barrier region of these P+N knots is mainly distributed on inside N-type semiconductor drift region 7, it is wide
Barrier region can form JFET effects, electronics flow path is narrowed even pinch off, and N-type semiconductor JFET areas 11 can be effective
Reduce P+N and tie the barrier width in N-type semiconductor drift region 7, so as to mitigate JFET effects, reduce P-type semiconductor protection zone
The infringement that 10 pairs of UMOS device forward characteristics are brought, improves the forward conduction electric current of UMOS devices, reduces forward conduction resistance, such as
Shown in Figure 13, curve 81 is to increase the curve changed behind N-type semiconductor JFET areas 11 than conducting resistance with gate source voltage in Fig. 8,
The curve that curve 82 changes when being no N-type semiconductor JFET areas 11 than conducting resistance with gate source voltage, it can be seen that the structure
UMOS device on-resistances can be effectively reduced, especially effect is more (when smaller than conducting resistance) when gate source voltage is larger
Add obvious.
Claims (7)
1. a kind of hetero-junctions channel insulation grid-type field-effect tube, including：First conductive type semiconductor drain ohmic contact area
(8), its front and back is equipped with the first conductive type semiconductor drift region (7) and drain electrode (9), the first conduction type half successively
The top central of conductor drift region (7) has the groove set along device vertical direction, and gate electrode (1), grid electricity are equipped with groove
Pole (1) is equipped with gate oxide (2), the top of the first conductive type semiconductor drift region (7) of groove both sides between trench wall
Layer is respectively equipped with the second conductive type semiconductor channel body region (6) being in contact with gate oxide (2), and the second conduction type is partly led
The top layer in bulk channel body area (6) is equipped with the first conductive type semiconductor source region (3) being in contact with gate oxide (2), and first leads
Electric type semiconductor source region (3) and the second conductive type semiconductor channel body region (6) with source electrode (4) equipotential；Its feature
It is：The material of first conductive type semiconductor source region (3) and the second conductive type semiconductor channel body region (6) is silicon materials,
The material in the first conductive type semiconductor drift region (7) and the first conductive type semiconductor drain ohmic contact area (8) is carbonization
Silicon.
A kind of 2. hetero-junctions channel insulation grid-type field-effect tube according to claim 1, it is characterised in that：Second conductive-type
It is connected between type semiconductor channel body area (6) and source electrode (4) by the second conductive type semiconductor source electrode ohmic contact regions (5)
Realize equipotential.
A kind of 3. hetero-junctions channel insulation grid-type field-effect tube according to claim 1, it is characterised in that：Described first leads
Also there is the second conductive type semiconductor protection zone (10), second conduction type half in electric type semiconductor drift region (7)
Conductor protection zone (10) is located at below channel bottom.
A kind of 4. hetero-junctions channel insulation grid-type field-effect tube according to claim 3, it is characterised in that：Described second leads
Electric type semiconductor protection zone (10) is connected with source electrode (4) and the second conductive type semiconductor channel body region (6), and second
Conductive type semiconductor channel body region (6) causes source electrode (4) to extend into it for groove-like.
A kind of 5. hetero-junctions channel insulation grid-type field-effect tube according to claim 3 or 4, it is characterised in that：Described
Also have be in contact with the second conductive type semiconductor protection zone (10) first to lead in one conductive type semiconductor drift region (7)
Electric type semiconductor JFET areas (11), the first conductive type semiconductor JFET areas (11) are located at the second conductive type semiconductor
Between the top of protection zone (10) and/or the second conductive type semiconductor protection zone (10).
A kind of 6. hetero-junctions channel insulation grid-type field-effect tube according to any one of claims 1 to 5, it is characterised in that：
First conductive type semiconductor is N-type semiconductor, and the second conductive type semiconductor is P-type semiconductor.
A kind of 7. hetero-junctions channel insulation grid-type field-effect tube according to any one of claims 1 to 5, it is characterised in that：
First conductive type semiconductor is P-type semiconductor, and the second conductive type semiconductor is N-type semiconductor.
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| WO2020258496A1 (en) * | 2019-06-27 | 2020-12-30 | 南京芯舟科技有限公司 | Cell structure and semiconductor device using same |
| CN113130627A (en) * | 2021-04-13 | 2021-07-16 | 电子科技大学 | Silicon carbide fin-shaped gate MOSFET integrated with channel diode |
| CN113270492A (en) * | 2021-05-13 | 2021-08-17 | 重庆邮电大学 | Trench type GaN insulated gate bipolar transistor |
| CN113471290A (en) * | 2021-06-18 | 2021-10-01 | 电子科技大学 | Tunneling-assisted conduction silicon/silicon carbide heterojunction MOSFET (Metal-oxide-semiconductor field Effect transistor) power device |
| CN114512539A (en) * | 2022-01-25 | 2022-05-17 | 电子科技大学 | Novel Si-SiC heterojunction tunneling MOSFET device and integrated device thereof |
| CN116504842A (en) * | 2023-06-28 | 2023-07-28 | 浙江大学 | Heterojunction insulated gate field effect transistor, manufacturing method thereof and semiconductor device |
| CN116825824A (en) * | 2023-08-29 | 2023-09-29 | 北京智芯微电子科技有限公司 | LDMOS device of silicon carbide and silicon heterojunction and manufacturing method |
| CN116895699A (en) * | 2023-09-08 | 2023-10-17 | 成都蓉矽半导体有限公司 | Cascade trench MOSFET with heterojunction and preparation method |
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| CN113270492A (en) * | 2021-05-13 | 2021-08-17 | 重庆邮电大学 | Trench type GaN insulated gate bipolar transistor |
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| CN116825824B (en) * | 2023-08-29 | 2023-12-15 | 北京智芯微电子科技有限公司 | LDMOS device of silicon carbide and silicon heterojunction and manufacturing method |
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