CN107993994A - Semiconductor package and its manufacture method - Google Patents
Semiconductor package and its manufacture method Download PDFInfo
- Publication number
- CN107993994A CN107993994A CN201711470750.5A CN201711470750A CN107993994A CN 107993994 A CN107993994 A CN 107993994A CN 201711470750 A CN201711470750 A CN 201711470750A CN 107993994 A CN107993994 A CN 107993994A
- Authority
- CN
- China
- Prior art keywords
- chip
- pad
- mounting surface
- cavity
- fan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 4
- 238000009434 installation Methods 0.000 claims description 4
- 239000003292 glue Substances 0.000 description 15
- 239000011521 glass Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 238000002161 passivation Methods 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 241000196324 Embryophyta Species 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229920002521 macromolecule Polymers 0.000 description 6
- 229920001296 polysiloxane Polymers 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910020776 SixNy Inorganic materials 0.000 description 4
- 229910020781 SixOy Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052593 corundum Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920000620 organic polymer Polymers 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- -1 polysiloxanes Polymers 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229920002379 silicone rubber Polymers 0.000 description 4
- 239000004945 silicone rubber Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 241000894007 species Species 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229920003051 synthetic elastomer Polymers 0.000 description 4
- 229920003002 synthetic resin Polymers 0.000 description 4
- 239000000057 synthetic resin Substances 0.000 description 4
- 239000005061 synthetic rubber Substances 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 description 4
- 208000002925 dental caries Diseases 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- FIPWRIJSWJWJAI-UHFFFAOYSA-N Butyl carbitol 6-propylpiperonyl ether Chemical compound C1=C(CCC)C(COCCOCCOCCCC)=CC2=C1OCO2 FIPWRIJSWJWJAI-UHFFFAOYSA-N 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 229920000297 Rayon Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000010426 asphalt Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000206 moulding compound Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 description 2
- 150000002830 nitrogen compounds Chemical class 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
This application involves field of semiconductor package, discloses a kind of semiconductor package and its manufacture method.The structure includes：The first chip and the second chip being arranged side by side, between form a gap side by side；Package, with the 3rd mounting surface and by the 3rd mounting surface recessed the first cavity and the second cavity, first chip is placed in the first cavity, second chip is placed in the second cavity, there is the first gap between first cavity and the first chip, there is the second gap between the second cavity and the second chip；Heat-conducting medium, is filled in the first gap and the second gap；Reroute layer, including the first fan-in pad, the second fan-in pad and external pad, first fan-in pad is engaged in the first contact and is connected to corresponding external pad via the first fan-out circuit, second fan-in pad is engaged in the second contact and is connected to corresponding external pad via the second fan-out circuit, reroute layer and further include interconnection line at least one, connect the first fan-in pad and the second fan-in pad.
Description
Technical field
This application involves field of semiconductor package, and in particular, to a kind of semiconductor package and its manufacture method.
Background technology
3 D stereo encapsulation (3D) is stacked on the direction perpendicular to chip surface, interconnects the envelope of two panels above crystal grain
Dress.Its space hold is small, electric performance stablity, is a kind of advanced system in package (SIP, System-In-Package) encapsulation
Technology.It is the system-level architecture based on wafer-level packaging that currently advanced 3D, which is integrated, and the lamination of a variety of devices is contained in inside, and passes through
It is connected with each other by silicon hole (Through Si Via, TSV) in vertical direction (Z-direction).In addition, in encapsulation technology, endeavour
Signal transmission distance and reduction shape factor (form between the soldered ball on the chip and substrate for shortening encapsulation
Factor), while also need to chip good heat radiating.
The content of the invention
The purpose of the application is to provide a kind of semiconductor package and its manufacture method, which has
More preferable heat dissipation effect.
To achieve these goals, in the one side of the application, there is provided a kind of semiconductor package, including：Side by side
Arrangement the first chip and the second chip, first chip have the first mounting surface and it is multiple be emerging in it is described first installation
First contact in face, second chip have the second mounting surface and multiple are emerging in the second of second mounting surface and connect
Point, forms a gap side by side between first chip and second chip；Package, has the 3rd mounting surface and by institute
State the 3rd mounting surface recessed the first cavity and the second cavity, the 3rd mounting surface is aligned in first mounting surface and described
Second mounting surface, first chip are placed in first cavity, and second chip is placed in second cavity,
There is the first gap between first cavity and first chip, have between second cavity and second chip
Second gap；Heat-conducting medium, is filled in first gap and second gap, and the heat-conducting medium has filling surface,
Connect first mounting surface, second mounting surface and the 3rd mounting surface so that first mounting surface, described second
Mounting surface and the 3rd mounting surface are formed in a continuous surface；Layer is rerouted, is formed on the continuous surface, the heavy cloth
Line layer includes the first fan-in pad, the second fan-in pad and external pad, and the first fan-in pad is engaged in described first and connects
Point is simultaneously connected to the corresponding external pad via the first fan-out circuit, and the second fan-in pad is engaged in described second and connects
Point is simultaneously connected to the corresponding external pad via the second fan-out circuit, and the rewiring layer further includes interconnection line at least one
Road, connects the first fan-in pad and the second fan-in pad.
Alternatively, the package also has passage, connects first cavity and second cavity, and the heat conduction is situated between
Matter is also filled in the passage.
Alternatively, semiconductor package may also include the first soldered ball, and plant is connected on the external pad.
Alternatively, semiconductor package may also include：Bearing substrate, has first surface and second surface, described to hold
Carried base board includes the interconnect pad positioned at the first surface, the terminal pad positioned at the second surface and is electrically connected institute
The circuit of interconnect pad and the terminal pad is stated, the interconnect pad is bonded with first soldered ball；And second soldered ball, plant
It is connected on the terminal pad.
Alternatively, the package also has the first opening connected with first cavity and connects with second cavity
The second logical opening, for inserting for the heat-conducting medium.
Alternatively, the shape of first opening or second opening may include in oval, circular, square, prismatic
Any one.
Alternatively, any one in first fan-out circuit, second fan-out circuit and the interior interconnection line
With line width/line-spacing less than 15 microns.
Alternatively, the material of the package can include silicon.
Alternatively, the package is formed by being performed etching to Silicon Wafer and singulation separating.
Alternatively, the width range in first gap and second gap is between 10 microns to 100 microns so that institute
State the first chip and second chip is not directly contacted with the package.
In the another aspect of the application, there is provided a kind of method for manufacturing semiconductor package, this method may include：
One support plate is provided, is arranged side by side on the support plate and places the first chip and the second chip, first chip has the first installation
Face and multiple the first contacts for being emerging in first mounting surface, second chip have the second mounting surface and multiple aobvious
The second contact of second mounting surface is exposed at, a gap side by side, institute are formed between first chip and second chip
State the first mounting surface and second mounting surface is attached at the support plate；One package is provided, have the 3rd mounting surface and by
3rd mounting surface recessed the first cavity and the second cavity；The package is covered in first chip and described
On two chips, the 3rd mounting surface is attached at the support plate so that the 3rd mounting surface is aligned in first mounting surface
With second mounting surface, first chip is placed in first cavity, and second chip is placed in described second
In cavity, there is the first gap, second cavity and second chip between first cavity and first chip
Between there is the second gap；Heat conducting medium filling is had in first gap and second gap, the heat-conducting medium
Surface is filled, connects the first mounting surface, second mounting surface and the 3rd mounting surface so that first installation
Face, second mounting surface and the 3rd mounting surface are formed in a continuous surface；Separate the support plate；In the continuous surface
Upper formed reroutes layer, and the rewiring layer may include the first fan-in pad, the second fan-in pad and external pad, and described first
Fan-in pad is engaged in first contact and is connected to the corresponding external pad via the first fan-out circuit, and described second
Fan-in pad is engaged in second contact and is connected to the corresponding external pad, the heavy cloth via the second fan-out circuit
Line layer may also include interconnection line at least one, connect the first fan-in pad and the second fan-in pad；And monomer
Change and separate the package, multiple semiconductor packages are made, each semiconductor package may include described first
Chip and second chip.
Alternatively, this method may additionally include to plant the first soldered ball before singulation separates the package and be connected on outside described
Connect on pad.
Alternatively, this method, which may also include, provides a bearing substrate, has first surface and second surface, the carrying base
Plate includes the interconnect pad positioned at the first surface, the terminal pad positioned at the second surface and is electrically connected described mutual
The circuit of connected bonding pads and the terminal pad；The interconnect pad is bonded with first soldered ball；And the second soldered ball is planted
It is connected on the terminal pad.
Alternatively, the package also has passage, connects first cavity and second cavity；When the heat conduction
Filled Dielectrics are also filled in the passage in first gap and second gap, the heat-conducting medium.
Alternatively, the material of the package includes silicon.
Alternatively, in the covering step of the package, the width range in first gap and second gap
Between 10 microns to 100 microns so that first chip and second chip are not directly contacted with the package.
Through the above technical solutions, heat-conducting medium surrounds chip surrounding, can be effectively quick by heat caused by chip operation
Disperse.
Other features and advantage will be described in detail in subsequent specific embodiment part.
Brief description of the drawings
Attached drawing is for providing further understanding of the present application, and a part for constitution instruction, with following tool
Body embodiment is used to explain the application together, but does not form the limitation to the application.In the accompanying drawings：
Fig. 1 is the sectional view according to the semiconductor package of the embodiment of the application；
Fig. 2 is the sectional view according to the semiconductor package of the further embodiment of the application；
Fig. 3 is the sectional view according to the semiconductor package of another further embodiment of the application；
Fig. 4 is the top view according to the semiconductor package of the further embodiment of the application；
Fig. 5 shows the encapsulation formed on Silicon Wafer in the semiconductor package according to presently filed embodiment
Cover；
Fig. 6 A to Fig. 6 H show the method for manufacturing semiconductor package of the embodiment according to the application
The schematic diagram of the structure obtained after each step is performed.
Description of reference numerals
100 semiconductor package, 110 first chip
111 first mounting surface, 112 first contact
113 first passivation layers 114 gap side by side
120 second chip, 121 second mounting surface
122 second contact, 123 second passivation layer
The 3rd mounting surface of 130 package 131
132 first cavity, 133 second cavity
134 first gap, 135 second gap
136 first opening, 137 second opening
138 passage, 140 heat-conducting medium
141 filling surfaces 150 reroute layer
151 first surface, 152 second surface
153 first fan-in pad, 154 second fan-in pad
155 external the first fan-out circuits of pad 156a
Interconnection line in the second fan-out circuits of 156b 156c
157 first soldered ball, 160 bearing substrate
161 first surface, 162 second surface
163 interconnect pad, 164 terminal pad
165 circuit, 166 second soldered ball
167 solder mask, 200 support plate
210 adhesive tapes
Embodiment
The embodiment of the application is described in detail below in conjunction with attached drawing.It should be appreciated that this place is retouched
The embodiment stated is only used for describing and explaining the application, is not limited to the application.
In this application, in the case where not making conversely explanation, the noun of locality that uses as " above/above and below/under,
The left side/left side, the right/right side " typically refers to shown upper and lower, left and right referring to the drawings." inside and outside " is typically referred to relative to each
Component profile itself it is inside and outside.
In this application if using term " front of chip ", " active face of chip ", " first surface of chip ",
It can refer to the surface with integrated circuit；In this application if using term " back side of chip ", " the second table of chip
Face ", then its can refer to the surface opposite with " front of chip ", " active face of chip ", " first surface of chip ".
In the accompanying drawings, the shape shown can have deformation according to manufacturing process and/or tolerance.Therefore, the example of the application
Property embodiment be not limited to the given shape that is shown in attached drawing, and alteration of form caused by can including in the fabrication process.This
Outside, the different elements in attached drawing and region are simply schematically shown, therefore the application is not limited to the relative size that is shown in attached drawing
Or distance.
Fig. 1 is the sectional view according to the semiconductor package 100 of the embodiment of the application.With reference to figure 1, according to this
The semiconductor package 100 of the embodiment of application can include the first chip 110 and the second chip 120.First chip 110
It can be arranged side by side with the second chip 120.First chip 110 can have the first mounting surface 111 and multiple be emerging in first
First contact 112 of mounting surface 111.For example, the first mounting surface 111 can be the active face of the first chip 110, the first contact
112 can be the first chip bonding pad.In addition, the region beyond the first chip bonding pad 1 on the first mounting surface 111 can cover
There is the first passivation layer 113.The species of first passivation layer 113 can include but is not limited to unorganic glass and organic polymer.It is inorganic
The material of glass can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、Fe2O3、SixOy), silicate
(for example, PSG, BSG, BPSG), nitride are (for example, Si3N4、SixNyH、BN、AlN、GaN).Organic macromolecule material can be with
Including but not limited to synthetic resin (for example, polyimide based resin, polysiloxanes resinoid), synthetic rubber are (for example, silicone
Rubber).
Second chip 120 can have the second mounting surface 121 and multiple the second contacts for being emerging in the second mounting surface 121
122.For example, the second mounting surface 121 can be the active face of the second chip 120, the second contact 122 can be the weldering of the second chip
Disk.In addition, the region beyond the second chip bonding pad on the second mounting surface 121 can be covered with the second passivation layer 123.Second
The species of passivation layer 123 can include but is not limited to unorganic glass and organic polymer.The material of unorganic glass can include but
Oxide is not limited to (for example, SiO2、Al2O3、TiO2、ZrO2、Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitrogen
Compound is (for example, Si3N4、SixNyH、BN、AlN、GaN).Organic macromolecule material can be including but not limited to synthetic resin
(for example, polyimide based resin, polysiloxanes resinoid), synthetic rubber (for example, silicone rubber).
The type of first chip 110 can include memory chip and logic chip.The example of memory chip can wrap
Include but be not limited to, random access memory (RAM).The example of RAM can include dynamic random access memory (DRAM) or quiet
State random access memory (SRAM).The example of logic chip can include but is not limited to, graphics processing unit (Graphic
Processing Unit, GPU) it is chip, central processing unit (Central Processing Unit, CPU) chip, system-level
Chip (System on Chip, SOC).
The type of second chip 120 can include memory chip and logic chip.The example of memory chip can wrap
Include but be not limited to, random access memory (RAM).The example of RAM can include dynamic random access memory (DRAM) or quiet
State random access memory (SRAM).The example of logic chip can include but is not limited to, graphics processing unit (Graphic
Processing Unit, GPU) it is chip, central processing unit (Central Processing Unit, CPU) chip, system-level
Chip (System on Chip, SOC).
In the embodiment of the application, the first chip 110 may, for example, be logic chip, and the second chip 120 can be with
E.g. memory chip.
In the embodiment of the application, gap side by side can be formed between the first chip 110 and the second chip 120
114。
Semiconductor package 100 can also include package 130.Package 130 can have the 3rd mounting surface 131 with
And by the 3rd mounting surface 131 recessed the first cavity 132 and the second cavity 133.3rd mounting surface 131 can be aligned in the first peace
111 and second mounting surface 121 of dress face, the first chip 110 can be placed in the first cavity 132, and the second chip 120 can house
In in the second cavity 133.Can have the first gap 134 between first cavity 132 and the first chip 110, the second cavity 133 with
There can be the second gap 135 between second chip 120.For example, in one example, the side and first of the first chip 110
Cavity 132 with or without but between gap it is extremely small (contact can be considered as), the only top surface of the first chip 110
There is the first gap 134 between the first cavity 132.In another example, the top surface and the first cavity of the first chip 110
132 with or without but between gap it is extremely small (contact can be considered as), the only side of the first chip 110 and the
There is the first gap 134 between one cavity 132.In another example, a part in the side of the first chip 110 (such as
It is one or more) it is extremely small (can be considered as and contact) with or without the gap between still with the first cavity 132, the
There is the first gap 134 between remainder and top surface and the first cavity 132 in the side of one chip 110.Preferably showing
In example, there is the first gap 134 between the side of the first chip 110 and top surface and the first cavity 132.The width in the first gap 134
Spending scope can be between 10 micron to 100 microns so that the first chip 110 is not directly contacted with package 130.This can be conducive to
Inserting for heat-conducting medium 140 and being formed continuously for continuous surface.
For example, in one example, the side of the second chip 120 and the second cavity 133 with or without but it
Between gap it is extremely small (contact can be considered as), only between the top surface of the second chip 120 and the second cavity 133 have second between
Gap 135.In another example, the top surface of the second chip 120 and the second cavity 133 with or without but between
Gap is extremely small (can be considered as contact), has the second gap 135 only between the side of the second chip 120 and the second cavity 133.
In another example, a part in the side of the second chip 120 (such as one or more) contacted with the second cavity 133 or
Person do not contact but between gap it is extremely small (contact can be considered as), remainder in the side of the second chip 120 with
And there is the second gap 135 between top surface and the second cavity 133.In preferred exemplary, the side of the second chip 120 and top surface with
There is the second gap 135 between second cavity 133.The width range in the second gap 135 can between 10 microns to 100 microns,
So that the second chip 120 is not directly contacted with package 130.This can be conducive to heat-conducting medium 140 insert and continuous surface
Be formed continuously.
Semiconductor package 100 can also include heat-conducting medium 140, be filled in the first gap 134 and the second gap
135, heat-conducting medium 140 has filling surface 141, the first mounting surface 111 of connection, the second mounting surface 121 and the 3rd mounting surface
131 so that the first mounting surface 111, the second mounting surface 121 and the 3rd mounting surface 131 are formed in a continuous surface.For example, heat conduction
Medium 140 can be selected from and is made of superhigh temperature heat-conducting glue, organosilicon heat-conducting glue, epoxy resin AB glue, polyurethane adhesive, heat-conducting silicone grease
At least one of group.Heat-conducting medium 140 not only can glue the first chip 110 and the second chip 120 with package 130
Close, heat dissipation can also be played the role of.
Semiconductor package 100 can also include rerouting layer 150, be formed on continuous surface, rerouting layer 150 can
With including the first fan-in pad 153, the second fan-in pad 154 and external pad 155.First fan-in pad 153 can engage
Corresponding external pad 155 is connected in the first contact 112 and via the first fan-out circuit 156a rerouted in layer 150.The
Two fan-in pads 154 are engaged in the second contact 122 and are connected to correspondence via the second fan-out circuit 156b rerouted in layer 150
External pad 155.Interconnection line 156c at least one can also be included by rerouting layer 150, the first fan-in pad 153 of connection with
Second fan-in pad 154.For example, the first fan-in pad 153 and the second fan-in pad 154, which can be located at, reroutes the of layer 150
On one surface 151, external pad 155 can be located on the second surface 152 opposite with first surface 151.
Specifically, the circuit of dielectric layer and formation in the dielectric layer can be included (for example, the first fan by rerouting layer 150
Go out circuit 156a, the second fan-out circuit 156b, interior interconnection line 156c etc.).The material of dielectric layer can include macromolecule membrane
Material, such as benzocyclobutene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer can also include other
Insulating materials.It is for instance possible to use pad (the example that the technology of rewiring forms circuit and is electrically connected with circuit in the dielectric layer
Such as, the first fan-in pad 153, the second fan-in pad 154, external pad 155 etc.).RDL technologies are known to those skilled in the art
Technology, repeat no more herein.In the embodiment of the application, the material of circuit can include one in copper and aluminium
Person.But it will be understood by those skilled in the art that the material of circuit can include other metals (such as gold, silver, platinum) or metal
Other kinds of conductive material in addition.In the embodiment of the application, circuit and pad can use identical material
Material.In another embodiment herein, circuit and pad can use different materials.In the embodiment of the application
In, any one in the first fan-out circuit 156a, the second fan-out circuit 156b and interior interconnection line 156c is micro- with being less than 15
Line width/line-spacing of rice.
Semiconductor packages can also include the first soldered ball 157, and plant is connected on external pad 155.It is, for example, possible to use plant ball
Technique, which plants the first soldered ball 157, is connected to external pad 155.
In the embodiment of the application, package 130 can also have connected with the first cavity 132 first to open
Mouth 136 and the second opening 137 connected with the second cavity 133, for inserting for heat-conducting medium 140.As shown in Figure 1, first opens
136 and/or second opening 137 of mouth can be located at the top of package 130, it will be recognized to those skilled in the art that first
136 and/or second opening 137 of opening may be located on the other positions of package 130.First opening 136 and/or the second opening
137 shape can be included in oval (Elliptic Cylinder), circular (cylinder), square (rectangular cylinder), prismatic (prism)
Any one.It will be recognized to those skilled in the art that the first opening 136 and/or the second opening 137 can also have not
The other shapes enumerated.Fig. 4 is the top view according to the semiconductor package 100 of the further embodiment of the application.Such as
Shown in Fig. 4, the shape of the first opening 136 can be oval (Elliptic Cylinder), and the shape of the second opening 137 can be circular
(cylinder), it will be recognized to those skilled in the art that the first opening 136 and the shape of the second opening 137 that are shown in Fig. 4
It is exemplary, the first opening 136 and the second opening 137 there can also be other combination of shapes.In one example, first open
The size of mouth 136 can be less than the size of the second opening 137.In another example, the size of the first opening 136 can be equal to the
The size of two openings 137.In the better embodiment of the application, the size of the first opening 136 can be more than the second opening 137
Size.
In the presently filed embodiment shown in Fig. 1, the first opening 136 and the second opening 137 may be used as the respectively
The entrance of one cavity 132 and the second cavity 133, i.e. heat-conducting medium 140 are noted respectively by the first opening 136 and the second opening 137
Enter into the first cavity 132 and the second cavity 133, and the first cavity 132 and the second cavity 133 and preferably can be filled
One opening 136 and the second opening 137.
Fig. 2 is the sectional view according to the semiconductor package 100 of the further embodiment of the application.With reference to figure 2, figure
The semiconductor package 100 shown in 2 and the semiconductor package 100 shown in Fig. 1 are essentially identical, and difference lies in Fig. 2
In package 130 in the semiconductor package 100 that shows can also have passage 138, connect the first cavity 132 and second
Cavity 133, heat-conducting medium 140 are also filled up in passage 138.As shown in Fig. 2, in one example, passage 138 can be empty by first
The groove on wall between 132 and second cavity 133 of chamber is formed.In another example, as passage 138 can be by the first cavity
132 and the second wall between cavity 133 on through hole formed.In the semiconductor according to presently filed embodiment shown in Fig. 4
In the top view of encapsulating structure 100, the first opening 136 may be used as glue inlet, and the second opening 137 may be used as gum outlet.
In the alternative embodiments of the application, the first opening 136 may be used as gum outlet, and the second opening 137 may be used as glue inlet.
In the embodiment for the size that the size of the first opening 136 is more than the second opening 137, the first opening 136 may be used as into glue
Mouthful, the second opening 137 may be used as gum outlet.It can be filled from the first 136 filling heat-conductive media 140 of opening, heat-conducting medium 140
Second cavity 133 is filled by passage 138 after first cavity 132, is then come out from the second opening 137, heat conduction is thus completed and is situated between
The filling of matter 140.
In presently filed embodiment, the material of package 130 can be including but not limited to glass, ceramics etc..At this
In the better embodiment of application, the material of package 130 can include silicon.Plastic packaging material is used (for example, asphalt mixtures modified by epoxy resin with traditional
Fat moulding compound (Epoxy Molding Compound, EMC)) encapsulation chip compare, encapsulated using the package 130 of silicon materials
Chip, because of the relatively low thermal coefficient of expansion of silicon, the angularity (Warpage) being thus easier on control processing procedure.
In presently filed embodiment, can using lithographic technique come formed in package 130 first cavity 132,
At least one of the 136, second opening 137 of second cavity 133, first opening, passage 138.In the preferable embodiment party of the application
In formula, package 130 can be formed on Silicon Wafer.Fig. 5 shows and is formed on Silicon Wafer according to presently filed embodiment
Semiconductor package 100 in package 130.As shown in figure 5, it can be etched on Silicon Wafer spaced multiple
First cavity 132 and multiple second cavitys 133 (and alternatively, first the 136, second opening 137 of opening, passage 138).Then
Singulation separation (such as cutting) is carried out to Silicon Wafer to obtain required package 130.It is ability that etching is separated with singulation
Any known routine techniques of field technique, the application repeat no more this.
Fig. 3 is the sectional view according to the semiconductor package 100 of another further embodiment of the application.Reference chart
3, semiconductor package 100 can also include bearing substrate 160.Bearing substrate 160 can have first surface 161 and second
Surface 162.Bearing substrate 160 can include interconnect pad 163, the terminal positioned at second surface 162 positioned at first surface 161
Pad 164 and the circuit 165 for being electrically connected interconnect pad 163 and terminal pad 164.Interconnect pad 163 can be with the first soldered ball
157 bondings.
Bearing substrate 160 can be but not limited to line film.Specifically, bearing substrate 160 can include dielectric layer,
The circuit 165 being formed in dielectric layer, and be separately positioned on the first surface 161 of bearing substrate 160 and second surface
The interconnect pad 163 and terminal pad 164 being electrically connected on 162 and with circuit 165.It is, for example, possible to use printed circuit board (PCB)
(Printed Circuit Board, PCB) processing procedure forms circuit 165.In presently filed embodiment, the material of circuit 165
Material can include gold, silver, platinum, aluminium, copper.In a preferred embodiment, the material of circuit 165 can include copper.
In presently filed embodiment, semiconductor package 100 can also include the second soldered ball 166, and plant is connected on end
On sub- pad 164.Terminal pad 164 is connected to it is, for example, possible to use planting ball technique and planting the second soldered ball 166.
In presently filed embodiment, there can be solder mask on the second surface 162 (bottom surface) of bearing substrate 160
(Solder Mask) 167, the solder mask 167 do not cover the terminal pad 164 on 160 bottom surface of bearing substrate.In addition, in terminal
Planted on pad 164 first can carry out surface polishing treatment before connecing the second soldered ball 166 to the surface of terminal pad 164.
Crystal wafer chip dimension encapsulation can be applied to according to the semiconductor package 100 of the application embodiment
In (Wafer Level Chip Size Package, WLCSP), formula (Fan-out) WLCSP (FOWLCSP) is especially fanned out to
In.
Presently filed embodiment also provides the method for manufacturing semiconductor package.Fig. 6 A to Fig. 6 H show root
The knot obtained according to the method for being used to manufacture semiconductor package of the embodiment of the application after each step is performed
The schematic diagram of structure.With reference to figure 6A to Fig. 6 H, may comprise steps of according to the method for presently filed embodiment.
With reference to figure 6A, in step s 102, there is provided a support plate 200, is arranged side by side on the support plate 200 and places the first chip
110 and second chip 120.First chip 110 has the first mounting surface 111 and multiple is emerging in the of the first mounting surface 111
One contact 112.Second chip 120 has the second mounting surface 121 and multiple the second contacts for being emerging in the second mounting surface 121
122.Gap 114 side by side are formed between first chip 110 and the second chip 120.First mounting surface 111 and the second mounting surface
121 can be attached at support plate 200.For example, the first mounting surface 111 can be the active face of the first chip 110, the first contact 112
It can be the first chip bonding pad.In addition, the region beyond the first chip bonding pad on the first mounting surface 111 can be covered with
One passivation layer 113.The species of first passivation layer 113 can include but is not limited to unorganic glass and organic polymer.Unorganic glass
Material can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、Fe2O3、SixOy), silicate (example
Such as, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).Organic macromolecule material can include
But it is not limited to, synthetic resin (for example, polyimide based resin, polysiloxanes resinoid), synthetic rubber are (for example, silicone rubber
Glue).
Second chip 120 can have the second mounting surface 121 and multiple the second contacts for being emerging in the second mounting surface 121
122.For example, the second mounting surface 121 can be the active face of the second chip 120, the second contact 122 can be the weldering of the second chip
Disk.In addition, the region beyond the second chip bonding pad on the second mounting surface 121 can be covered with the second passivation layer 123.Second
The species of passivation layer 123 can include but is not limited to unorganic glass and organic polymer.The material of unorganic glass can include but
Oxide is not limited to (for example, SiO2、Al2O3、TiO2、ZrO2、Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitrogen
Compound is (for example, Si3N4、SixNyH、BN、AlN、GaN).Organic macromolecule material can be including but not limited to synthetic resin (example
Such as, polyimide based resin, polysiloxanes resinoid), synthetic rubber (for example, silicone rubber).
The type of first chip 110 can include memory chip and logic chip.The example of memory chip can wrap
Include but be not limited to random access memory (RAM).The example of RAM can include dynamic random access memory (DRAM) or static state
Random access memory (SRAM).The example of logic chip can include but is not limited to graphics processing unit (Graphic
Processing Unit, GPU) it is chip, central processing unit (Central Processing Unit, CPU) chip, system-level
Chip (System on Chip, SOC).
The type of second chip 120 can include memory chip and logic chip.The example of memory chip can wrap
Include but be not limited to random access memory (RAM).The example of RAM can include dynamic random access memory (DRAM) or static state
Random access memory (SRAM).The example of logic chip can include but is not limited to, graphics processing unit (Graphic
Processing Unit, GPU) it is chip, central processing unit (Central Processing Unit, CPU) chip, system-level
Chip (System on Chip, SOC).
In the embodiment of the application, the first chip 110 may, for example, be logic chip, and the second chip 120 can be with
E.g. memory chip.
In the embodiment of the application, known good chip (Known Good can be selected from the first chip 110
Die, KGD), KGD can be selected from the second chip 120.
With reference to figure 6B, in step S104, there is provided a package 130, the package 130 can have the 3rd mounting surface
131 and by the 3rd mounting surface 131 recessed the first cavity 132 and the second cavity 133.
With reference to figure 6C, in step s 106, package 130 is covered on the first chip 110 and the second chip 120, the
Three mounting surfaces 131 are attached at the support plate 200 so that the 3rd mounting surface 131 is aligned in the first mounting surface 111 and the second mounting surface
121, the first chip 110 is placed in the first cavity 132, and the second chip 120 is placed in the second cavity 133, the first cavity 132
There is the first gap 134 between the first chip 110, there is the second gap 135 between the second cavity 133 and the second chip 120.
For example, in one example, the side of the first chip 110 and the first cavity 132 with or without but it
Between gap it is extremely small (contact can be considered as), only between the top surface of the first chip 110 and the first cavity 132 have first between
Gap 134.In another example, the top surface of the first chip 110 and the first cavity 132 with or without but between
Gap is extremely small (can be considered as contact), has the first gap 134 only between the side of the first chip 110 and the first cavity 132.
In another example, a part in the side of the first chip 110 (such as one or more) contacted with the first cavity 132 or
Person do not contact but between gap it is extremely small (contact can be considered as), remainder in the side of the first chip 110 with
And there is the first gap 134 between top surface and the first cavity 132.In preferred exemplary, the side of the first chip 110 and top surface with
There is the first gap 134 between first cavity 132.The width range in the first gap 134 can between 10 microns to 100 microns,
So that the first chip 110 is not directly contacted with package 130.This can be conducive to heat-conducting medium 140 insert and continuous surface
Be formed continuously.
For example, in one example, the side of the second chip 120 and the second cavity 133 with or without but it
Between gap it is extremely small (contact can be considered as), only between the top surface of the second chip 120 and the second cavity 133 have second between
Gap 135.In another example, the top surface of the second chip 120 and the second cavity 133 with or without but between
Gap is extremely small (can be considered as contact), has the second gap 135 only between the side of the second chip 120 and the second cavity 133.
In another example, a part in the side of the second chip 120 (such as one or more) contacted with the second cavity 133 or
Person do not contact but between gap it is extremely small (contact can be considered as), remainder in the side of the second chip 120 with
And there is the second gap 135 between top surface and the second cavity 133.In preferred exemplary, the side of the second chip 120 and top surface with
There is the second gap 135 between second cavity 133.The width range in the second gap 135 can between 10 microns to 100 microns,
So that the second chip 120 is not directly contacted with package 130.This can be conducive to heat-conducting medium 140 insert and continuous surface
Be formed continuously.
In the embodiment of the application, package 130 can also have connected with the first cavity 132 first to open
Mouth 136 and the second opening 137 connected with the second cavity 133, for inserting for heat-conducting medium 140.As shown in Figure 6 C, first open
136 and/or second opening 137 of mouth can be located at the top of package 130, it will be recognized to those skilled in the art that first
136 and/or second opening 137 of opening may be located on the other positions of package 130.First opening 136 and/or the second opening
137 shape can be included in oval (Elliptic Cylinder), circular (cylinder), square (rectangular cylinder), prismatic (prism)
Any one.It will be recognized to those skilled in the art that the first opening 136 and/or the second opening 137 can also have not
The other shapes enumerated.The shape of first opening 136 can be oval (Elliptic Cylinder), and the shape of the second opening 137 can be with
It is circular (cylinder), it will be recognized to those skilled in the art that the first opening 136 and the second opening 137 can also have it
His combination of shapes.In one example, the size of the first opening 136 can be less than the size of the second opening 137.Show another
In example, the size of the first opening 136 can be equal to the size of the second opening 137.In the better embodiment of the application, first
The size of opening 136 can be more than the size of the second opening 137.
In the further embodiment of the application, package 130 can also have passage 138, connect the first cavity 132
With the second cavity 133, heat-conducting medium 140 is also filled up in passage 138.In one example, passage 138 can be by the first cavity
132 and the second wall between cavity 133 on groove formed.In another example, passage 138 can be by the first cavity 132
The through hole on wall between the second cavity 133 is formed.
In presently filed embodiment, the material of package 130 can be including but not limited to glass, ceramics etc..At this
In the better embodiment of application, the material of package 130 can include silicon.Plastic packaging material is used (for example, asphalt mixtures modified by epoxy resin with traditional
Fat moulding compound (Epoxy Molding Compound, EMC)) encapsulation chip compare, encapsulated using the package 130 of silicon materials
Chip, because of the relatively low thermal coefficient of expansion of silicon, the angularity (Warpage) being thus easier on control processing procedure.
In presently filed embodiment, can using lithographic technique come formed in package 130 first cavity 132,
At least one of the 136, second opening 137 of second cavity 133, first opening, passage 138.In the preferable embodiment party of the application
In formula, package 130 can be formed on Silicon Wafer.Thus, the offer package 130 in step S104 can include following step
Suddenly.Spaced multiple first cavitys 132 and multiple second cavitys 133 can be etched on Silicon Wafer.And alternatively,
It can etch any in the first opening 136, second opening 137, passage 138.Then singulation separation is carried out to Silicon Wafer
(such as cutting) is to obtain required package 130.It is any known conventional skill of art technology that etching is separated with singulation
Art, the application repeat no more this.
With reference to figure 6D, in step S108, heat-conducting medium 140 is filled in the first gap 134 and the second gap 135.Lead
Thermal medium 140 has filling surface 141, the first mounting surface 111 of connection, the second mounting surface 121 and the 3rd mounting surface 131 so that
First mounting surface 111, the second mounting surface 121 and the 3rd mounting surface 131 are formed in a continuous surface.
In package 130 without in the embodiment of the first opening 136 and the second opening 137, step S108 can be
Occur before step S106, that is to say, that after the first chip 110 and the second chip 120 is installed, in the first chip 110
With coated with thermally conductive medium 140 on 120 surface of the second chip so that it covers the first chip 110 and the second chip 120, and form one
Determine 140 layers of the heat-conducting medium of thickness.Then step S106 is performed so that the first chip 110 is placed in the first cavity 132
And second chip 120 be placed in the second cavity 133, and 140 layers of heat-conducting medium the first gap 134 of filling and the second gap
135。
In the embodiment that package 130 has the first opening 136 and the second opening 137, the first opening can be passed through
136 and second opening 137 heat-conducting medium 140 is filled in the first gap 134 and the second gap 135 respectively.
, can be by the first opening 136 and the second opening 137 in the package 130 also embodiment with passage 138
One of be used as glue inlet, heat-conducting medium 140 can be injected into the first cavity by another one as gum outlet by glue inlet
132 and second cavity 133, unnecessary heat-conducting medium 140 can be come out from gum outlet.
Heat-conducting medium 140 can be selected from by superhigh temperature heat-conducting glue, organosilicon heat-conducting glue, epoxy resin AB glue, polyurethane adhesive,
At least one of group of heat-conducting silicone grease composition.Heat-conducting medium 140 not only can by the first chip 110 and the second chip 120 with
Package 130 bonds, and can also play the role of heat dissipation.
With reference to figure 6E, in step s 110, support plate 200 is separated.Specifically, in the embodiment of the application,
An adhesive tape 210, such as hot degumming film, in step s 102, the first chip 110 and the second chip can be attached on support plate 200
120 are placed on the hot degumming film.After execution of step S108, which (such as can be passed through
Laser irradiates), it is lost viscosity, thus support plate 200 is stripped.
In the alternative embodiments of the application, support plate can be separated using other modes.Such as can be in glass
Ultraviolet (UV) photosensitive viscose glue is coated on glass piece or semiconductor carrier plate, carrying out irradiation to the photosensitive viscose glues of UV after step S108 makes
It loses viscosity, it is possible to peels off support plate 200.
It will be understood by those skilled in the art that the mode of other separation support plates 200 commonly used in the art should also belong to this
The scope of application.
After support plate 200 is separated, the packaging body upset obtained after step S108 can will be performed.
With reference to figure 6F, in step S112, formed on continuous surface and reroute layer 150.Rerouting layer 150 includes first
Fan-in pad 153, the second fan-in pad 154 and external pad 155.First fan-in pad 153 be engaged in the first contact and via
First fan-out circuit 156a is connected to corresponding external pad 155.Second fan-in pad 154 is engaged in the second contact and via
Two fan-out circuit 156b are connected to corresponding external pad 155.Reroute layer 150 and further include interconnection line 156c at least one,
Connect the first fan-in pad 153 and the second fan-in pad 154.
Specifically, the circuit of dielectric layer and formation in the dielectric layer can be included (for example, the first fan by rerouting layer 150
Go out circuit 156a, the second fan-out circuit 156b, interior interconnection line 156c etc.).The material of dielectric layer can include macromolecule membrane
Material, such as benzocyclobutene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer can also include other
Insulating materials.It is for instance possible to use pad (the example that the technology of rewiring forms circuit and is electrically connected with circuit in the dielectric layer
Such as, the first fan-in pad 153, the second fan-in pad 154, external pad 155 etc.).RDL technologies are known to those skilled in the art
Technology, repeat no more herein.In the embodiment of the application, the material of circuit can include one in copper and aluminium
Person.But it will be understood by those skilled in the art that the material of circuit can include other metals (such as gold, silver, platinum) or metal
Other kinds of conductive material in addition.In the embodiment of the application, circuit and pad can use identical material
Material.In another embodiment herein, circuit and pad can use different materials.In the embodiment of the application
In, any one in the first fan-out circuit 156a, the second fan-out circuit 156b and interior interconnection line 156c is micro- with being less than 15
Line width/line-spacing of rice.
In step S114, the first soldered ball 157 is planted and is connected on external pad 155.Will it is, for example, possible to use planting ball technique
First soldered ball 157, which is planted, is connected to external pad 155.
With reference to figure 6G, in step S116, the packaging body and singulation that overturn separate package 130, more to be made
A semiconductor package, each semiconductor package include the first chip 110 and the second chip 120.
In the further embodiment of the application, the method for manufacturing semiconductor package can also include following
Step.
With reference to figure 6H, in step S118, there is provided a bearing substrate 160, the bearing substrate 160 can have first surface
161 and second surface 162, bearing substrate 160 includes the interconnect pad 163 positioned at first surface 161, positioned at second surface 162
Terminal pad 164 and be electrically connected the circuit 165 of interconnect pad 163 and terminal pad 164.
Bearing substrate 160 can be but not limited to line film.Specifically, bearing substrate 160 can include dielectric layer,
The circuit 165 being formed in dielectric layer, and be separately positioned on the first surface 161 of bearing substrate 160 and second surface
The interconnect pad 163 and terminal pad 164 being electrically connected on 162 and with circuit 165.It is, for example, possible to use printed circuit board (PCB)
(Printed Circuit Board, PCB) processing procedure forms circuit 165.In presently filed embodiment, the material of circuit 165
Material can include gold, silver, platinum, aluminium, copper.In a preferred embodiment, the material of circuit can include copper.
In presently filed embodiment, there can be solder mask on the second surface 162 (bottom surface) of bearing substrate 160
(Solder Mask) 167, the solder mask 167 do not cover the terminal pad 164 on 160 bottom surface of bearing substrate.In addition, in terminal
Planted on pad 164 first can carry out surface polishing treatment before connecing the second soldered ball 166 to the surface of terminal pad 164.
In the step s 120, interconnect pad 163 is bonded with the first soldered ball 157.
In step S122, the second soldered ball 166 is planted and is connected on terminal pad 164.Will it is, for example, possible to use planting ball technique
Second soldered ball 166, which is planted, is connected to terminal pad 164.
Wafer stage chip can be applied to according to the method for being used to manufacture semiconductor package of the application embodiment
In sized package (Wafer Level Chip Size Package, WLCSP) technique, formula (Fan-out) is especially fanned out to
In WLCSP (FOWLCSP) technique.
It is used to manufacture according to the semiconductor package 100 of the application embodiment or according to presently filed embodiment
The semiconductor package of the method manufacture of semiconductor package, the epoxy resin mould in common process is replaced using silicon materials
Plastics (Epoxy Molding Compound, EMC) carry out plastic package chip, its thermal coefficient of expansion is lower, it is easier to controls on processing procedure
Angularity (Warpage).In addition, heat-conducting medium surrounds chip surrounding, can be effectively quick scattered by heat caused by chip operation
Go.
In addition, according to the semiconductor package 100 of the application embodiment or the use according to presently filed embodiment
There can be smaller in being encapsulated applied to SIP in the semiconductor package of the method manufacture of manufacture semiconductor package
Shape factor is connected with shorter signal, and good thermal diffusivity.
In addition, the step of method for manufacturing semiconductor package of embodiment of above description, only describes system
Some key steps of manufacturing semiconductor encapsulating structure, it will be appreciated by those skilled in the art that in whole semiconductor packaging process also
It can include some other known steps, to make the description of the present application brief and concise, these conventional known steps are at this
It is not described in application, but should also be as being considered as scope of the present application.
The preferred embodiment of the application is described in detail above in association with attached drawing, still, the application is not limited to above-mentioned reality
The detail in mode is applied, in the range of the technology design of the application, a variety of letters can be carried out to the technical solution of the application
Monotropic type, these simple variants belong to the protection domain of the application.
It is further to note that each particular technique feature described in above-mentioned embodiment, in not lance
In the case of shield, it can be combined by any suitable means.In order to avoid unnecessary repetition, the application to it is various can
The combination of energy no longer separately illustrates.
In addition, it can also be combined between a variety of embodiments of the application, as long as it is without prejudice to originally
The thought of application, it should equally be considered as content disclosed in the present application.
Claims (16)
- A kind of 1. semiconductor package, it is characterised in that including：The first chip and the second chip being arranged side by side, first chip have the first mounting surface and it is multiple be emerging in it is described First contact of the first mounting surface, second chip have the second mounting surface and multiple are emerging in second mounting surface Second contact, forms a gap side by side between first chip and second chip；Package, has the 3rd mounting surface and by the 3rd mounting surface recessed the first cavity and the second cavity, and described the Three mounting surfaces are aligned in first mounting surface and second mounting surface, and first chip is placed in first cavity Interior, second chip is placed in second cavity, is had between first cavity and first chip between first Gap, has the second gap between second cavity and second chip；Heat-conducting medium, is filled in first gap and second gap, and the heat-conducting medium has filling surface, connects institute State the first mounting surface, second mounting surface and the 3rd mounting surface so that first mounting surface, second mounting surface And the 3rd mounting surface is formed in a continuous surface；Reroute layer, be formed on the continuous surface, it is described rewiring layer include the first fan-in pad, the second fan-in pad and External pad, the first fan-in pad are engaged in first contact and are connected to via the first fan-out circuit corresponding described External pad, the second fan-in pad are engaged in second contact and are connected to via the second fan-out circuit corresponding described External pad, the rewiring layer further include interconnection line at least one, connect the first fan-in pad and the described second fan Enter pad.
- 2. semiconductor package according to claim 1, it is characterised in that the package also has passage, connection First cavity and second cavity, the heat-conducting medium are also filled in the passage.
- 3. semiconductor package according to claim 1, it is characterised in that further include：First soldered ball, plant are connected on the external pad.
- 4. semiconductor package according to claim 3, it is characterised in that further include：Bearing substrate, has first surface and second surface, and the bearing substrate includes the interconnection weldering positioned at the first surface Disk, the terminal pad positioned at the second surface and the circuit for being electrically connected the interconnect pad and the terminal pad, it is described Interconnect pad is bonded with first soldered ball；AndSecond soldered ball, plant are connected on the terminal pad.
- 5. semiconductor package according to claim 1, it is characterised in that the package also has and described first First opening of cavity connection and the second opening connected with second cavity, for inserting for the heat-conducting medium.
- 6. semiconductor package according to claim 5, it is characterised in that first opening or second opening Shape include oval, circular, square, prismatic in any one.
- 7. semiconductor package according to claim 1, it is characterised in that first fan-out circuit, described second Any one in fan-out circuit and the interior interconnection line has the line width/line-spacing for being less than 15 microns.
- 8. semiconductor package according to claim 1, it is characterised in that the material of the package includes silicon.
- 9. semiconductor package according to claim 8, it is characterised in that the package be by Silicon Wafer into What row etching and singulation were separated and formed.
- 10. semiconductor package according to any one of claim 1 to 9, it is characterised in that first gap and The width range in second gap is between 10 microns to 100 microns so that first chip and second chip be not straight The contact package.
- A kind of 11. method for manufacturing semiconductor package, it is characterised in that this method includes：One support plate is provided, is arranged side by side on the support plate and places the first chip and the second chip, first chip has first Mounting surface and multiple the first contacts for being emerging in first mounting surface, second chip have the second mounting surface and more A the second contact for being emerging in second mounting surface, between one is formed between first chip and second chip side by side Gap, first mounting surface and second mounting surface are attached at the support plate；One package is provided, there is the 3rd mounting surface and by the 3rd mounting surface recessed the first cavity and the second cavity；The package is covered on first chip and second chip, the 3rd mounting surface is attached at the load Plate so that the 3rd mounting surface is aligned in first mounting surface and second mounting surface, and first chip is placed in In first cavity, second chip is placed in second cavity, first cavity and first chip it Between there is the first gap, there is the second gap between second cavity and second chip；By heat conducting medium filling in first gap and second gap, the heat-conducting medium has filling surface, connection First mounting surface, second mounting surface and the 3rd mounting surface so that first mounting surface, second installation Face and the 3rd mounting surface are formed in a continuous surface；Separate the support plate；On the continuous surface formed reroute layer, it is described rewiring layer include the first fan-in pad, the second fan-in pad and External pad, the first fan-in pad are engaged in first contact and are connected to via the first fan-out circuit corresponding described External pad, the second fan-in pad are engaged in second contact and are connected to via the second fan-out circuit corresponding described External pad, the rewiring layer further include interconnection line at least one, connect the first fan-in pad and the described second fan Enter pad；AndSingulation separates the package, and multiple semiconductor packages are made, each semiconductor package includes institute State the first chip and second chip.
- 12. according to the method for claim 11, it is characterised in that further include：The first soldered ball is planted before singulation separates the package and is connected on the external pad.
- 13. according to the method for claim 12, it is characterised in that further include：One bearing substrate is provided, there is first surface and second surface, the bearing substrate is included positioned at the first surface Interconnect pad, the terminal pad positioned at the second surface and the line for being electrically connected the interconnect pad and the terminal pad Road；The interconnect pad is bonded with first soldered ball；AndSecond soldered ball is planted and is connected on the terminal pad.
- 14. according to the method for claim 11, it is characterised in that the package also has passage, connection described first Cavity and second cavity；When the heat conducting medium filling is situated between in first gap and second gap, the heat conduction Matter is also filled in the passage.
- 15. according to the method for claim 11, it is characterised in that the material of the package includes silicon.
- 16. the method according to any one of claim 11 to 15, it is characterised in that in the covering step of the package In, the width range in first gap and second gap is between 10 microns to 100 microns so that first chip and Second chip is not directly contacted with the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711470750.5A CN107993994B (en) | 2017-12-29 | 2017-12-29 | Semiconductor packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711470750.5A CN107993994B (en) | 2017-12-29 | 2017-12-29 | Semiconductor packaging structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107993994A true CN107993994A (en) | 2018-05-04 |
| CN107993994B CN107993994B (en) | 2023-07-25 |
Family
ID=62042123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711470750.5A Active CN107993994B (en) | 2017-12-29 | 2017-12-29 | Semiconductor packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107993994B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021097814A1 (en) * | 2019-11-22 | 2021-05-27 | 华为技术有限公司 | Chip package, electronic device and method for manufacturing chip package |
| CN115332226A (en) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | Packaging structure based on ceramic intermediate layer and manufacturing method thereof |
| CN117153839A (en) * | 2023-08-28 | 2023-12-01 | 湖北三维半导体集成创新中心有限责任公司 | Packaging structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| CN102194804A (en) * | 2010-03-04 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Package structure |
| CN102915978A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
| CN206250183U (en) * | 2016-12-15 | 2017-06-13 | 吕志庆 | A kind of radiating enhanced integrated circuit packaging structure |
| CN107104058A (en) * | 2017-06-21 | 2017-08-29 | 中芯长电半导体（江阴）有限公司 | Fan-out-type list die package structure and preparation method thereof |
-
2017
- 2017-12-29 CN CN201711470750.5A patent/CN107993994B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| CN102194804A (en) * | 2010-03-04 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Package structure |
| CN102915978A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
| CN206250183U (en) * | 2016-12-15 | 2017-06-13 | 吕志庆 | A kind of radiating enhanced integrated circuit packaging structure |
| CN107104058A (en) * | 2017-06-21 | 2017-08-29 | 中芯长电半导体（江阴）有限公司 | Fan-out-type list die package structure and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021097814A1 (en) * | 2019-11-22 | 2021-05-27 | 华为技术有限公司 | Chip package, electronic device and method for manufacturing chip package |
| CN115332226A (en) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | Packaging structure based on ceramic intermediate layer and manufacturing method thereof |
| CN117153839A (en) * | 2023-08-28 | 2023-12-01 | 湖北三维半导体集成创新中心有限责任公司 | Packaging structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107993994B (en) | 2023-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11037819B2 (en) | Wafer level chip scale packaging intermediate structure apparatus and method | |
| TWI720094B (en) | Integrated fan-out package on package structure and methods of forming same | |
| KR101884971B1 (en) | Fan-out stacked system in package(sip) having dummy dies and methods of making the same | |
| US10636678B2 (en) | Semiconductor die assemblies with heat sink and associated systems and methods | |
| US9691696B2 (en) | Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication | |
| KR102239259B1 (en) | Stacked semiconductor die assembly with high efficiency thermal path and molded underfill | |
| TWI614850B (en) | A semiconductor package structure and method for forming the same | |
| US9252127B1 (en) | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture | |
| TWI441285B (en) | Recessed semiconductor substrates for package apparatus and method thereof | |
| US8039315B2 (en) | Thermally enhanced wafer level package | |
| CN105428329B (en) | Packaging part and forming method with UBM | |
| CN107403733A (en) | Three layer laminate encapsulating structures and forming method thereof | |
| CN106997855A (en) | Ic package and forming method thereof | |
| US20230245923A1 (en) | Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method | |
| KR102480685B1 (en) | Semiconductor devices and methods of manufacture | |
| CN107993994A (en) | Semiconductor package and its manufacture method | |
| TWI743996B (en) | Package structure and method of fabricating the same | |
| TW202008531A (en) | Package structure | |
| KR20210040341A (en) | Info structure and method forming same | |
| CN207624680U (en) | Semiconductor package | |
| TW201642428A (en) | Silicon interposer and fabrication method thereof | |
| TWI830528B (en) | Package and method forming same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20181008 Address after: 230601 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant after: CHANGXIN MEMORY TECHNOLOGIES, Inc. Address before: 230601 No. 3188, Yun Gu Road, Hefei, Anhui Applicant before: INNOTRON MEMORY CO.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |