CN107978673B - Semiconductor device, preparation method and electronic device - Google Patents
Semiconductor device, preparation method and electronic device Download PDFInfo
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- CN107978673B CN107978673B CN201610935796.9A CN201610935796A CN107978673B CN 107978673 B CN107978673 B CN 107978673B CN 201610935796 A CN201610935796 A CN 201610935796A CN 107978673 B CN107978673 B CN 107978673B
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
- H10N70/8845—Carbon or carbides
Abstract
The invention provides a semiconductor device, a preparation method and an electronic device. The method comprises the steps of providing a semiconductor substrate, and forming a plurality of laminated structures on the semiconductor substrate, wherein each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially laminated; sequentially forming a first epitaxial substrate layer, a first graphene layer, an insulating layer, a second epitaxial substrate layer, a second graphene layer and a bottom electrode layer on the semiconductor substrate and the multilayer laminated structure; patterning the multilayer laminated structure to form an opening, dividing the multilayer laminated structure into two parts which are spaced from each other and exposing the semiconductor substrate; removing the sacrificial layer exposed in the opening to form a groove between the isolation layers; a layer of top electrode material is deposited to fill the recess and form a top electrode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method and an electronic device.
Background
With the continuous extension and depth of Moore's law, the device size of Silicon-based integrated circuits is getting closer to the physical limit, and the Beyond Silicon (Beyond Silicon) technology is proposed by the international semiconductor technology community, wherein graphene with greater development potential is generated.
Graphene (Graphene) is a two-dimensional crystal composed of carbon atoms on a single-layer honeycomb crystal lattice, the thickness of the single-layer Graphene is about 0.35 nm, and less than ten layers of graphite are regarded as Graphene. Graphene has not only very excellent mechanical properties and thermal stability, but also superconducting electrical properties. The theoretical carrier mobility of graphene can be as high as 2 x 105cm2the/Vs is about 10 times of the carrier mobility of the current silicon material, and has physical properties such as room-temperature quantum hall effect, so that graphene is considered to be a main generation of the new generation instead of siliconFlowing a semiconductor material.
Among them, in a Resistive Random Access Memory (RRAM), a graphene high out-of-plane resistance (out-of-plane resistance) is currently used to reduce an operation current, but the out-of-plane resistance (out-of-plane resistance) requires a higher forming voltage, for example, 6V, which is much higher than a conventional operation voltage, so how to maintain the out-of-plane resistance (out-of-plane resistance) and eliminate the high forming voltage becomes a problem to be solved.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein a plurality of laminated structures are formed on the semiconductor substrate, and each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially laminated;
sequentially forming a first epitaxial substrate layer, a first graphene layer, an insulating layer, a second epitaxial substrate layer, a second graphene layer and a bottom electrode layer on the semiconductor substrate and the multilayer laminated structure;
patterning the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer, and the multilayer stack structure to form an opening, dividing the multilayer stack structure into two parts spaced apart from each other, and exposing the semiconductor substrate;
removing the sacrificial layer exposed in the opening to form a groove between the isolation layers;
a layer of top electrode material is deposited to fill the recess and form a top electrode.
Optionally, the first epitaxial substrate layer comprises a SiC layer;
the second epitaxial substrate layer includes a SiC layer.
Optionally, the insulating layer comprises a metal oxide layer.
Optionally, the step of forming the top electrode further comprises etching the bridged portion of the top electrode in the opening to form top electrodes isolated from each other by the opening.
Optionally, the method further comprises the step of forming a sacrificial material layer on the bottom electrode layer to the top of the bottom electrode layer after forming the bottom electrode.
Optionally, the method further comprises the step of removing the sacrificial material layer after forming the top electrode.
The present invention also provides a semiconductor device comprising a plurality of memory cells, the memory cells comprising:
a semiconductor substrate;
the multilayer laminated structure comprises a top electrode and an isolating layer which are sequentially laminated, and the multilayer laminated structure comprises a first side wall and a second side wall which are oppositely arranged;
a memory structure comprising a first graphene layer, an insulating layer and a second graphene layer sequentially formed on the semiconductor substrate, the top of the multilayer stack structure and the first sidewall;
a bottom electrode located above the second graphene layer.
Optionally, the semiconductor device comprises two memory cells, wherein the top electrodes of the two memory cells are opposite and spaced apart from each other.
Optionally, the insulating layer comprises a metal oxide layer.
Optionally, a first epitaxial substrate layer is formed between the first graphene layer and the insulating layer;
a second epitaxial substrate layer is formed between the second graphene layer and the insulating layer.
Optionally, the first epitaxial substrate layer comprises a SiC layer;
the second epitaxial substrate layer includes a SiC layer.
The invention also provides an electronic device comprising the semiconductor device.
In order to solve the problems of the conventional semiconductor device, the application provides a semiconductor device and a preparation method thereof, in the preparation method, an epitaxial substrate is firstly formed, Graphene grows on the epitaxial substrate, and a RRAM (Graphene-Insulator-Graphene, G-I-G) with a 3D structure is formed, so that adverse effects caused by high-temperature deposition are avoided, and the yield and the performance of the RRAM are further improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a flow chart of a process for fabricating a semiconductor device according to the present invention;
FIG. 2 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 3 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 4 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 5 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 6 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 7 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 8 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 9 illustrates a cross-sectional view of a structure formed at a step associated with one method of fabricating a semiconductor device in an embodiment of the present invention;
FIG. 10 illustrates a cross-sectional view of a structure formed at a step associated with one method of fabricating a semiconductor device, in an embodiment of the present invention;
FIG. 11 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
fig. 12 is a cross-sectional view of a structure formed at a step associated with a method of manufacturing a semiconductor device in an embodiment of the present invention;
fig. 13 is a cross-sectional view of a structure formed at a step associated with a method of manufacturing a semiconductor device in an embodiment of the present invention;
fig. 14 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the existing problems, a method for manufacturing a semiconductor device is provided, which comprises the following steps:
providing a semiconductor substrate, wherein a plurality of laminated structures are formed on the semiconductor substrate, and each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially laminated;
sequentially forming a first epitaxial substrate layer, a first graphene layer, an insulating layer, a second epitaxial substrate layer, a second graphene layer and a bottom electrode layer on the semiconductor substrate and the multilayer laminated structure;
patterning the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer, and the multilayer stack structure to form an opening, dividing the multilayer stack structure into two parts spaced apart from each other, and exposing the semiconductor substrate;
removing the sacrificial layer exposed in the opening to form a groove between the isolation layers;
a layer of top electrode material is deposited to fill the recess and form a top electrode.
The graphene is the thinnest and hardest nano-material known to the world, is almost completely transparent, and only absorbs 2.3% of light; the thermal conductivity coefficient is high 5300W/m.K, higher than that of carbon nano tube and diamond, and its electron mobility is over 15000cm at normal temp2V.s, higher than that of carbon nanotube or silicon crystal,the resistivity is only about 1 omega-m, is lower than copper or silver, and is the material with the minimum resistivity in the world. Because of its extremely low resistivity, the rate of electron transfer is extremely fast.
Graphene is a carbon with a two-dimensional crystal structure, and has good prospects in remarkable electron mobility and other unique nanoelectronic and photonic functions.
Wherein the first epitaxial substrate layer comprises a SiC layer;
the second epitaxial substrate layer includes a SiC layer.
In the invention, the graphene layer can be well extended on the SiC layer without needing too high voltage.
The invention provides a semiconductor device, which comprises a plurality of memory cells, wherein each memory cell comprises:
a semiconductor substrate;
the multilayer laminated structure comprises a top electrode and an isolating layer which are sequentially laminated, and the multilayer laminated structure comprises a first side wall and a second side wall which are oppositely arranged;
a memory structure comprising a first graphene layer, an insulating layer and a second graphene layer sequentially formed on the semiconductor substrate, the top of the multilayer stack structure and the first sidewall;
a bottom electrode located above the second graphene layer.
Optionally, the semiconductor device includes two memory cells, wherein the top electrodes of the two memory cells are opposite and spaced apart from each other.
In order to solve the problems of the conventional semiconductor device, the application provides a semiconductor device and a preparation method thereof, in the preparation method, an epitaxial substrate is firstly formed, Graphene grows on the epitaxial substrate, and a RRAM (Graphene-Insulator-Graphene, G-I-G) with a 3D structure is formed, so that adverse effects caused by high-temperature deposition are avoided, and the yield and the performance of the RRAM are further improved.
Example one
Referring now to fig. 1-13, wherein fig. 1 illustrates a process flow diagram for fabricating a semiconductor device in accordance with the present invention; FIG. 2 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 3 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 4 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 5 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 6 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 7 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 8 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 9 illustrates a cross-sectional view of a structure formed at a step associated with one method of fabricating a semiconductor device in an embodiment of the present invention; FIG. 10 illustrates a cross-sectional view of a structure formed at a step associated with one method of fabricating a semiconductor device, in an embodiment of the present invention; FIG. 11 illustrates a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in an embodiment of the present invention; fig. 12 is a cross-sectional view of a structure formed at a step associated with a method of manufacturing a semiconductor device in an embodiment of the present invention; fig. 13 is a cross-sectional view of a structure formed at a step associated with a method of manufacturing a semiconductor device in an embodiment of the present invention.
The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:
step S1: providing a semiconductor substrate, wherein a plurality of laminated structures are formed on the semiconductor substrate, and each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially laminated;
step S2: sequentially forming a first epitaxial substrate layer, a first graphene layer, an insulating layer, a second epitaxial substrate layer, a second graphene layer and a bottom electrode layer on the semiconductor substrate and the multilayer laminated structure;
step S3: patterning the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer, and the multilayer stack structure to form an opening, dividing the multilayer stack structure into two parts spaced apart from each other, and exposing the semiconductor substrate;
step S4: removing the sacrificial layer exposed in the opening to form a groove between the isolation layers;
step S5: a layer of top electrode material is deposited to fill the recess and form a top electrode.
Next, a detailed description will be given of a specific embodiment of the method for manufacturing a semiconductor device of the present invention.
First, step one is performed to provide a semiconductor substrate 201 on which a multilayer stack structure in which a sacrificial layer 202 and an isolation layer 203 are sequentially stacked is formed.
Specifically, as shown in fig. 2, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
Wherein, the sacrificial layer can be selected from materials with larger etching selection ratio with the isolation layer.
For example, in this embodiment, the sacrificial layer is SiN.
Among them, the isolation layer may be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer such as a layer containing polyvinylphenol, polyimide, siloxane, or the like. Further, polyvinyl phenol, polyimide, or siloxane can be effectively formed by a droplet discharge method, printing, or spin coating method. Siloxanes can be classified according to their structure into silica glass, alkyl siloxane polymers, alkyl silsesquioxane polymers, silsesquioxane hydride polymers, alkyl silsesquioxane hydride polymers, and the like.
In addition, the isolation layer 203 is made of oxide and may be formed by various deposition methods commonly used in the art.
In this step, the sacrificial layers 202 and the isolation layers 203 are alternately deposited, and the present embodiment forms three layers of the sacrificial layers 202 and three layers of the isolation layers 203.
Wherein the sacrificial layer 202 is first formed over the semiconductor substrate.
After a stacked structure composed of a sacrificial layer and an isolation layer is sequentially stacked on the semiconductor substrate, the stacked structure is then patterned to form a square multi-layered stacked structure.
Wherein the multi-layered stacked structure is a cubic structure, such as a rectangular parallelepiped, etc., as shown in fig. 3.
And step two, sequentially forming a first epitaxial substrate layer 204, a first graphene layer 205, an insulating layer 206, a second epitaxial substrate layer 207, a second graphene layer 208 and a bottom electrode layer 209 on the semiconductor substrate and the multilayer laminated structure.
Specifically, as shown in fig. 4, to avoid using a high pressure deposition method in the present application, a first epitaxial substrate layer 204 is first formed on the semiconductor substrate and the multilayer stack structure for epitaxial graphene layers.
Wherein the first epitaxial substrate layer comprises a SiC layer;
in the invention, the graphene layer can be well extended on the SiC layer without needing too high voltage.
The graphene is the thinnest and hardest nano-material known to the world, is almost completely transparent, and only absorbs 2.3% of light; the thermal conductivity coefficient is high 5300W/m.K, higher than that of carbon nano tube and diamond, and its electron mobility is over 15000cm at normal temp2The resistivity of the material is only about 1 omega.m, and is lower than that of copper or silver, so that the material with the minimum resistivity is the world. Because of its extremely low resistivity, the rate of electron transfer is extremely fast.
Graphene is a carbon with a two-dimensional crystal structure, and has good prospects in remarkable electron mobility and other unique nanoelectronic and photonic functions.
The growth method of the first graphene layer may be an epitaxial growth method.
Illustratively, the epitaxial growth method specifically includes the steps of:
cleaning a semiconductor substrate in acetone, ethanol and deionized water in sequence, taking the substrate out of the deionized water every time for 10min, and drying the substrate by using high-purity nitrogen (99.9999%); placing the semiconductor substrate into a CVD reaction chamber, and vacuumizing to 10%-5Torr, to remove residual gas in the reaction chamber; introducing high-purity Ar into the reaction chamber, keeping the temperature at 150 ℃ for 10min, and then vacuumizing to 10 DEG C-5And Torr, discharging adsorbed gas on the surface of the substrate.
Introducing H into the reaction chamber2Performing substrate surface pretreatment, wherein the gas flow is 1sccm, the vacuum degree of a reaction chamber is 0.1Torr, the substrate temperature is 1000 ℃, and the treatment time is 1 min; introducing H into the reaction chamber2And CH4Hold H2And CH4The flow ratio of (A) to (B) is 10: 1, H2Flow rate 20sccm, CH4The flow rate is 2sccm, the air pressure is maintained at 0.1atm (standard atmospheric pressure), the temperature is 1200 ℃, the temperature rise time is 20min, and the holding time is 50 min; retention of H2And CH4The flow and the air pressure are unchanged, and the temperature is naturally reduced to finish the growth of the graphene layer.
Cooling to below 100 deg.C, and closing CH4、H2Ar is introduced, the reaction chamber is opened, and the sample is taken out as shown in FIG. 5.
The step of forming an insulating layer may be further included after the first graphene layer is formed, wherein the insulating layer may be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer such as a layer including polyvinyl phenol, polyimide, siloxane, or the like. Further, polyvinyl phenol, polyimide, or siloxane can be effectively formed by a droplet discharge method, printing, or spin coating method. Siloxanes can be classified according to their structure into silica glass, alkyl siloxane polymers, alkyl silsesquioxane polymers, silsesquioxane hydride polymers, alkyl silsesquioxane hydride polymers, and the like.
In addition, the insulating layer is made of oxide and may be formed by various deposition methods commonly used in the art, as shown in fig. 6.
Then, a second epitaxial substrate layer 207 and a second graphene layer 208 are sequentially formed, and the forming method and the selected material of the second epitaxial substrate layer 207 and the second graphene layer 208 may be the same as those of the first epitaxial substrate layer and the first graphene layer, as shown in fig. 7 to 8.
And then forming a bottom electrode on the second graphene layer, wherein the bottom electrode can be made of a metal material, such as copper.
And step three, forming a sacrificial material layer on the bottom electrode layer to the top of the bottom electrode layer.
Specifically, as shown in fig. 9, the sacrificial material layer is made of a fluorine-free carbon-containing material (NFC).
The step of forming the layer of barrier material may comprise: first, a spacer material layer 210 is deposited on top of the second graphene layer to cover the second graphene layer and fill the gaps between the stacked multilayer structures, and then the spacer material layer 210 is planarized to the top of the bottom electrode until the bottom electrode is exposed.
And fourthly, patterning the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer and the multilayer laminated structure to form an opening, and dividing the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer and the multilayer laminated structure into two parts which are mutually spaced and expose the semiconductor substrate.
Specifically, as shown in fig. 10, the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer, and the multilayer stack structure are patterned in this step to form an opening at a middle position of the multilayer stack structure.
And step five, removing the sacrificial layer exposed in the opening to form a groove between the isolation layers.
Specifically, as shown in fig. 11, sidewalls of the sacrificial layer and the isolation layer in the multilayer stack structure are exposed after the opening is formed, and then the sacrificial layer is removed through the opening using wet etching to form a groove between the isolation layers.
The sacrificial layer may be removed using hot phosphoric acid in this step, but is not limited to this example.
Step six is performed to deposit a top electrode material layer to fill the recess and form the top electrode 211.
Specifically, as shown in fig. 12, in this step, an electrode material layer is first deposited to fill the groove formed after removing the sacrificial layer, and a multi-layered stack structure having the same shape as that before removing the sacrificial layer is formed after filling the groove to form the top electrode 211.
In this step the electrode material layer does not completely fill the opening, but only the top electrode is formed on the sidewalls, so that the top electrodes on both sides of the opening are isolated from each other.
The step of forming the top electrode further includes etching portions of the top electrode bridging in the openings to form top electrodes isolated from each other by the openings.
For example, if a bridge is formed on the semiconductor substrate at the bottom of the opening, the bottom of the opening is etched to break the bridge to form top electrodes that are isolated from each other by the opening.
The method further includes the step of forming an interlevel dielectric layer 212 and an interconnect layer located thereover.
Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. The method may further include the step of forming a transistor and other related steps, which are not described in detail herein. Besides the above steps, the preparation method of this embodiment may further include other steps in the above steps or between different steps, and these steps may be implemented by various processes in the current process, and are not described herein again.
In order to solve the problems of the conventional semiconductor device, the application provides a semiconductor device and a preparation method thereof, in the preparation method, an epitaxial substrate is firstly formed, Graphene grows on the epitaxial substrate, and a RRAM (Graphene-Insulator-Graphene, G-I-G) with a 3D structure is formed, so that adverse effects caused by high-temperature deposition are avoided, and the yield and the performance of the RRAM are further improved.
Example two
The present invention also provides a semiconductor device comprising a plurality of memory cells, the memory cells comprising:
a semiconductor substrate;
the multilayer laminated structure comprises a top electrode and an isolating layer which are sequentially laminated, and the multilayer laminated structure comprises a first side wall and a second side wall which are oppositely arranged;
a memory structure comprising a first graphene layer, an insulating layer and a second graphene layer sequentially formed on the semiconductor substrate, the top of the multilayer stack structure and the first sidewall;
a bottom electrode located above the second graphene layer.
Wherein the semiconductor device comprises two memory cells, wherein the top electrodes of the memory cells on the two sides are opposite and are arranged at intervals.
Wherein the insulating layer comprises a metal oxide layer.
A first epitaxial substrate layer is formed between the first graphene layer and the insulating layer;
a second epitaxial substrate layer is formed between the second graphene layer and the insulating layer.
Wherein the first epitaxial substrate layer comprises a SiC layer;
the second epitaxial substrate layer includes a SiC layer.
First, a multilayer stack structure in which a sacrificial layer 202 and an isolation layer 203 are sequentially stacked is formed on the semiconductor substrate.
The semiconductor substrate (not shown in the figures) may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In the invention, the graphene layer can be well extended on the SiC layer without needing too high voltage.
The graphene is the thinnest and hardest nano-material known to the world, is almost completely transparent, and only absorbs 2.3% of light; the thermal conductivity coefficient is high 5300W/m.K, higher than that of carbon nano tube and diamond, and its electron mobility is over 15000cm at normal temp2The resistivity of the material is only about 1 omega.m, and is lower than that of copper or silver, so that the material with the minimum resistivity is the world. The resistivity is extremely low, and the speed of electron migration is extremely high, so that the performance of the photoelectric detector adopting graphene is further improved.
Graphene is a carbon with a two-dimensional crystal structure, and has good prospects in remarkable electron mobility and other unique nanoelectronic and photonic functions.
The application provides a semiconductor device in order to solve the problem that present semiconductor device exists semiconductor device includes epitaxial substrate the Graphene grows on epitaxial substrate to form the RRAM of the 3D structure of graphite alkene-insulating layer-graphite alkene (G-I-G), avoided the adverse effect that high temperature deposition brought, further improved RRAM's yield and performance.
EXAMPLE III
Another embodiment of the present invention provides an electronic device, which includes a semiconductor device, wherein the semiconductor device is the semiconductor device in the second embodiment or the semiconductor device manufactured by the method of manufacturing the semiconductor device in the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.
The electronic device also has the advantages described above, since the semiconductor device included has higher performance.
Among them, fig. 14 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the semiconductor device or the semiconductor device manufactured by the manufacturing method of the semiconductor device according to the embodiment one, and the semiconductor device comprises a semiconductor substrate; the multilayer laminated structure comprises a top electrode and an isolating layer which are sequentially laminated, and the multilayer laminated structure comprises a first side wall and a second side wall which are opposite; a memory structure comprising a first graphene layer, an insulating layer and a second graphene layer sequentially formed on the semiconductor substrate, the top of the multilayer stack structure and the first sidewall; a bottom electrode located above the second graphene layer. The semiconductor device comprises an epitaxial substrate, Graphene grows on the epitaxial substrate, and the RRAM of a 3D structure of Graphene-insulating layer-Graphene (G-I-G) is formed, so that adverse effects caused by high-temperature deposition are avoided, and the yield and the performance of the RRAM are further improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein a multilayer laminated structure of sacrificial layers and isolating layers which are alternately laminated is formed on the semiconductor substrate;
sequentially forming a first epitaxial substrate layer, a first graphene layer, an insulating layer, a second epitaxial substrate layer, a second graphene layer and a bottom electrode layer on the surface of the semiconductor substrate, which is not covered by the multilayer laminated structure, and on the top and the side wall of the multilayer laminated structure, wherein the first graphene layer and the second graphene layer are formed through epitaxial growth;
patterning the bottom electrode layer, the second graphene layer, the second epitaxial substrate layer, the insulating layer, the first graphene layer, the first epitaxial substrate layer, and the multilayer stack structure to form an opening, dividing the multilayer stack structure into two parts spaced apart from each other, and exposing the semiconductor substrate;
removing the sacrificial layer exposed in the opening to form a groove between the isolation layers;
a layer of top electrode material is deposited to fill the recess and form a top electrode.
2. The method of claim 1, wherein the first epitaxial substrate layer comprises a SiC layer;
the second epitaxial substrate layer includes a SiC layer.
3. The method of claim 1 further including etching portions of the top electrode bridging in the openings to form top electrodes isolated from each other by the openings in the step of forming the top electrodes.
4. The method of claim 1, further comprising the step of forming a layer of sacrificial material on the bottom electrode layer to the top of the bottom electrode layer after forming the bottom electrode.
5. A semiconductor device, comprising a plurality of memory cells, the memory cells comprising:
a semiconductor substrate;
the multilayer laminated structure comprises a top electrode and an isolating layer which are sequentially laminated, and the multilayer laminated structure comprises a first side wall and a second side wall which are oppositely arranged;
a storage structure comprising a 3D structure of a first epitaxial substrate layer, a first graphene layer, an insulating layer, a second epitaxial substrate layer and a second graphene layer formed in sequence on the semiconductor substrate, the top of the multilayer stack structure and the first sidewall, wherein the first graphene layer and the second graphene layer are formed by epitaxial growth;
a bottom electrode located above the second graphene layer.
6. The semiconductor device according to claim 5, wherein the semiconductor device comprises two of the memory cells, wherein top electrodes of the two memory cells are opposite and spaced apart from each other.
7. The semiconductor device according to claim 5, wherein the insulating layer comprises a metal oxide layer.
8. The semiconductor device of claim 5, wherein the first epitaxial substrate layer comprises a SiC layer;
the second epitaxial substrate layer includes a SiC layer.
9. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 5 to 8.
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| US20110121366A1 (en) * | 2009-04-14 | 2011-05-26 | NuPGA Corporation | System comprising a semiconductor device and structure |
| CN104810476A (en) * | 2015-05-07 | 2015-07-29 | 中国科学院微电子研究所 | Non-volatile resistive switching memory device and manufacturing method thereof |
| TWI549227B (en) * | 2015-05-20 | 2016-09-11 | 旺宏電子股份有限公司 | Memory device and method for fabricating the same |
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| US20110121366A1 (en) * | 2009-04-14 | 2011-05-26 | NuPGA Corporation | System comprising a semiconductor device and structure |
| CN104810476A (en) * | 2015-05-07 | 2015-07-29 | 中国科学院微电子研究所 | Non-volatile resistive switching memory device and manufacturing method thereof |
| TWI549227B (en) * | 2015-05-20 | 2016-09-11 | 旺宏電子股份有限公司 | Memory device and method for fabricating the same |
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