CN107978276A - Level circuit, scanner driver and display device - Google Patents
Level circuit, scanner driver and display device Download PDFInfo
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- CN107978276A CN107978276A CN201810054349.1A CN201810054349A CN107978276A CN 107978276 A CN107978276 A CN 107978276A CN 201810054349 A CN201810054349 A CN 201810054349A CN 107978276 A CN107978276 A CN 107978276A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of level circuit, scanner driver and display device, the level circuit has small number of transistor and the scanning signal of required waveform can be exported using only the first clock signal and second clock signal, and circuit is simple, and stability is high；And power consumption can be reduced to avoid the output of the second clock signal and the first supply voltage at the same time with high level.The scanner driver and display device of the present invention, power consumption is relatively low, and performance is higher.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of level circuit, scanner driver and display device.
Background technology
In recent years, the display device of numerous types, such as liquid crystal display device, plasma display dress be have developed both at home and abroad
Put, electrowetting display device, electrophoretic display apparatus, organic light-emitting display device etc..Wherein organic light-emitting display device utilizes electricity
Sub- hole sends the light of specific wavelength, to show image, has quick response to compound in certain material, low in energy consumption, gently
It is thin, the advantages that colour gamut is wide.Organic light-emitting display device includes：Pixel region, data driver, scanner driver, emission control are driven
Dynamic device etc., wherein, data driver is used to data-signal being supplied to a plurality of data cable arranged along column direction, scanner driver
For scanning signal to be supplied to a plurality of scan line arranged along line direction, emission control driver is used to be swept according at least one
Retouch signal and be supplied to launch-control line to produce an emissioning controling signal, pixel region includes being connected to scan line, data cable, hair
Multiple pixels of control line are penetrated, the pixel region realizes phase according to the data-signal of reception, scanning signal and emissioning controling signal
The pixel light emission answered is to show image.Wherein, scanner driver includes multiple grades of circuits for being connected to multi-strip scanning line, Duo Geji
Scanning signal is supplied to the multi-strip scanning line for being connected to the multiple level circuit by circuit, with corresponding to being supplied to the multiple level
Signal.
It is found by the applicant that power consumption caused by current scanner driver considerably increases the overall power of display device.
The content of the invention
It is an object of the invention to provide a kind of level circuit, scanner driver and display device, power consumption can be reduced.
In order to solve the above technical problems, the present invention provides a kind of level circuit, including：
Output module with first node, section point and signal output part, for according to be applied to first node and
The voltage of section point, signal output part is supplied to by the voltage of the voltage of the first power supply or second clock signal；
Input module with the first clock end, second clock end, the first power end and the first signal input part, it is described
First clock end is used to receive the first clock signal, and the second clock end is used to receive second clock signal, first electricity
Source be used for access the first power supply, first signal input part be used for receive scanning commencing signal or previous stage circuit it is defeated
Go out signal；The input module be used for first clock signal, second clock signal control under by first signal
Input terminal received signal writes；
With second source end and connect the voltage control module of the input module, first node and section point, institute
State second source end to be used to access second source, the voltage control module is used under the control of first clock signal will
The voltage of first power supply or the voltage of second source are provided to the first node, and will under the voltage control of second source
The voltage of the first signal input part received signal is provided to section point.
Optionally, the input module include being sequentially arranged in first signal input part and first power end it
Between the first transistor, second transistor, third transistor, the grid of the first transistor is connected to first clock
End, the grid of the second transistor are connected to the second clock end, and the grid of the third transistor is connected to described the
One node.
Optionally, the voltage control module includes pull-up control unit, drop-down control unit and partial pressure control unit；
The pull-up control unit is connected between first power end and the first node, for being inputted in first signal
Hold and the voltage of the first power supply is supplied to first node under the control of received signal；The drop-down control unit is connected to described
Between first node and second source end, and the control terminal of the drop-down control unit is connected to first clock end, is used for
The voltage of second source is supplied to first node under the control of first clock signal；The partial pressure control unit series connection
Between the input module and the output module, and the node that the partial pressure control unit is connected with the input module is also
The control terminal of the pull-up control unit is connected to, the control terminal of the partial pressure control unit is connected to the second source end,
The partial pressure control unit is used for the voltage of the first signal input part received signal under the control of the second source
The section point is provided to, is additionally operable to share between the pull-up control unit and the section point and the input mould
The voltage on circuit between block and the section point, to protect the pull-up control unit and the input module
Optionally, the pull-up control unit includes the 4th transistor, and the drop-down control unit includes the 5th transistor,
The partial pressure control unit includes the 8th transistor, wherein, the grid of the 4th transistor is the pull-up control unit
Control terminal, is connected to the first pole of the 8th transistor, and the first pole of the 4th transistor is connected to first power supply
End, the second pole of the 4th transistor is connected to the first node；The grid of 5th transistor is as the drop-down
The control terminal of control unit, is connected to first clock end, and the first pole of the 5th transistor is connected to the first segment
Point, the second pole of the 5th transistor are connected to the second source end；The grid of 8th transistor is the partial pressure
The control terminal of control unit, is connected to the second source end, and the first pole of the 8th transistor is additionally coupled to the input
Module, the second pole of the 8th transistor are connected to the section point.
Optionally, the output module includes the first output unit and the second output unit, and first output unit connects
The first node, the first power end and signal output part are connect, for electric by described first under the control of the first node
The voltage output in source is to the signal output part；Second output unit connects section point, second clock end and the letter
Number output terminal, under the control of the section point by the second clock signal output to the signal output part.
Optionally, first output unit includes the first charging capacitor and the 6th transistor, the 6th transistor
One end of grid and first charging capacitor is connected to the first node, the first pole of the 6th transistor and described
The other end of first charging capacitor is connected to first power end, and the second pole of the 6th transistor is connected to the letter
Number output terminal；Second output unit includes the second charging capacitor and the 7th transistor, the grid of the 7th transistor and
One end of second charging capacitor is connected to the section point, and the first pole of the 7th transistor and described first are filled
The other end of capacitance is connected to the signal output part, and the second pole of the 7th transistor is connected to the second clock
End.
Optionally, the output module further includes speed expanded unit and/or filter unit, the speed expanded unit with
Second output unit is in parallel, for improving the transmission speed for the signal for being transmitted to the signal output part；The filtering is single
First one end is connected at the node of the first output unit and the second output unit connection, and one end is connected to the signal output
End, for being transmitted to the signal after being filtered to the signal of first output unit or the second output unit signal output
Output terminal.
Optionally, the speed expanded unit includes at least one and extended transistor of the 7th coupled in parallel,
The grid of each extended transistor is connected to the second clock end, and the first pole of each extended transistor is connected to described
Signal output part, the second pole of each extended transistor are connected to the section point；The filter unit includes filtered electrical
Hold and protective resistance, one end of the protective resistance and one end of the filter capacitor are connected to the signal output part, institute
The other end for stating protective resistance is connected at the node of the first output unit and the second output unit connection, the filtered electrical
The other end ground connection of appearance.
Optionally, the input module further includes first control signal end, second control signal end, secondary signal input terminal
With bi-directional drive unit, the bi-directional drive unit includes the 9th transistor and the tenth transistor, the 9th transistor connection
Between the first signal input part and the second pole of the first transistor, the grid of the 9th transistor is connected to first control
Signal end processed, the 9th transistor are turned on when the first control signal end provides first control signal, and the described tenth is brilliant
Body pipe is connected between secondary signal input terminal and the second pole of the first transistor, and the grid of the tenth transistor is connected to institute
Second control signal end is stated, the tenth transistor is turned on when the second control signal end provides second control signal, institute
State the first signal input part to receive the output signal of previous stage circuit or start scanning signal, secondary signal input terminal receives latter
The output signal of level circuit starts scanning signal.
The present invention also provides a kind of scanner driver, include multiple one of above-mentioned level circuits of cascade, each level circuit
Signal output part be connected in corresponding scan line, and the level circuit of the first order the first signal input part receive start to scan
Signal, the first signal input part of remaining grade of circuit receive the output signal of the signal output part of previous stage circuit.
The present invention also provides a kind of display device, including above-mentioned scanner driver.
Compared with prior art, technical scheme has the advantages that：
1st, the normal output of the output signal of waveform needed for can realizing；
2nd, the voltage of second clock signal and the first power supply is alternatively provided to signal output part, therefore when second
When the voltage of clock signal and the first power supply is high level, one of them can be only exported, advantageously reduces power consumption；
3rd, only have drop-down control unit in voltage control module and be connected to the first clock end, advantageously reduce the first clock end
The load of itself.
Brief description of the drawings
Figure 1A is the structure diagram of the level circuit of one embodiment of the invention；
Figure 1B is the sequence diagram of the level circuit shown in Fig. 1；
Fig. 2 is the structure diagram of the scanner driver of one embodiment of the invention；
Fig. 3 is the structure diagram of the display device of one embodiment of the invention；
Fig. 4 is the structure diagram of the level circuit of another embodiment of the present invention；
Fig. 5 is the structure diagram of the scanner driver of another embodiment of the present invention.
Embodiment
Level circuit proposed by the present invention, scanner driver and display device are made further specifically below in conjunction with attached drawing
It is bright.It should be noted that attached drawing uses using very simplified form and non-accurate ratio, only to conveniently, lucidly
The purpose of the embodiment of the present invention is aided in illustrating, a part for corresponding construction is only indicated in each attached drawing, and actual product can
Need to make corresponding change according to actual displayed.In addition, show that an element is connected to another element it will be further understood that working as
When upper, which can be directly connected to another described element, or can connect indirectly via one or more add ons
It is connected to another described element.In the accompanying drawings, for brevity and clarity, it is convenient to omit some add ons.Entirely saying
In bright book, identical label represents identical element.
A is please referred to Fig.1, the present invention provides a kind of level circuit, including input module 11, voltage control module 12 and output mould
Block 13.
Input module 11 has the first clock end SCK1, second clock end SCK2, the first power end VGH and the first signal
Input terminal SIN, the first clock end SCK1 are used to receiving the first clock signal, and the second clock end SCK2 is used to receiving the
Two clock signals, the first power end VGH are used to access the first power supply (high level), and the first signal input part SIN is used
In the output signal for receiving scanning commencing signal or previous stage circuit.The input module 11 is used to believe in first clock
Number, the first signal input part SIN received signals are exported under the control of second clock signal., will in order to facilitate understanding
Port with and its transmission signal title it is unified, i.e. the first clock signal that the first clock end SCK1 is transmitted is denoted as SCK1, the
The second clock signal of two clock end SCK2 transmission is denoted as SCK2, and the signal of the first signal input part SIN transmission is denoted as SIN, institute
The voltage signal (or being high level signal) for stating the first power supply of the first power end VGH transmission is denoted as VGH.Institute in the present embodiment
State input module 11 includes being sequentially arranged between the first signal input part SIN and the first power end VGH first
Transistor M1, second transistor M2, the grid of third transistor M3, the first transistor M1 are connected to first clock end
The second pole (drain electrode) of the first pole (source electrode) connection second transistor M2 of SCK1, the first transistor M1, described first is brilliant
The second pole (drain electrode) of body pipe M1 connects the first signal input part SIN, under the control of the first clock signal SCK1
On or off, to write the SIN signals of low level or high level, and then makes SIN signals be provided to the second of output module 13
Node N2, and the main function of the first transistor M1 is the low level for exporting SIN signals；The grid of the second transistor M2 connects
It is connected to the second clock end SCK2, the first pole of the first pole (source electrode) connection third transistor M3 of the second transistor M2
(source electrode), for the on or off under the control of second clock signal SCK2, to control third transistor M3 to be controlled with voltage
The connection of the partial pressure control unit 123 (i.e. the first pole of the 8th transistor M8) of module 12, that is, control third transistor M3 and the
The connection of two node N2；The grid of third transistor M3 is connected to the first node N1 of the output module 13, third transistor
The second pole (drain electrode) of M3 connects the first power end VGH, and the first power supply is controlled for the voltage according to first node N1
Hold the connection of VGH and second transistor M2.Preferably, the first transistor M1 is double-gated transistor, to reduce transistor leakage.Institute
The first clock signal SCK1 and second clock signal SCK2 are stated with the identical period and with nonoverlapping phase, can be
It is provided in different leveled time sections as low level signal, i.e. the first clock signal SCK1, second clock signal SCK2
Waveform has the phase postponed successively.
The voltage control module 12 includes pull-up control unit 121, drop-down control unit 122 and partial pressure control unit
123.In the present embodiment, the pull-up control unit 121 includes being connected to the first power end VGH and the first node N1
Between the 4th transistor M4, the drop-down control unit include be connected to the first node N1 and second source end VGL it
Between the 5th transistor M5, the partial pressure control unit 123 include be connected on the input module 11 and the output module 13
Between the 8th transistor M8.Specifically, the grid of the 4th transistor M4 is the control of the pull-up control unit 121
End, is connected to the first pole (source electrode) of described point of the 8th transistor M8, the first pole (source electrode) connection of the 4th transistor M4
To the first power end VGH, the second pole (drain electrode) of the 4th transistor M4 is connected to the first node N1, and described the
Four transistor M4 are used to be supplied to the voltage VGH of the first power supply under the control of the SIN signals write through the first transistor M1
First node N1；Control terminal of the grid of the 5th transistor M5 as the drop-down control unit 122, is connected to described
The first pole (source electrode) of one clock end SCK1, the 5th transistor M5 is connected to the first node N1, the 5th crystal
The second pole (drain electrode) of pipe M5 is connected to the second source end VGL, and the 5th transistor M5 is used in first clock
The voltage VGL of second source is supplied to first node N1 under the control of signal SCK1；The grid of the 8th transistor M8 is
The control terminal of the partial pressure control unit 123, is connected to the second source end VGL, the first pole of the 8th transistor M8
(source electrode) is connected to the connecting node of the first transistor M1 and second transistor M2 in the input module 11, i.e. first crystal
The position that the first pole of pipe M1 is connected with the second pole of second transistor M2, that is to say, that the first pole of the 8th transistor M8 can
To be connected to the second pole of the first pole of the first transistor M1 and/or second transistor M2, the second of the 8th transistor M8
Pole (drain electrode) is connected to the section point N2, and the 8th transistor M8 is used for the control in the voltage VGL of the second source
The voltage of the first signal input part SIN received signals SIN is provided to the section point N2 under system, is additionally operable to point
Pressure, by high pressure (for for example negative 18.5V high pressures) partition the second output unit 132 of output module 13 the 7th transistor
In the area of grid of M7, the breakdown risk of the first transistor M1, the 4th transistor M4 is reduced, i.e. the 8th transistor M8 is additionally operable to
Share between the grid (i.e. the control terminal of pull-up control unit 121) of the 4th transistor M4 and the section point N2 and
The voltage on circuit between the input module 11 and the section point N2, to protect 121 He of pull-up control unit
The input module 11.In the present embodiment, breadth length ratio (W/L) design of M2 to M5 is close, meets switching function, the width of M8
Long (i.e. bigger than M2 to M5) more relatively large than (W/L), to meet the second charging capacitor quick charge in output module 13
It is required that.The first pole of M4 connects the first power end VGH, and is not connected to the first clock end SCK1, advantageously reduces the first clock end
The loads of SCK1 in itself, and then advantageously reduce the power consumption of circuit entirety.
Output module 13 has first node N1, section point N2 and signal output part OUT, and first is applied to for basis
The voltage of node N1 and section point N2, letter is supplied to by the voltage of the voltage VGH of the first power supply or second clock signal SCK2
Number output terminal OUT, the output module 13 include the first output unit 131, the second output unit 132, speed expanded unit 133
With filter unit 134, wherein, first output unit 131 connects the first node N1 (being directly connected to), the first power end
VGH (being directly connected to) and signal output part OUT (being indirectly connected with), described in being incited somebody to action under the control of the voltage of the first node N1
The voltage VGH of first power supply is exported to the signal output part OUT；Second output unit 122 connects the section point
N2 (being directly connected to), second clock end SCK2 (being directly connected to) and signal output part OUT (being indirectly connected with), for described second
The second clock signal SCK2 is exported to the signal output part OUT under the control of node N2；The speed expanded unit
133 is in parallel with second output unit 132, for improving the transmission speed for the signal for being transmitted to the signal output part OUT；
Described 134 one end of filter unit is connected at the node of 131 and second output unit 132 of the first output unit connection, and one
End is connected to the signal output part OUT, for 131 or second output unit of the first output unit, 132 signal output
Signal be filtered after be transmitted to the signal output part OUT.In the present embodiment, the speed expanded unit 133 includes protecting
Resistance R1 and filter capacitor C3 is protected, one end of the protective resistance R1 and one end of the filter capacitor C3 are connected to the letter
The other end of number output terminal OUT, the protective resistance R1 are connected to 131 and second output unit 132 of the first output unit
At the node of connection, the other end ground connection of the filter capacitor C3, the protective resistance R1 is used to protect first output single
The output voltage of 131 or second output unit 132 of member avoids output voltage is excessive from causing rear stage circuit to burn in given threshold
Ruin, the filter capacitor can be filtered place to the output voltage of 131 or second output unit 132 of the first output unit
Reason, filtering interference signals, ensure to export the accuracy of signal.First output unit 131 include the first charging capacitor C1 and
One end of 6th transistor M6, the grid of the 6th transistor M6 and the first charging capacitor C1 are connected to described first
The other end of node N1, the first pole (source electrode) of the 6th transistor M6 and the first charging capacitor C1 are connected to described
The second pole (drain electrode) of first power end VGH, the 6th transistor M6 is connected to the other end of the protective resistance R1, described
First output unit 131 be used for the first node N1 voltage control under by the voltage VGH of first power supply export to
The signal output part OUT；Second output unit 132 includes the second charging capacitor C2 and the 7th transistor M7, and described
One end of the grid of seven transistor M7 and the second charging capacitor C2 are connected to the section point N2, the 7th crystal
The other end of the first pole (source electrode) of M7 pipes and the first charging capacitor C1 are connected to the signal output part OUT, described
The second pole (drain electrode) of 7th transistor M7 is connected to the second clock end SCK2, and second output unit 132 is used for
The voltage SCK2 of the second clock signal SCK2 is exported to the signal output under the voltage control of the section point N2
Hold OUT；The speed expanded unit 133 includes at least one extended transistor MDx in parallel with the 7th transistor M7, example
As shown in the MD1 to MD3 in Figure 1A, the grid of each extended transistor MDx is connected to the second clock end SCK2, each
The first pole (source electrode) of extended transistor MDx is connected to the first pole (source electrode) of the 7th transistor M7, and each extension is brilliant
The second pole of body pipe MDx is connected to the section point N2, and extended transistor MDx in parallel can extend breadth length ratio (W/L),
The charging rate of the second capacitance C2 is improved, and then improves signaling rate.
It should be noted that each transistor in above-described embodiment can be N-type switching transistor or p-type
Switching transistor, N-type switching transistor are turned on when its grid connects high level, are ended when connecing low level, and the p-type switchs crystal
Pipe is turned on when its grid connects low level, is ended when connecing high level, and each transistor can be thin film transistor (TFT) (TFT),
It can be metal oxide semiconductor field effect tube (MOS), be not limited thereto, the source electrode of these switching transistors and drain electrode can
With the difference according to switching transistor type and input signal, its function can be exchanged, do not distinguished specifically herein.In addition, work as
When the breadth length ratio of 7th transistor M7 is sufficiently large, it is convenient to omit the setting of speed expanded unit 133, similarly, when the of input
One clock signal SCK1, second clock signal SCK2, SIN signal and the voltage VGH of the first power supply and the voltage of second source
When VGL is sufficiently stable, the setting of filter unit 134 can also be omitted.
The sequence diagram of input and output shown in 1B below in conjunction with the accompanying drawings, carries out the course of work of the level circuit shown in Figure 1A
Detailed description.Wherein, the voltage VGH of the first power supply of the first power end VGH accesses is high level, and second source end VGL connects
The voltage VGL of the second source entered is low level, and all transistors are p-type switching transistor.
First, during the t1 periods, there is the output signal of low level previous stage circuit or start scanning signal SIN
The second pole (source electrode) of the first transistor M1 is supplied to, there is low level first clock signal SCK1 to be provided to first crystal
The grid of the grid of pipe M1 and the 5th transistor M5, the second clock signal SCK2 with high level are fed into second transistor
The second pole (drain electrode) of the grid of M2 and the 7th transistor M7, the voltage VGH with the first power supply of high level are provided to the
The second pole (drain electrode), the first pole (source electrode) of the 4th transistor M4 and the first pole of the 6th transistor M6 of three transistor M3
One end of (source electrode), the first charging capacitor C1, the voltage VGL with low level second source are provided to the 8th transistor M8
The second pole (drain electrode) of grid and the 5th transistor M5.Correspondingly, third transistor M2, third transistor M3 keep cut-off shape
State, the first transistor M1, the 5th transistor M5, low level SIN signals write the 8th transistor M8 by the first transistor M1
The first pole (source electrode) and the 4th transistor M4 grid, the low level of SIN signals makes the 4th transistor M4, the 8th transistor
M8 is turned on, and the low level of SIN signals is write to the grid of the 7th transistor M7, the 7th transistor M7 conductings, second clock signal
SCK2 is exported to signal output part OUT by the 7th transistor M7, i.e., signal output part OUT keeps output high during the t1 periods
Level signal, and the high level signal is the second clock signal SCK2 with high level.At this time, the 7th crystal can be turned on
The voltage of pipe M7 is stored (or charging) in the second charging capacitor C2.In addition, during the t1 periods, the 4th transistor M4's leads
The logical voltage VGH (high level) for causing the first power supply is supplied to first node N1, the 6th transistor M6 cut-off, therefore avoids
The output of the VGH signals of high level, advantageously reduces power consumption.
Next, during the t2 periods, there is the output signal of low level previous stage circuit or start scanning signal
SIN continues the second pole (source electrode) of supply the first transistor M1, and the first clock signal SCK1 with high level is provided to
The grid of the grid of the first transistor M1 and the 5th transistor M5, there is low level second clock signal SCK2 to be fed into the
The second pole (drain electrode) of the grid of two-transistor M2 and the 7th transistor M7, has the voltage VGH quilts of the first power supply of high level
It is supplied to the second pole (drain electrode) of third transistor M3, the first pole (source electrode) of the 4th transistor M4 and the 6th transistor M6
First pole (source electrode), one end of the first charging capacitor C1, the voltage VGL with low level second source are provided to the 8th crystalline substance
The second pole (drain electrode) of body pipe M8 grids and the 5th transistor M5.Because the voltage of the 7th transistor M7 can be turned on previous
Stored during period t1 (or charging) in the second charging capacitor C2 (i.e. C2 can keep the t1 periods during SIN signals it is low
Level), so the 7th transistor M7 is tended to remain on, there is low level second clock signal SCK2 to pass through the 7th transistor
M7 is exported to signal output part OUT, i.e., signal output part OUT keeps output low level signal, and the low electricity during the t2 periods
Ordinary mail number is with low level second clock signal SCK2.In addition, the 8th transistor M8 is held on during the t2 periods
State, low level section point N2 are low level by the grid of the 4th transistor M4 of the 8th transistor M8, therefore the
Four transistor M4 are tended to remain on, and the conducting of the 4th transistor M4 is so that the voltage VGH (high level) of the first power supply is supplied to
To first node N1, so that third transistor M3 and the 6th transistor M6 keeps cut-off state, therefore high level is avoided
VGH signals output, advantageously reduce power consumption.In addition, the first clock signal SCK1 of high level cause the first transistor M1,
5th transistor M5 ends, and low level second clock signal SCK2 causes second transistor M2 to turn on.
Next, during the t3 periods, there is the output signal of the previous stage circuit of high level or start scanning signal
SIN is supplied to the second pole (source electrode) of the first transistor M1, and there is low level first clock signal SCK1 to be provided to first
The grid of the grid of transistor M1 and the 5th transistor M5, the second clock signal SCK2 with high level are fed into the second crystalline substance
The grid of body pipe M2 and the second pole (drain electrode) of the 7th transistor M7, the voltage VGH with the first power supply of high level are provided
The first pole (source electrode) of the second pole (drain electrode), the 4th transistor M4 to third transistor M3 and the first of the 6th transistor M6
Pole (source electrode), one end of the first charging capacitor C1, the voltage VGL with low level second source are provided to the 8th transistor
The second pole (drain electrode) of M8 grids and the 5th transistor M5.Correspondingly, second transistor M2 ends, the first transistor M1, the
Five transistor M5 are turned on, and the SIN signals of high level write the first pole (source electrode) of the 8th transistor M8 by the first transistor M1
And the 4th transistor M4 grid, the high level of SIN signals makes the 4th transistor M4 cut-offs, the 8th transistor M8 conductings, high
The SIN signals of level are write to the grid of the 7th transistor M7 by the 8th transistor M8, and the 7th transistor M7 cut-offs, have height
The second clock signal SCK2 of level can not be exported to signal output part OUT.In addition, during the t3 periods, the 5th transistor
The conducting of M5 with the voltage VGL of low level second source so that be transmitted to first node N1 so that third transistor M3 and
The grid of 6th transistor M6 has low level, so that third transistor M3 and the 6th transistor M6 conductings, have high electricity
The voltage VGH of flat second source is exported to signal output part OUT, i.e., during the t3 periods, signal by the 6th transistor M6
Output terminal OUT keeps output high level signal, and the high level signal is the voltage VGH of the second source with high level.
At this time, the voltage that can turn on the 6th transistor M6 is stored (or charging) in the first charging capacitor C1.
Next, during the t4 periods, there is the output signal of the previous stage circuit of high level or start scanning signal
SIN continues the second pole (source electrode) of supply the first transistor M1, and the first clock signal SCK1 with high level is provided to
The grid of the grid of the first transistor M1 and the 5th transistor M5, there is low level second clock signal SCK2 to be fed into the
The second pole (drain electrode) of the grid of two-transistor M2 and the 7th transistor M7, has the voltage VGH quilts of the first power supply of high level
It is supplied to the second pole (drain electrode) of third transistor M3, the first pole (source electrode) of the 4th transistor M4 and the 6th transistor M6
First pole (source electrode), one end of the first charging capacitor C1, the voltage VGL with low level second source are provided to the 8th crystalline substance
The second pole (drain electrode) of body pipe M8 grids and the 5th transistor M5.Because the voltage of the 6th transistor M6 can be turned on previous
Stored during period t3 (or charging) in the first charging capacitor C1 (i.e. C1 can keep the t3 periods during VGL low electricity
It is flat), so third transistor M3 and the 6th transistor M6 are tended to remain on, there is the voltage VGH of the first power supply of high level
Exported by the 6th transistor M6 to signal output part OUT, i.e., during the t4 periods, signal output part OUT keeps the high electricity of output
Ordinary mail number, and the high level signal is the voltage VGH of the second source with high level.In addition, have during the t4 periods
Low level second clock signal SCK2 causes second transistor M2 to turn on, and the first clock signal SCK1 with high level causes
The first transistor M1 and the 5th transistor M5 cut-offs, the 8th transistor M8 are tended to remain on, and the 4th transistor M4 keeps cut-off
State, so that the grid of the 7th transistor M7 keeps high level, the 7th transistor M7 keeps cut-off for the conducting of the 8th transistor M8
State, there is low level second clock signal SCK2 can not export to signal output part OUT.
In the above-mentioned course of work, extended transistor MDx's (such as MD1, MD2, MD3) in speed expanded unit 133
Conducting and cut-off state are synchronous with the 7th transistor M7.T3 to the t4 periods be the pixel light emission stage.When signal output part OUT is carried
The VGH signals of confession are transmitted to corresponding scan line, and the data-signal of data cable corresponding with being synchronously filled with as scanning signal
Collective effect chooses the pixel of needs, so that the pixel chosen produces the light component with predetermined luminance component, for
Show image.
According to the description of the above-mentioned course of work, it is seen that level circuit of the invention can export the signal of required waveform.And
And the voltage inputted in t1 periods, the first power end and the second clock signal of second clock end input are high level, but
Signal output part only outputs the second clock signal of high level, avoids the voltage output of the first power supply of high level, favorably
In reduction power consumption.
Based on same inventive concept, the present embodiment also provides a kind of scanner driver, please refers to Fig.2, the turntable driving
Device include cascade multiple grades of circuit SG1, SG2 ..., SGn, the signal output part OUT of each level circuit is connected to be swept accordingly
Retouch on line, and according to the first clock signal SCK1, second clock signal SCK2, the voltage VGH of the first power supply and second source
Voltage VGL drives, such as the signal output part OUT of the level circuit SG1 of the first order is connected on first scan line S1, the second level
The signal output part OUT of level circuit SG2 be connected on Article 2 scan line S2, the signal of the level circuit SGn of afterbody is defeated
Outlet OUT is connected on the last item scan line Sn.Multiple grades of circuit SG1, SG2 ..., SGn there is identical circuit layout,
Using the level circuit layout shown in Figure 1A, each level circuit includes with lower structure：
Output module 13 with first node N1, section point N2 and signal output part OUT, for according to being applied to the
The voltage of one node N1 and section point N2, the voltage of the voltage VGH of the first power supply or second clock signal SCK2 are supplied to
Signal output part OUT；
With the first clock end SCK1, second clock end SCK2, the first power end VGH and the first signal input part SIN
Input module 11, the first clock end SCK1 is used to receive the first clock signal SCK1, and the second clock end SCK2 is used
It is used for the first power supply of access VGH, the first signal input in receiving second clock signal SCK2, the first power end VGH
SIN is held to be used for the output signal for receiving scanning commencing signal or previous stage circuit；The input module 11 is used for described the
One clock signal SCK1, second clock signal SCK2 control under by the first signal input part SIN received signals write；
With second source end VGL and connect the voltage control of the input module 11, first node N1 and section point N2
Molding block 12, the second source end VGL are used to access second source VGL, and the voltage control module 12 is used for described the
The voltage VGL of the voltage VGH of the first power supply or second source are provided to described first under the control of one clock signal SCK1
Node, and be provided to the voltage of the first signal input part SIN received signals under the voltage VGL controls of second source
Section point N2.
In addition, multiple grades of circuit SG1, SG2 ..., the first signal input part SIN of the level circuit SG1 of the first order in SGn
Receive and start scanning signal, the first signal input part SIN of remaining grade of circuit receives the signal output part of previous stage circuit
Export signal, such as the level electricity of the i-th -1 grade of the first signal input part SIN receptions of the level circuit SGi of i-stage (i is more than or equal to 2)
The signal of the signal output part OUT outputs of road SGi-1.In addition, the first clock signal SCK1 and second clock signal SCK2 have
Identical period and there is nonoverlapping phase.For example, when scanning signal is provided to the period quilt of a scan line
During referred to as 1 leveled time section 1H, clock signal SCK1 and SCK2 have the period of 2H and in different leveled time section quilts
There is provided.Specifically, although the time that the first clock signal SCK1 and second clock signal SCK2 are not provided can overlapping (example
Such as, the first clock signal SCK1 and second clock signal SCK2 can have high level at the same time), but the first clock signal SCK1 and
The time that second clock signal SCK2 is provided is (for example, the first clock signal SCK1 and second clock signal SCK2 has low electricity
The flat time) it is not overlapping.The signal of the signal output part OUT outputs of each level circuit is available to sweeping for corresponding scan line
Retouch signal, for choosing one-row pixels, correspondingly, multiple grades of circuit SG1, SG2 ..., SGn can sequentially by it is multiple scanning believe
Number it is supplied to multi-strip scanning line.
Based on same inventive concept, the present embodiment also provides a kind of display device, including above-mentioned scanner driver.It please join
Fig. 3 is examined, display device of the invention can be organic light-emitting display device, and the organic light-emitting display device specifically includes pixel
Area 20, data driver 21, scanner driver 22 and emission control driver 23, further include the electricity of the first power supply VGH and second
Source VGL.
Pixel region 20 can include multi-strip scanning line S, a plurality of data lines D, a plurality of launch-control line E and multiple pixel P,
Multi-strip scanning line S is, for example, scan line S1, S2 ..., the Sn arranged along line direction；A plurality of data lines D is, for example, along column direction cloth
Data cable D1, D2 ..., the Dm put；A plurality of launch-control line E is, for example, the launch-control line E1 arranged along line direction,
E2 ..., En；Multiple pixel p-shapeds are into defining in a plurality of data lines D1, D2 ..., Dm and multi-strip scanning line S1, S2 ..., Sn
In region, and be connected respectively to corresponding scan line, data cable, on launch-control line, can according to the data-signal of reception, sweep
Retouch signal and emissioning controling signal realizes corresponding shine to show image.Each pixel P can include image element circuit and organic
Light emitting diode, the image element circuit can produce the pixel current for flowing through pixel, and can be according to passing through a plurality of data lines
D1, D2 ..., Dm-1, the data-signal and pass through multi-strip scanning line S1, S2 ..., Sn-1 that Dm is transmitted, the scanning letter of Sn transmission
Number the pixel current is supplied to Organic Light Emitting Diode, i.e. image element circuit receives the electricity of data-signal in response to scanning signal
Pressure, and then corresponding pixel current is produced, when the anode electrode of the pixel current from Organic Light Emitting Diode (OLED) flows to
During its cathode electrode, luminescent layer can shine, and the brightness of light is corresponding with the pixel current amount, and Organic Light Emitting Diode produces at this time
The light with predetermined luminance corresponding with the voltage of data-signal is given birth to show image.The launch time section of pixel is (when shining
Between section) controlled by emissioning controling signal.
Data driver 21 may be coupled to a plurality of data lines D1, D2 ..., Dm.Data driver 21 can produce data
Signal, and data-signal is supplied to a plurality of data lines D1, D2 ..., Dm, the voltage of data-signal is applied to accordingly
On pixel P.
Scanner driver 22 may be coupled to multi-strip scanning line S1, S2 ..., Sn.Scanner driver 22 can produce scanning
Signal, and scanning signal is supplied to multi-strip scanning line S1, S2 ..., Sn, scanning signal is sequentially applied to corresponding picture
Element.Specific a line can be selected by scanning signal, and the data-signal of data driver 21 can be supplied to and be located at
Pixel P at selected particular row, the voltage of data-signal is received with addressed pixel P in response to scanning signal, and generation has
The light of predetermined luminance corresponding with the voltage of data-signal is to show image.The scanner driver 22 of the present embodiment is shown in Fig. 2
Scanner driver, that is, include cascade multiple grades of circuits SG1, SG2 ..., SGn, each level circuit can use Figure 1A shown in
Circuit structure, and the signal output part OUT of the level circuit SG1 of the first order connects first scan line S1 and the second level respectively
Level circuit SG2 the first signal input part SIN, the signal output part OUT of the level circuit SG2 of the second level connects Article 2 respectively
The first signal input part SIN ... of scan line S2 and the level circuit SG3 of the third level, the signal of the level circuit SGn of afterbody
Output terminal OUT connects the last item scan line Sn respectively.Further, since the scanner driver 22 uses the first clock signal
Multiple scanning signals are output to multi-strip scanning line by SCK1 and second clock signal SCK2, i.e. level circuit according to the present invention is not
Receive other initializing signal, thus the width of scanning signal can be configured to it is larger.
Emission control driver 23 may be coupled to a plurality of launch-control line E1, E2 ..., En.Emission control driver 23
Emissioning controling signal is produced in response to initial control signal, and emissioning controling signal is supplied to a plurality of launch-control line E1,
E2 ..., En, corresponding pixel is applied to by emissioning controling signal, to control the launch time of pixel section.
First power supply VGH and second source VGL is each image element circuit, data driver 21, turntable driving of pixel region 20
Device 22 and mission controller 23 provide the first supply voltage and second source voltage.As shown in figure 3, pixel region 20, data are driven
Dynamic device 21, scanner driver 22, emission control driver 23, the first power supply and second source can be formed on one piece of substrate.
Fig. 4 shows the circuit diagram of the level circuit of another embodiment of the present invention.In Fig. 4, by by identical label come
Represent the element identical with the element of Figure 1A, and detailed description thereof will not be repeated.
Please refer to Fig.4, in the level circuit of another embodiment of the present invention, the input module 11 further includes first control signal
Hold CS1, second control signal end CS2, secondary signal input terminal SIN ' and bi-directional drive unit 110.The bi-directional drive unit
110 include the 9th transistor M9 and the tenth transistor M10；The 9th transistor M9 be connected to the first signal input part SIN and
Between the second pole (drain electrode) of the first transistor M1, the grid of the 9th transistor M9 is connected to the first control signal end
CS1, the 9th transistor M9 are turned on when the first control signal end CS1 provides first control signal.Described tenth is brilliant
Body pipe M10 is connected between the second pole (drain electrode) of secondary signal input terminal SIN ' and the first transistor M1, the tenth crystal
The grid of pipe M10 is connected to the second control signal end CS2, and the tenth transistor M10 is at the second control signal end
CS2 is turned on when providing second control signal, and the first signal input part SIN receives output signal or the beginning of previous stage circuit
Scanning signal, secondary signal input terminal SIN ' receive the output signal of rear stage circuit or start scanning signal.Bi-directional drive list
Member 110 can cause scanning signal can be in the first direction (from first scan line S1 to nth bar scan line Sn) or along second party
It is provided to (a scan line S1 from nth bar scan line Sn to first), specifically, when first control signal CS1 is provided, the
Nine transistor M9 are turned on, the letter that the level circuit is exported according to the signal output part OUT for starting scanning signal or previous stage circuit
Number (i.e. scanning signal) driving, so that the scanner driver of multiple level circuits including cascade can be in the first direction
(from the first scan line S1 to the n-th scan line Sn) multiple scanning signals of Sequential output；When second control signal CS2 is provided,
Tenth transistor M10 is turned on, and the level circuit is exported according to the signal output part OUT for starting scanning signal or rear stage circuit
Signal (i.e. scanning signal) drives, so that the scanner driver of multiple level circuits including cascade can be along second party
To (a scan line S1 from nth bar scan line Sn to first) the multiple scanning signals of Sequential output.
Other driving processing of the level circuit of the present embodiment are identical with the driving processing of the level circuit shown in Figure 1A, so will
Its detailed description is not repeated.
Based on same inventive concept, the present embodiment also provides a kind of scanner driver, refer to Fig. 5, the turntable driving
Device include cascade multiple grades of circuit SG1, SG2 ..., SGn, the signal output part OUT of each level circuit is connected to be swept accordingly
Retouch on line, and according to the first clock signal SCK1, second clock signal SCK2, the voltage VGH of the first power supply, second source electricity
Press VGL, first control signal CS1 and second control signal CS2 drivings, such as the signal output part of the level circuit SG1 of the first order
OUT is connected on first scan line S1, and the signal output part OUT of the level circuit SG2 of the second level is connected to Article 2 scan line
On S2, the signal output part OUT of the level circuit SGn of afterbody is connected on the last item scan line Sn.Multiple grades of circuits
SG1, SG2 ..., SGn there is identical circuit layout, the circuit layout is as shown in Figure 4.The scanner driver of the present embodiment with
The main distinction of scanner driver shown in Fig. 2 has been drive signal more first control signal CS1 and second control signal
CS2, it is defeated that the input module of each level circuit further includes first control signal end CS1, second control signal end CS2, secondary signal
Enter to hold SIN ' and bi-directional drive unit, when first control signal CS1 is provided, the level electricity of rear stage in the scanner driver
The first signal input part SIN on road receives the signal (i.e. scanning signal) of the signal output part OUT outputs of the level circuit of previous stage,
The scanner driver root can (from the first scan line S1 to the n-th scan line Sn), the multiple scannings of Sequential output be believed in the first direction
Number；When second control signal CS2 is provided, the secondary signal input terminal of the level circuit of previous stage in the scanner driver
SIN ' receives the signal (i.e. scanning signal) of the signal output part OUT outputs of the level circuit of rear stage, the scanner driver energy
Enough (a scan line S1 from nth bar scan line Sn to first) multiple scanning signals of Sequential output in a second direction.The scanning is driven
Dynamic device remaining circuit part and driving processing are identical with the scanner driver shown in Fig. 2, are retouched in detail so will not be repeated again it
State.
Based on same inventive concept, the present embodiment also provides a kind of display device of the scanner driver including shown in Fig. 5.
In conclusion the level circuit of the present invention has small number of transistor and using only the first clock signal and the
Two clock signals can export the scanning signal of required waveform, and circuit is simple, and stability is high；And can to avoid at the same time there is height
The output of the second clock signal and the first supply voltage of level, reduces power consumption, be conducive to high performance scanner driver and
The manufacture of display device.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, but the present invention is not limited thereto.For those skilled in the art, the essence of the present invention is not being departed from
In the case of refreshing and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (11)
- A kind of 1. grade circuit, it is characterised in that including：Output module with first node, section point and signal output part, first node and second are applied to for basis The voltage of node, signal output part is supplied to by the voltage of the voltage of the first power supply or second clock signal；Input module with the first clock end, second clock end, the first power end and the first signal input part, described first Clock end is used to receive the first clock signal, and the second clock end is used to receive second clock signal, first power end For accessing the first power supply, first signal input part is used for the output letter for receiving scanning commencing signal or previous stage circuit Number；The input module be used for first clock signal, second clock signal control under will first signal input Hold received signal write-in；With second source end and connect the voltage control module of the input module, first node and section point, described Two power ends are used to access second source, and the voltage control module is used for first under the control of first clock signal The voltage of power supply or the voltage of second source are provided to the first node, and under the voltage control of second source by described in The voltage of first signal input part received signal is provided to section point.
- 2. as claimed in claim 1 grade of circuit, it is characterised in that the input module includes being sequentially arranged in first letter The first transistor, second transistor number between input terminal and first power end, third transistor, the first transistor Grid be connected to first clock end, the grid of the second transistor is connected to the second clock end, the described 3rd The grid of transistor is connected to the first node.
- 3. as claimed in claim 1 grade of circuit, it is characterised in that the voltage control module include pull-up control unit, under Draw control unit and partial pressure control unit；The pull-up control unit is connected to first power end and the first node Between, for the voltage of the first power supply to be supplied to first segment under the control of the first signal input part received signal Point；The drop-down control unit is connected between first node and the second source end, and the control of the drop-down control unit End processed is connected to first clock end, for being supplied to the voltage of second source under the control of first clock signal First node；The partial pressure control unit is connected between the input module and the output module, and the partial pressure controls Unit is additionally coupled to the control terminal of the pull-up control unit, the partial pressure control unit with the node that the input module is connected Control terminal be connected to the second source end, the partial pressure control unit is used for described the under the control of the second source The voltage of one signal input part received signal is provided to the section point, is additionally operable to share the pull-up control unit and institute The voltage between section point and on the circuit between the input module and the section point is stated, to protect the pull-up Control unit and the input module.
- 4. as claimed in claim 3 grade of circuit, it is characterised in that the pull-up control unit includes the 4th transistor, described Drop-down control unit includes the 5th transistor, and the partial pressure control unit includes the 8th transistor, wherein, the 4th transistor Grid be the pull-up control unit control terminal, be connected to the first pole of the 8th transistor, the 4th transistor The first pole be connected to first power end, the second pole of the 4th transistor is connected to the first node；Described Control terminal of the grid of five transistors as the drop-down control unit, is connected to first clock end, the 5th crystal First pole of pipe is connected to the first node, and the second pole of the 5th transistor is connected to the second source end；It is described The grid of 8th transistor is the control terminal of the partial pressure control unit, is connected to the second source end, the 8th crystal First pole of pipe is additionally coupled to the input module, and the second pole of the 8th transistor is connected to the section point.
- 5. as claimed in claim 1 grade of circuit, it is characterised in that the output module is defeated including the first output unit and second Go out unit, first output unit connects first node, the first power end and the signal output part, for described first By the voltage output of first power supply to the signal output part under the control of node；Described in the second output unit connection Section point, second clock end and signal output part, under the control of the section point by the second clock signal Export to the signal output part.
- 6. as claimed in claim 5 grade of circuit, it is characterised in that first output unit includes the first charging capacitor and the Six transistors, the grid of the 6th transistor and one end of first charging capacitor are connected to the first node, institute State the first pole of the 6th transistor and the other end of first charging capacitor is connected to first power end, the described 6th Second pole of transistor is connected to the signal output part；Second output unit includes the second charging capacitor and the 7th crystal Pipe, the grid of the 7th transistor and one end of second charging capacitor are connected to the section point, and the described 7th The other end of first pole of transistor and first charging capacitor is connected to the signal output part, the 7th transistor The second pole be connected to the second clock end.
- 7. as claimed in claim 5 grade of circuit, it is characterised in that the output module further include speed expanded unit and/or Filter unit, the speed expanded unit is in parallel with second output unit, and the signal output part is transmitted to for improving Signal transmission speed；Described filter unit one end is connected to the section of the first output unit and the second output unit connection At point, one end is connected to the signal output part, for first output unit or the second output unit signal output Signal is transmitted to the signal output part after being filtered.
- 8. as claimed in claim 7 grade of circuit, it is characterised in that the speed expanded unit includes at least one with described the The extended transistor of seven coupled in parallel, the grid of each extended transistor are connected to the second clock end, each extension First pole of transistor is connected to the signal output part, and the second pole of each extended transistor is connected to second section Point；The filter unit includes filter capacitor and protective resistance, one end of the protective resistance and one end of the filter capacitor The signal output part is connected to, the other end of the protective resistance is connected to first output unit and the second output is single At the node of member connection, the other end ground connection of the filter capacitor.
- 9. the level circuit as any one of claim 1 to 7, it is characterised in that the input module further includes the first control Signal end, second control signal end, secondary signal input terminal and bi-directional drive unit processed, the bi-directional drive unit include the 9th Transistor and the tenth transistor, the 9th transistor be connected to the first signal input part and the first transistor the second pole it Between, the grid of the 9th transistor is connected to the first control signal end, and the 9th transistor is in the described first control Signal end turns on when providing first control signal, and the tenth transistor is connected to secondary signal input terminal and the first transistor Between second pole, the grid of the tenth transistor is connected to the second control signal end, and the tenth transistor is described Second control signal end turns on when providing second control signal, and first signal input part receives the output letter of previous stage circuit Number or start scanning signal, secondary signal input terminal receive rear stage circuit output signal or start scanning signal.
- A kind of 10. scanner driver, it is characterised in that the level electricity any one of multiple claims 1 to 9 including cascade Road, the signal output part of each level circuit are connected in corresponding scan line, and the first signal input of the level circuit of the first order End, which receives, starts scanning signal, and the first signal input part of remaining grade of circuit receives the defeated of the signal output part of previous stage circuit Go out signal.
- 11. a kind of display device, it is characterised in that including the scanner driver described in claim 10.
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| CN201810054349.1A CN107978276B (en) | 2018-01-19 | 2018-01-19 | Grade circuit, scanner driver and display device |
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| CN201810054349.1A CN107978276B (en) | 2018-01-19 | 2018-01-19 | Grade circuit, scanner driver and display device |
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| CN110364121A (en) * | 2019-06-27 | 2019-10-22 | 昆山国显光电有限公司 | Scanning circuit, display panel and display device |
| CN110767175A (en) * | 2019-10-08 | 2020-02-07 | 武汉华星光电半导体显示技术有限公司 | Drive circuit and display panel |
| CN111243513A (en) * | 2020-03-13 | 2020-06-05 | Oppo广东移动通信有限公司 | Control circuit and control method |
| WO2021042512A1 (en) * | 2019-09-05 | 2021-03-11 | 深圳市华星光电半导体显示技术有限公司 | Display driving circuit |
| CN113168814A (en) * | 2018-11-23 | 2021-07-23 | 三星显示有限公司 | Scanning drive unit |
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| CN111243513A (en) * | 2020-03-13 | 2020-06-05 | Oppo广东移动通信有限公司 | Control circuit and control method |
| CN111243513B (en) * | 2020-03-13 | 2021-07-20 | Oppo广东移动通信有限公司 | Control circuit and control method |
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