CN107976646B - Signal power characteristic compensation method and device based on vector network analyzer - Google Patents
Signal power characteristic compensation method and device based on vector network analyzer Download PDFInfo
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Abstract
The invention discloses a signal power characteristic compensation method and a signal power characteristic compensation device based on a vector network analyzer, which are used for collecting uncompensated power values of various frequency points, calculating DAC (digital-to-analog converter) values required when the uncompensated power values are compensated to set power, adjusting the power according to the DAC values and storing the DAC values in a memory; and obtaining the storage position of the DAC value required by the current frequency compensation according to the current frequency and the stepping frequency, reading the DAC value from the memory, and outputting the DAC value to the compensation circuit for power compensation. The invention saves the compensation data in the hardware and realizes the power compensation function through the hardware, thereby reducing the calculation time and improving the scanning speed, simultaneously, one point is calibrated by 16MHz, when the scanning point falls into the range, the compensation data is directly called from the memory, and the compensation precision is improved by increasing the number of calibration points.
Description
Technical Field
The invention relates to the field of signal power characteristic compensation, in particular to a signal power characteristic compensation method and device based on a vector network analyzer.
Background
For a vector network analyzer, the power accuracy of an output signal has a direct influence on the measurement precision, and at present, a certain gap exists between the power precision of a port output signal of a domestic vector network analyzer and a foreign similar product, mainly because the power of the output signal at different frequency points is different due to the influence of the frequency characteristics of components in the signal generation process.
At present, the vector network analyzer in China mainly adopts a software interpolation method to compensate the power of an output signal and keep the power of the output signal at a set value.
With the development of measurement technology, the index requirements of users on the vector network analyzer are higher and higher. Due to the influence of the frequency characteristics of devices, the power of output signals of the vector network analyzer at different frequency points may be greatly different from a program set value, so that errors occur during measurement, and the domestic vector network has a certain gap compared with similar products abroad, so that the power error is reduced, and the measurement accuracy is improved, which becomes one of the problems to be solved by the vector network analyzer.
At present, a domestic vector network analyzer mostly uses a software interpolation method to improve the output power accuracy, and the method comprises the steps of selecting a plurality of points (generally selecting one point every hundreds of MHz) in the whole scanning frequency band, calibrating the power of each calibration point to be near 0dBm through a power meter when the power is set to be 0dBm, obtaining a DAC value of each calibration point, judging which two calibration points the currently scanned point falls between in the scanning process, using the DAC values of the two calibration points as reference to be used as an interpolation slope algorithm to obtain the DAC value of the current point, and then sending the DAC value of the current point to a power setting circuit to be added to a DA conversion summation circuit to realize power compensation. Finally, all the points of the scanning can meet the power accuracy index.
The prior art mainly adopts a software interpolation method for compensation, the method mainly realizes power compensation of each scanning point through software, the software can select a plurality of points to be calibrated to a set value through a power meter to obtain corresponding compensation data, the software can firstly judge which two calibration points the current scanning point falls between and take the two calibration points as reference to be used as an interpolation algorithm, because each point needs to be judged, the scanning time is increased, the scanning speed is reduced, and meanwhile, the number of reference points selected by the software during the calibration by the power meter is less, and the compensation precision is poor.
In summary, the prior art has a problem that the software interpolation method increases the scanning time and the compensation accuracy is poor, and an effective solution is not yet available.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a signal power characteristic compensation method and device based on a vector network analyzer.
The technical scheme adopted by the invention is as follows:
a signal power characteristic compensation method based on a vector network analyzer comprises the following steps:
step 1: collecting uncompensated power values of each frequency point, calculating a DAC value required when the uncompensated power values are compensated to set power, adjusting the power according to the DAC value, and storing the DAC value in a memory;
step 2: and obtaining the storage position of the DAC value required by the current frequency compensation according to the current frequency and the stepping frequency, reading the DAC value from the memory, and outputting the DAC value to the compensation circuit for power compensation.
Further, in step 1, acquiring an uncompensated power value of each frequency point, calculating a DAC value required when the uncompensated power value is compensated to a set value, performing power adjustment according to the DAC value, and storing the DAC value in a memory, includes:
step 1.1: dividing the scanning range into a plurality of frequency bands at equal intervals, and calculating the adjustable power range of the compensation circuit;
step 1.2: collecting uncompensated power values of each point in each frequency band, and calculating a DAC value required when each uncompensated power value is compensated to set power;
step 1.3: the compensation circuit converts the DAC value into a voltage value according to the received DAC value to carry out power adjustment, and an adjusted power value is obtained;
step 1.4: verifying whether the adjusted power value meets an expected compensation threshold value, if not, calculating the DAC value again, and returning to the step 1.3; if yes, entering step 1.5;
step 1.5: the DAC value is stored in memory.
Further, the dividing the scanning range into a plurality of frequency bands at equal intervals and calculating the adjustable power range of the compensation circuit includes:
dividing the whole scanning range into a plurality of frequency bands at equal intervals, and selecting a middle frequency point of each frequency band as a calibration standard;
setting the DAC value to 0 and 4095, respectively, and reading the minimum adjustable power value when the DAC value is 0; when the DAC value is 4095, the maximum adjustable power value;
the vector network analyzer sets a power value.
The power set value is used as a compensation target, and an error range deviating from the power set value by a certain degree is used as a compensation threshold value.
Further, after calculating the adjustable power range, the required DAC value for each 1dB change in power is also calculated.
Further, the acquiring an uncompensated power value of each point in each frequency band, and calculating a DAC value required when each uncompensated power value is compensated to a set power, includes:
(1) the vector network analyzer collects the uncompensated power value of the current frequency point by connecting a power meter;
(2) calculating the DAC value required when the uncompensated power value is compensated to the set power according to the DAC value required when the power changes by 1 dB;
(3) and (3) adding a fixed frequency value on the basis of the current frequency to obtain the frequency of the next point, and repeating the steps (1) to (2) until the DAC value required when the frequency of all points in the whole frequency band is compensated to the set power is obtained.
Further, the verifying whether the adjusted power value reaches the power value threshold includes:
when the error between the adjusted power value and the power set value is smaller than the power value threshold, the requirement is met; otherwise, the required DAC value is corrected when the power value is compensated to the set value according to the required DAC value when the power changes by 1dB and the error between the power value and the power set value, the corrected DAC value is sent to the compensation circuit, and the adjustment is carried out again until the expected compensation threshold value is met.
Further, in step 2, obtaining a storage location of a DAC value required for current frequency compensation according to the current frequency and the step frequency, reading the DAC value from the memory, and outputting the DAC value to the compensation circuit for power compensation, including:
step 2.1: the CPLD receives the initial frequency and the stepping frequency sent by the vector network analyzer;
step 2.2: dividing the current frequency by the stepping frequency, and rounding to obtain the storage position of the DAC value required by the frequency to be compensated in the memory;
step 2.3: reading the stored DAC value and outputting the DAC value to a compensation circuit;
step 2.4: the compensation circuit carries out power compensation on the current frequency point according to the DAC value, and meanwhile, the stepping frequency is added on the basis of the current frequency to obtain the frequency value of the next scanning point;
step 2.5: judging whether a trigger signal is received, and if the trigger signal is received, repeating the step 2.2-2.4; otherwise, the power compensation is completed.
A signal power characteristic compensation device based on a vector network analyzer comprises the vector network analyzer, a CPLD, a memory and a compensation circuit;
the vector network analyzer is connected with a power meter and is used for collecting uncompensated power values of all frequency points, calculating DAC values required when the uncompensated power values are compensated to set values, and sending the DAC values to the CPLD;
the CPLD is used for sending the DAC value to the compensation circuit;
the compensation circuit is used for converting the received DAC value into a voltage value through DA conversion to carry out power adjustment;
and the memory is used for storing the DAC value after the power adjustment.
Further, the vector network analyzer sends the starting frequency and the stepping frequency to the CPLD; the CPLD divides the frequency of the scanning point by the stepping frequency, and performs rounding to obtain the storage address of the DAC value of the frequency to be compensated in the memory, reads the stored DAC value and outputs the DAC value to the compensation circuit; and the compensation circuit performs power compensation according to the received DAC value.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the invention, a 12-bit DAC circuit is added in the compensation circuit, the power can be adjusted by setting a proper DAC, and data storage and reading are changed into hardware implementation, so that the time of software calculation is avoided, the scanning speed is improved, and meanwhile, more calibration points are provided, and the compensation precision is also improved;
(2) the invention saves the compensation data in the hardware, realizes the power compensation function through the hardware, realizes the part of software calculation through the hardware, reduces the calculation time, improves the scanning speed, simultaneously adopts one point for each 16MHz calibration, directly calls the compensation data from the memory when the scanning point falls into the range, and improves the compensation precision by increasing the number of calibration points.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application.
FIG. 1 is a flowchart of a calibration process in a compensation method for signal power characteristics based on a vector network analyzer according to an embodiment of the present invention;
fig. 2 is a flowchart of a scanning process in a compensation method for signal power characteristics based on a vector network analyzer according to an embodiment of the present invention.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As described in the background of the invention, the software interpolation method in the prior art has the disadvantages of increased scanning time and poor compensation accuracy, and in order to solve the above technical problems, the present application provides a signal power characteristic compensation method and apparatus based on a vector network analyzer.
Example one
The present embodiment aims to provide a signal power characteristic compensation method based on a vector network analyzer, which includes a calibration process and a scanning process.
1. Calibration procedure
Fig. 1 is a flow chart of a calibration process for compensating signal power characteristics. During calibration, the whole scanning range is divided into four to five frequency bands, the middle frequency point of each frequency band is selected as a calibration standard, 12-bit DACs are respectively set to be 0 and 4095, the read power meter value is the minimum and maximum adjustable power value, the DAC value required by each 1dB change of power is obtained through calculation, then the frequency point is selected from the starting frequency at intervals of 16MHz for power calibration, the power value of the point is read first, then the DAC value required when the power is compensated to the set value is obtained through calculation, the DAC value is added into a circuit for verification, if the error requirement is met, the DAC value is stored in a memory, and if the error requirement is not met, the DAC value is continuously adjusted until the error requirement is met. The specific process comprises the following steps:
step 101: the scanning range is divided into a plurality of frequency bands at equal intervals, and the power range adjustable by the compensation circuit is calculated.
Dividing the whole scanning range into a plurality of frequency bands at equal intervals, and selecting a middle frequency point of each frequency band as a calibration standard; setting the DAC value to 0 and 4095, respectively, and reading the minimum adjustable power value when the DAC value is 0; when the DAC value is 4095, the maximum adjustable power value; determining a power set value through a vector network analyzer; and taking the power set value as a compensation target, and taking an error range deviating from the power set value by a certain degree as a compensation threshold value.
At the same time, the required DAC value for each 1dB change in power is also calculated
Step 102: and collecting the uncompensated power value P1 of each point in each frequency band, and calculating the DAC value required when each uncompensated power value is compensated to the set power.
The vector network analyzer collects the uncompensated power value of the current frequency point by connecting a power meter; calculating the DAC value required when the uncompensated power value is compensated to the set power according to the DAC value required when the power changes by 1 dB; adding 16MHz to the current frequency to obtain the frequency of the next point, and calculating the power value P1 without frequency compensation of the point again; and calculating the DAC value required when the uncompensated power value is compensated to the set power according to the DAC value required when the power changes by 1dB until the DAC value required when the frequency of all points in the whole frequency range is compensated to the set power is obtained, transmitting the DAC value to the CPLD, and transmitting the DAC value to the compensation circuit through the CPLD.
Step 103: and the compensation circuit converts the DAC value into a voltage value according to the received DAC value to carry out power adjustment, so that an adjusted power value P2 is obtained.
In the compensation circuit, the DAC value is converted into a voltage value through DA conversion for power adjustment, and the adjusted power value P2 is read through a vector network analyzer.
Step 104: and verifying whether the adjusted power value P2 meets the expected compensation threshold, if not, calculating the DAC value again, sending the DAC value to the compensation circuit, and adjusting again until the expected compensation threshold is met.
When the error between the adjusted power value and the power set value is smaller than the power value threshold, the requirement is met; otherwise, the required DAC value is corrected when the power value is compensated to the set value according to the required DAC value when the power changes by 1dB and the error between the power value and the power set value, the corrected DAC value is sent to the compensation circuit, and the adjustment is carried out again until the expected compensation threshold value is met.
Step 105: and storing the DAC value after the power adjustment into a memory.
2. Scanning process
Fig. 2 is a flowchart of a scanning process for compensating the signal power characteristic. During scanning, the frequency and the scanning step of a starting point are sent to the CPLD, after the CPLD receives the starting frequency, the frequency is divided by 16MHz and then is rounded to obtain a storage position of compensation data, then the data is called from a storage chip and is added into a summation compensation circuit, so that the power of the point is compensated, meanwhile, the CPLD adds the step data to the starting frequency to find the frequency of the next scanning point, when a trigger signal is received, the calculation process is repeated to find the compensation data of the point until the scanning of the whole frequency band is completed, and the software for starting the second scanning can resend the starting frequency and the step. The specific process comprises the following steps:
step 201: the CPLD receives the initial frequency and the stepping frequency sent by the vector network analyzer;
step 202: dividing the current frequency by the stepping frequency, and rounding to obtain the storage address of the DAC value which is required to be compensated by the frequency in the memory;
step 203: reading the stored DAC value and outputting the DAC value to a compensation circuit;
step 204: the compensation circuit carries out power compensation on the current frequency point according to the DAC value, and meanwhile, the stepping frequency is added on the basis of the current frequency to obtain the frequency value of the next scanning point;
step 205: judging whether a trigger signal is received, and if the trigger signal is received, repeating the step 2.2-2.4; otherwise, the power compensation is completed.
Example two
The embodiment provides a signal power characteristic compensation device based on a vector network analyzer, which comprises the vector network analyzer, a CPLD, a memory and a compensation circuit.
The vector network analyzer is connected with a power meter to collect uncompensated power values of all frequency points, calculates DAC values required when the uncompensated power values are compensated to set values, and sends the DAC values to the CPLD; the CPLD sends the DAC value to a compensation circuit; the compensation circuit converts the received DAC value into a voltage value through DA conversion to carry out power adjustment; the memory stores the power adjusted DAC value.
The vector network analyzer sends the initial frequency and the stepping frequency to the CPLD; the CPLD divides the frequency of the scanning point by the stepping frequency, and performs rounding to obtain the storage address of the DAC value of the frequency to be compensated in the memory, reads the stored DAC value and outputs the DAC value to the compensation circuit; and the compensation circuit performs power compensation according to the received DAC value.
The compensation circuit comprises a 12-bit D/A converter and a corresponding peripheral operational amplifier, DAC data are converted into voltage through a D/A conversion chip, and the voltage is output to the voltage-controlled attenuator after the voltage is reversely amplified through the peripheral operational amplifier, so that power change is adjusted.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
(1) according to the invention, a 12-bit DAC circuit is added in the compensation circuit, the power can be adjusted by setting a proper DAC, and data storage and reading are changed into hardware implementation, so that the time of software calculation is avoided, the scanning speed is improved, and meanwhile, more calibration points are provided, and the compensation precision is also improved;
(2) the invention saves the compensation data in the hardware, realizes the power compensation function through the hardware, realizes the part of software calculation through the hardware, reduces the calculation time, improves the scanning speed, simultaneously adopts one point for each 16MHz calibration, directly calls the compensation data from the memory when the scanning point falls into the range, and improves the compensation precision by increasing the number of calibration points.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (7)
1. A signal power characteristic compensation method based on a vector network analyzer is characterized by comprising the following steps:
step 1: collecting uncompensated power values of each frequency point, calculating a DAC value required when the uncompensated power values are compensated to set power, adjusting the power according to the DAC value, and storing the DAC value in a memory;
step 2: according to the current frequency and the stepping frequency, obtaining a storage position of a DAC value required by the current frequency compensation, reading the DAC value from a memory, and outputting the DAC value to a compensation circuit for power compensation;
step 1.1: dividing the scanning range into a plurality of frequency bands at equal intervals, and calculating the adjustable power range of the compensation circuit;
step 1.2: collecting uncompensated power values of each point in each frequency band, and calculating a DAC value required when each uncompensated power value is compensated to set power;
step 1.3: the compensation circuit converts the DAC value into a voltage value according to the received DAC value to carry out power adjustment, and an adjusted power value is obtained;
step 1.4: verifying whether the adjusted power value meets an expected compensation threshold value, if not, calculating the DAC value again, and returning to the step 1.3; if yes, entering step 1.5;
step 1.5: storing the DAC value in a memory;
the dividing the scanning range into a plurality of frequency bands at equal intervals and calculating the adjustable power range of the compensation circuit comprises the following steps:
dividing the whole scanning range into a plurality of frequency bands at equal intervals, and selecting a middle frequency point of each frequency band as a calibration standard;
setting the DAC value to 0 and 4095, respectively, and reading the minimum adjustable power value when the DAC value is 0; when the DAC value is 4095, the maximum adjustable power value;
a vector network analyzer determines a power set value;
and taking the power set value as a compensation target, and taking an error range deviating from the power set value by a certain degree as a compensation threshold value.
2. The method of claim 1, wherein after the adjustable power range is calculated, the DAC value required for each 1dB change in power is also calculated.
3. The method of claim 1, wherein the collecting an uncompensated power value of each point in each frequency band and calculating a DAC value required for each uncompensated power value to be compensated to a set power comprises:
(1) the vector network analyzer collects the uncompensated power value of the current frequency point by connecting a power meter;
(2) calculating the DAC value required when the uncompensated power value is compensated to the set power according to the DAC value required when the power changes by 1 dB;
(3) and (3) adding a fixed frequency value on the basis of the current frequency to obtain the frequency of the next point, and repeating the steps (1) to (2) until the DAC value required when the frequency of all points in the whole frequency band is compensated to the set power is obtained.
4. The method of claim 1, wherein the verifying whether the adjusted power value reaches the power value threshold comprises:
when the error between the adjusted power value and the power set value is smaller than the power value threshold, the requirement is met; otherwise, the required DAC value is corrected when the power value is compensated to the set value according to the required DAC value when the power changes by 1dB and the error between the power value and the power set value, the corrected DAC value is sent to the compensation circuit, and the adjustment is carried out again until the expected compensation threshold value is met.
5. The method as claimed in claim 1, wherein the step 2 of obtaining a DAC value storage location required for the current frequency compensation according to the current frequency and the step frequency, reading the DAC value from the memory, and outputting the DAC value to the compensation circuit for power compensation comprises:
step 2.1: the CPLD receives the initial frequency and the stepping frequency sent by the vector network analyzer;
step 2.2: dividing the current frequency by the stepping frequency, and rounding to obtain the storage position of the DAC value required by the frequency to be compensated in the memory;
step 2.3: reading the stored DAC value and outputting the DAC value to a compensation circuit;
step 2.4: the compensation circuit carries out power compensation on the current frequency point according to the DAC value, and meanwhile, the stepping frequency is added on the basis of the current frequency to obtain the frequency value of the next scanning point;
step 2.5: judging whether a trigger signal is received, and if the trigger signal is received, repeating the step 2.2-2.4; otherwise, the power compensation is completed.
6. A signal power characteristic compensation device based on a vector network analyzer is characterized by comprising the vector network analyzer, a CPLD, a memory and a compensation circuit;
the vector network analyzer is connected with a power meter and is used for collecting uncompensated power values of all frequency points, calculating DAC values required when the uncompensated power values are compensated to set values, and sending the DAC values to the CPLD;
the CPLD is used for sending the DAC value to the compensation circuit;
the compensation circuit is used for converting the received DAC value into a voltage value through DA conversion to carry out power adjustment;
the memory is used for storing the DAC value after power adjustment;
collecting uncompensated power values of each frequency point, calculating a DAC value required when the uncompensated power values are compensated to a set value, adjusting power according to the DAC value, and storing the DAC value in a memory, wherein the method comprises the following steps:
step 1: dividing the scanning range into a plurality of frequency bands at equal intervals, and calculating the adjustable power range of the compensation circuit;
step 2: collecting uncompensated power values of each point in each frequency band, and calculating a DAC value required when each uncompensated power value is compensated to set power;
and step 3: the compensation circuit converts the DAC value into a voltage value according to the received DAC value to carry out power adjustment, and an adjusted power value is obtained;
and 4, step 4: verifying whether the adjusted power value meets an expected compensation threshold value, if not, calculating the DAC value again, and returning to the step 3; if yes, entering step 5;
and 5: storing the DAC value in a memory;
the dividing the scanning range into a plurality of frequency bands at equal intervals and calculating the adjustable power range of the compensation circuit comprises the following steps:
dividing the whole scanning range into a plurality of frequency bands at equal intervals, and selecting a middle frequency point of each frequency band as a calibration standard;
setting the DAC value to 0 and 4095, respectively, and reading the minimum adjustable power value when the DAC value is 0; when the DAC value is 4095, the maximum adjustable power value;
a vector network analyzer determines a power set value;
and taking the power set value as a compensation target, and taking an error range deviating from the power set value by a certain degree as a compensation threshold value.
7. The vector network analyzer-based signal power characteristic compensation device of claim 6, wherein the vector network analyzer transmits a start frequency and a step frequency to the CPLD; the CPLD divides the frequency of the scanning point by the stepping frequency, and performs rounding to obtain the storage address of the DAC value of the frequency to be compensated in the memory, reads the stored DAC value and outputs the DAC value to the compensation circuit; and the compensation circuit performs power compensation according to the received DAC value.
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| CN114337860B (en) * | 2022-01-07 | 2023-09-26 | 中电科思仪科技股份有限公司 | Power calibration optimization method and system of signal generating device |
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