CN107966454A - A kind of end plug defect detecting device and detection method based on FPGA - Google Patents
A kind of end plug defect detecting device and detection method based on FPGA Download PDFInfo
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Abstract
The invention discloses a kind of end plug defect detecting device based on FPGA, described device includes image capture module, signal converting module, FPGA main control modules, host computer.Wherein image capture module is used for the side surface image and upper surface image data for gathering end plug, and changes intermediary using Signals Transfer Board as transmission, and LVDS types of image data is converted into TTL categorical datas and is transferred to FPGA master control systems；FPGA main control modules are mainly used for handling end plug view data, detect end plug defect, and result is sent to host computer and is shown；Machine vision and image processing techniques based on FPGA are applied to end plug surface defects detection by the present invention, are effectively guaranteed real-time and precision that end plug detects.
Description
Technical Field
The invention relates to the technical field of end plug surface defect detection, in particular to an end plug surface defect detection device based on an FPGA (field programmable gate array).
Background
End plugs are an important component of nuclear reaction fuel rods, primarily for sealing the fuel rod against spillage of nuclear reaction products. In the actual processing, manufacturing and midway transportation processes of the end plug, scratches, bruises or other defects appear on the side surface of the end plug due to mechanical aging, materials or artificial reasons, and foreign matters or burrs appear in the center hole of the end plug. For the detection of defects on the surface of the end plug, no mature method and corresponding non-destructive detection device based on machine vision exist at present. At present, the traditional human eye detection method is adopted for detecting the defects on the surface of the end plug, the detection method has the defects of high labor intensity, low detection efficiency, high detection precision easily influenced by physiological visual fatigue of workers and personal subjectivity, and inevitably causes missed detection or false detection, and simultaneously needs to consume a large amount of human resources.
In addition, in recent years, an end plug surface defect detection method based on an ultrasonic principle appears, and a method for detecting the surface defect of the end plug by adopting an ultrasonic detection method of the inclined groove flaw on the surface of the end plug, which is proposed by people in the name of san et al, has the advantages of high cost, difficulty in detecting workpieces with complex surface shapes and no accordance with the production requirements of end plug defect detection.
Disclosure of Invention
Aiming at the problems and the defects in the end plug defect detection, the invention applies the FPGA and the machine vision technology to the end plug defect detection and provides the nondestructive defect detection device which has the advantages of lower cost, simple structure, high real-time performance and high detection precision.
The invention is realized by the following technical scheme:
an end plug defect detection device based on FPGA comprises a rotary detection table, an image acquisition module, an FPGA main control module containing an image processing module and an upper computer; the FPGA main control module is respectively interacted with the image acquisition module and the upper computer;
the image acquisition module comprises an area-array camera for adopting the images of the holes of the end plugs and a linear array camera for acquiring the images of the side faces of the end plugs; the area-array camera is positioned right above the rotary detection table, and the line-array camera is positioned laterally above the rotary detection table;
the FPGA main control module is used for transmitting the acquired images to the image processing module and transmitting the defects detected by the image processing module to an upper computer;
the image processing module is used for detecting defects in the image and comprises an image preprocessing unit, a feature extraction unit and a classification unit;
the image preprocessing unit is used for carrying out noise reduction and background compensation on the image acquired by the image acquisition module;
the feature extraction unit is used for extracting defect features of the filtered and background-compensated image;
the classification unit is used for identifying and classifying the extracted defect characteristics.
Further, the feature extraction unit comprises an image segmentation subunit, a morphology processing subunit and a defect extraction subunit which are connected in sequence;
the image segmentation subunit is used for extracting suspected defects in the image;
the morphology processing subunit is used for removing non-defects in the suspected defects;
the defect feature extraction subunit is used for extracting the aspect ratio feature, the circularity feature, the area feature, the gray mean feature and the gray standard deviation feature of the defect.
Further, the rotary detection table comprises a detection platform and a motor; the motor is installed below testing platform to drive testing platform rotation.
Furthermore, an encoder is connected to the motor and is connected with the FPGA main control module;
the FPGA main control module also comprises a motor control module and a trigger control module; the motor control module is used for controlling the motor; the trigger control module is used for receiving the motor rotating speed information collected by the encoder and outputting a line trigger signal to trigger the linear array camera according to the rotating speed information.
Further, the device also comprises a first light source and a second light source; the first light source is arranged on the detection platform and vertically irradiates the hole of the end plug; the second light source is arranged above the side of the detection platform and horizontally irradiates the side face of the end plug.
Furthermore, the image acquisition module interacts with the FPGA main control module through a signal adapter plate; the signal adapter plate comprises a control signal module, a serial communication module and an image data module.
Furthermore, the area-array camera and the line-scan camera are both connected with a camera fine-tuning device for adjusting the shooting angle.
A detection method of an end plug defect detection device based on an FPGA comprises the following steps:
s1, collecting an image of an object to be detected;
s2, carrying out noise reduction on the acquired image by adopting an improved median filtering algorithm, and compensating the background by adopting a polynomial fitting mode;
s3, extracting suspected defects of the image obtained in the step S2 by adopting a Soble operator combined double-threshold segmentation method;
s4, eliminating non-defects in the suspected defects by adopting opening and closing operation;
s5, extracting aspect ratio features, circularity features, area features, gray mean features and gray standard deviation features of the defects in the suspected defects;
and S6, identifying and classifying the defect characteristics extracted in the step S5 by adopting an SVM classifier.
Further, the specific method for extracting the suspected defects by combining the Soble operator and the double-threshold segmentation method in the step S3 is as follows:
1. edge gradient calculation
Calculating the gradient value and gradient direction of each pixel point in the image in the x and y directions, wherein the calculation formula is as follows:
wherein P is a pixel matrix after noise reduction, G X And G Y Respectively representing the gray gradient values in the horizontal direction and the vertical direction, G is the size of the gradient value of the processing pixel point, and theta represents the gradient direction;
2. defect edge detection
Processing the gradient value of the pixel point by adopting a dual-threshold segmentation method, determining whether the pixel point is a defect edge, and outputting a binary image, wherein the calculation formula is as follows:
wherein, P m To process the value of a pixel, T 1 、T 2 (T 1 ＜T 2 ) For the set dual threshold, if the gray value G of the pixel point is larger than T 2 Or G < T 1 If the pixel point is the edge of the defect, otherwise, the pixel point is the normal background;
3. defect localization and segmentation
After a binary image of the end plug image is obtained, the end plug image is subjected to defect positioning and segmentation processing, the end plug defect is positioned by adopting a vertex method, firstly, the end plug image data is traversed, and the upper left corner coordinate { X ] of a defect area is determined min ,Y min The coordinates of the lower right corner { X } max ,Y max Finishing the primary positioning of the defects; further extract { X over end plug image min ‐m,Y min -m } and { X } max +m,Y max A rectangular area between + m } where m represents the number of expanded pixel values as a defective area.
Further, the method for extracting the defect features in step S5 is as follows:
length to width ratio T
The length-width ratio T of the defect refers to the ratio of the length to the width of the minimum circumscribed rectangle of the defect area, and the formula is as follows:
wherein L and W represent the length and width of the defect region, respectively;
degree of circularity E
The circularity E is a parameter for describing how similar the defect shape is to a circular shape, and is expressed by the formula:
wherein P is the perimeter of the defect region, and E is 1 when the defect shape is circular; the larger the difference between the defect shape and the circular shape is, the smaller E is;
area A
The area of the image defect is a variable describing the size of the whole defect area, and the number of pixel points occupied by the defect area is generally calculated by the following formula:
wherein Ω is a set of pixel points in the image defect region;
mean value of gray scale m
The gray level mean value m of the image refers to a gray level mean value in a defect area, reflects the brightness of defect distribution, and has the formula:
wherein N represents the number of pixels in the image area, and f (i, j) represents the gray value of the pixel of the coordinate (i, j);
gray scale standard deviation sigma
The standard deviation sigma of the gray level of the image reflects the discrete degree of the gray level in the defect area, and the formula is as follows:
where m represents the average value of the gradations and N represents the total number of pixels.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides an end plug defect detection device based on an FPGA (field programmable gate array). An image acquisition device acquires images of an end plug in real time, and an FPGA main control module firstly performs noise reduction and background compensation on the acquired images and then performs defect feature extraction and classifies the extracted defect features. The device utilizes the characteristic that FPGA processes data at a high speed in parallel, and the high-speed accurate detection goes out the end plug defect, rejects unqualified end plug product from it, has effectually eliminated the hourglass of traditional people's eye detection method existence and has examined and the false retrieval defect, has improved end plug detecting system's real-time and precision. And FPGA hardware is parallel to a pipeline processing flow, so that the image data processing speed is increased. And a nondestructive testing mode is adopted, so that the quality of the end plug is effectively ensured.
In order to avoid the influence on defect identification caused by the problems of noise and uneven image gray scale introduced in the image acquisition process, the image is subjected to noise reduction and background compensation, and the detection accuracy is improved.
The method comprises the steps of segmenting defects in an image by combining a Soble operator with a double-threshold segmentation method, eliminating non-defects in the defects by morphological processing, extracting the characteristics of the defects, and finally identifying and splitting characteristic parameters of the defects by adopting an SVM classifier. The defect detection precision and efficiency are effectively improved, the product consistency is well guaranteed, and the intelligent and automatic degrees of the detection system are improved.
The trigger control module outputs a trigger signal according to the rotating speed information of the motor to trigger the linear array camera, so that the matching of the shooting rate of the linear array camera and the speed of the rotary detection table is ensured, and the quality of the shot image is improved.
Drawings
FIG. 1 is a schematic view of the detecting device of the present invention;
FIG. 2 is a block diagram of the detecting device of the present invention;
FIG. 3 is a block diagram of a signal patch panel;
FIG. 4 is a control flow diagram of the FPGA main control module;
FIG. 5 is a flow chart of the detection device;
FIG. 6 is a schematic diagram of a fast median filtering process;
FIG. 7 is a schematic diagram of a convolution kernel of a Soble operator;
FIG. 8 is a schematic diagram of a dilation operation;
FIG. 9 is a schematic diagram of the etching operation;
FIG. 10 is a schematic diagram of an SVM classifier.
Fig. 11 is a detection flowchart of the image processing unit.
The system comprises an area-array camera 1, a first camera fine-tuning device 2, a linear array camera 3, a second camera fine-tuning device 4, an end plug 5, a second linear annular light source 6, a first linear annular light source 7, a detection platform 8, an encoder 9, a motor 10, a signal adapter plate module 11, an FPGA main control module 12 and an upper computer 13.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which the invention is shown by way of illustration and not by way of limitation.
Referring to fig. 1 and 2, an end plug surface defect detection device based on an FPGA includes a rotation detection table, an image acquisition module, a signal adapter plate 11, an FPGA main control module 12, and an upper computer 13. The image acquisition module is connected with the input end of the signal adapter plate 11, the output end of the signal adapter plate 11 is connected with the FPGA main control module 12, and the FPGA main control module 12 is connected with the upper computer 13.
The rotary detection table comprises a detection platform 8, a motor 10 and a decoder which are horizontally arranged; the detection platform 8 is connected with the motor 10, the motor 10 drives the detection platform 8 to rotate at a constant speed, the motor 10 is connected with the input end of the decoder 9, the output end of the decoder 9 is connected with the FPGA main control module 12, and the decoder 9 collects the rotating speed information of the motor 10 and inputs the rotating speed information to the FPGA main control module 12.
The image acquisition module comprises an area-array camera 1, a first camera fine-tuning device 2, a linear array camera 3, a first annular light source 6, a second camera fine-tuning device 4 and a first linear annular light source 7. The first linear annular light source 7 is arranged at the center of the detection platform 8, the area-array camera 1 is positioned right above the first linear annular light source 7, and the first camera fine-tuning device 2 is connected with the area-array camera 1; the second linear annular light source 6 is horizontally arranged above the side of the detection platform 8 and used for irradiating the side face of the end plug, the linear array camera 3 is connected with the second linear annular light source 6, the second camera fine-tuning device 4 is connected with the linear array camera 3, and the linear array camera 3 and the area array camera 1 are both connected with the signal transfer board 11.
The linear array Camera 3 is a monochromatic linear array CCD Camera with resolution of 2048 and based on a Base Camera Link interface, and is provided with an object space telecentric lens;
the area-array Camera 1 is a monochrome area-array CCD Camera with the resolution of 192 ten thousand pixels and based on a Base Camera Link interface, and is provided with a zoom lens.
Referring to fig. 3, the signal adapting board 11 uses standard MDR26 interfaces and IDE interfaces for communication, the two MDR26 interfaces are used for connecting the area array CCD camera 1 and the line array camera 3, and the IDE interface is used for communicating with the FPGA main control module 12. The signal board is provided with two LVDS-to-TTL/COMS signal chips DS90CR288A for converting LVDS image signals from the area-array camera 1 and the line-array camera 3 into TTL signals; two TTL/COMS signal to LVDS signal conversion chips DS90LV047 are carried and used for converting TTL control signals from the FPGA main control module 12 into LVDS signals and sending the LVDS signals to the area-array camera 1 and the linear array camera 3, and performing configuration control on the area-array camera 1 and the linear array camera 3; in addition, two TTL/COMS and LVDS bidirectional signal conversion chips DS90LV019 and a data selector chip 74HC4052 are mounted for serial communication between the FPGA main control module 12 and the area-array camera 1 and the line-array camera 3.
The FPGA main control module 12 comprises a motor controller module, a trigger control module, a serial communication module, an image acquisition control module, an image processing module and a main controller module;
the trigger control module receives the speed information of the stepping motor collected by the encoder 9 for processing, and outputs a trigger signal to the linear CCD camera 3 through the signal adapter plate 11 for triggering.
The motor control module is used for receiving the motor control signal output by the main controller module and outputting a square wave model to control the motor according to the motor control signal.
The image acquisition control module is used for receiving the image information of the image acquisition module and storing the image information into SDRAM.
The image processing module comprises an image preprocessing unit, a feature extraction unit and a classification unit.
The image preprocessing unit firstly adopts an improved median filtering algorithm to perform noise reduction processing on the image data. The background is then compensated by means of polynomial fitting.
The feature extraction unit comprises an image segmentation subunit, a morphology processing subunit and a defect extraction subunit which are sequentially connected;
firstly, extracting suspected defects in the filtered and background-compensated image by adopting a Soble operator combined double-threshold segmentation method by an image segmentation subunit; then the morphological processing subunit removes non-defects in the suspected defects by adopting an image morphological processing method, and the defect feature extraction subunit extracts the features of the defects.
And the classification unit identifies and classifies the extracted defect characteristics by adopting an SVM classifier.
The motor 10 is a stepping motor.
The working principle of the FPGA-based end plug surface defect detection apparatus of the present invention is described in detail below.
1. And (5) configuring the system.
Referring to fig. 4, after the device is powered on, the FPGA main control module 12 acquires configuration information from the programming configuration chip to initialize, and after the initialization is completed, the response host computer establishes connection with the device. After the upper computer receives the response of the FPGA main control module 12, the configuration parameters of the area-array Camera 1 and the line-array Camera 3, the serial communication configuration parameters and the control parameters of the motor 10 are packed according to the ethernet protocol and are sent to the main controller module in the FPGA main control module 12 through the RJ45 ethernet interface, the main controller module receives the configuration information data packet and then analyzes the data, the configuration parameters of the cameras and the serial communication configuration parameters are repacked according to the serial communication protocol and are sent to the signal adapter board module 11 through the IDE interface, the configuration data are converted into Camera Link protocol data through the LVDS and TTL bidirectional conversion chip and are respectively sent to the area-array Camera 1 and the line-array Camera 3 through the two MDR26 interfaces, and when the signals that the Camera configuration is completed are received, the FPGA main control module 12 sends feedback information to the upper computer to mark that the system configuration is completed. After the system configuration is completed, the FPGA main control module 12 is in a standby state.
2. End plug images were acquired.
After the upper computer sends out a system starting operation signal, the FPGA main control module 12 responds to the signal and starts to acquire an end plug image. The image acquisition of the end plug is divided into two parts, namely acquiring the image of the hole of the end plug and acquiring the 360-degree image of the side surface of the end plug.
As shown in fig. 11, an end plug hole image is first acquired. Under the static state of the rotary platform and under the irradiation of the light source 7, the area array Camera 1 collects an end plug hole image, transmits the image to the signal adapter plate 11 through a standard MDR26 interface, converts LVDS (low voltage differential signaling) image signals based on a Camera Link protocol into TTL (transistor-transistor logic) type signals, and transmits the TTL type signals to the image collection control module in the FPGA main control module 12, and the image collection control module stores received image information into SDRAM (synchronous dynamic random access memory).
After the hole images are collected, the main controller module outputs control signals, the motor control module receives the control signals and outputs square wave signals, the motor 10 is started, the motor 10 drives the detection platform 8 to rotate, at the moment, the encoder 9 collects the rotating speed information of the motor 10, the speed information is transmitted to the trigger control module, the trigger control module outputs trigger signals, the trigger signals are sent to the linear camera 3 through the signal adapter plate 11 to trigger the linear camera, the linear camera 3 starts to collect the side surface images of the end plugs, the collected side surface images of the end plugs are converted into TTL type signals through the signal adapter plate 11 and sent to the image collection control module in the FPGA main control module 12, and the image collection control module stores the received image information into SDRAM.
3. Image defect detection
Due to the hardware pipeline processing characteristic of the FPGA, when the image acquisition control module in the FPGA main control module 12 obtains the images of the holes and the side surfaces of the end plugs, the image acquisition control module is divided into two branches to simultaneously perform image processing on the images of the holes and the side surfaces of the end plugs. Firstly, designing a data template by using an ALTSIFT _ TAPS IP core, reading out image data on the side surface of the end plug from SDRAM by using an image processing module, carrying out filtering processing on the image data by using a rapid median filtering algorithm, then correcting the image gray scale by adopting a polynomial fitting mode, and then extracting the defects of the end plug by using a Soble operator in combination with a dual-threshold segmentation method; if no defect exists, the defect detection is finished, the detection result of 'no defect' is stored in the SDRAM, if a defect exists and a plurality of defects exist, then the length-width ratio T, the circularity E, the area A, the gray mean value m and the gray standard deviation delta of the defect on the side surface of the end plug are sequentially extracted for each defect, and finally the characteristic data are stored in the SDRAM. Meanwhile, the same processing is carried out on the terminal hole plugging image, and the detection result is stored in the SDRAM. Then, according to the results of the previous steps, there are 4 cases as follows: (1) both the end plug holes and the side surfaces have defects; (2) the end plug holes have defects, and the side surfaces have no defects; (3) the end plug holes have no defects, and the side surfaces have defects; (4) neither the end plug holes nor the side surfaces are defective. And aiming at the first three conditions, inputting all the characteristic parameters of each divided defect into a built SVM classifier, outputting the category of the defect through the identification and classification of the classifier, and storing the result into SDRAM. And finally, reading the detection result from the SDRAM, packaging the detection result by using an Ethernet protocol, and sending the detection result to the upper computer 13 through an RJ45 Ethernet interface.
As shown in fig. 5, the following describes in detail four steps of end plug image preprocessing, defect feature extraction, and defect identification and classification in the end plug defect detection process.
End plug image preprocessing
As shown in fig. 6, since various types of noise are inevitably introduced into an image, and the subsequent image processing is adversely affected, it is necessary to perform noise reduction processing on the image. The invention adopts an improved median filtering algorithm to carry out noise reduction processing on image data. And then, combining a programming environment, fully utilizing the parallel characteristic of the FPGA, designing by using a hardware description language Verilog HDL and realizing a median filtering algorithm, and denoising the end plug image.
Step 1, reading image data from SDRAM and sending the image data to a 3 x 3 template generation module, obtaining a pixel matrix with 3 rows and 3 columns for each pixel point in the image data, respectively sorting the obtained image data of each row, and respectively solving a maximum value, a median value and a minimum value, wherein one clock cycle is consumed due to the parallelism of FPGA program execution;
step 2, sorting the 3 maximum values, the 3 minimum values and the 3 median values obtained in the step 1 respectively, and calculating the minimum value in the maximum values, the maximum value in the minimum values and the median value in the median values;
and 3, sequencing the three data obtained in the step 2, wherein the obtained middle numerical value is the median of 9 pixels in the neighborhood. The median filtering of a single pixel point just needs to be completed by consuming three clock cycles, and the filtering efficiency is greatly improved.
Due to the problems of different axes of rotation of the end plugs, uneven illumination of the light source and the like, the acquired image may have uneven gray distribution, and the uneven gray can cause serious influence on subsequent threshold segmentation, so that background compensation needs to be performed on the image. Since the gray level distribution of the background of the end plug is random and has only a single direction, the background is compensated by adopting a polynomial fitting mode.
Defect feature extraction
After the image is preprocessed, the noise of the image is suppressed. The defects need to be detected next, and the defect feature extraction is mainly divided into three parts:
1. image segmentation
The image segmentation is an important link in defect extraction, and because the proportion of defect parts is small and the defect parts are distributed at two ends, the defects are segmented from the image background by combining a Soble operator with a dual-threshold segmentation method. The Soble operator is used as a discrete difference operator and can be used for calculating the size and the direction of the gray value gradient of the image, and the Soble operator is used for any pixel point in the image to generate a normal vector and a gray gradient vector. Fig. 6 shows a convolution kernel of the cable operator, where P is a pixel matrix after noise reduction.
As shown in FIG. 7, this operator includes two convolution operators, X-direction (Sx) and Y-direction (Sy), respectively, convolution kernels if G is used X And G Y Representing the gray gradient values in the horizontal and vertical directions, the calculation formula is as follows:
the magnitude and direction of the gradient value of each pixel in the image data may be calculated by the following formula:
the following describes the implementation of the image segmentation algorithm in detail with reference to FPGA hardware logic.
(1) Calculating G according to the formula X And G Y . First calculate S X And S Y And a moldThe product of each row or column of the plate is calculated by omitting the negative sign in the template and processing as a positive number because G is finally calculated X And G Y Neither the square nor the presence of the negative sign affects the result of the calculation, which takes a total of two clock cycles.
(2) Calculating G X And G Y The sum of the squares of (c). The multiplication of the step can not be replaced by mobile operation, and a hardware multiplier embedded in the FPGA is directly used for operation, so that one clock cycle is consumed.
(3) Calculating machineThe ALTSQRT IP core is used for squaring operations, consuming one clock cycle.
(4) According to a set double threshold value T 1 、T 2 (T 1 ＜T 2 ) And realizing the judgment of the edge. Judging the gray scale gradient value obtained by the previous step, and if the gray scale gradient value is larger than a set threshold value T 2 Or less than a set threshold value T 1 If so, the pixel is an edge and is assigned a value of 1, otherwise, the pixel is assigned a value of 0.
(5) After a binary image of the end plug image is obtained, carrying out defect positioning and segmentation processing on the end plug image, positioning the end plug defect by adopting a vertex method, traversing the end plug image data, and determining the coordinates { X _ min, Y _ min } at the upper left corner and { X _ max, Y _ max } at the lower right corner of a defect area, namely finishing the primary positioning of the defect; the rectangular area between { X _ min-m, Y _ min-m } and { X _ max + m, Y _ max + m } on the end plug image, where m represents the number of expanded pixel values, is further extracted as a defect area.
In the algorithm implementation process, addition logic is skillfully adopted to replace multiplication operation, meanwhile, the occurrence of negative numbers is avoided, the idea of pipeline program design is fully utilized, and the edge detection and judgment of a single pixel point can be completed only by consuming 5 clock cycles for initial operation, so that the segmentation of the end plug image defects is realized.
2. Morphological treatment
After the end plug defects are detected through image segmentation, some non-defect points can be doped, so that the images can be post-processed by using a morphological processing method to eliminate the non-defect points.
The image morphology mainly utilizes the morphological characteristics of the target graph to change the target graph so as to obtain an ideal processing result. The two most basic processing procedures in image morphology are erosion and expansion, wherein erosion is the operation Θ of a by using a structural element B and is defined as:may be represented as fig. 4-9; the expansion is carried out by using the structural element B to AThe operation, defined as:can be represented as fig. 8 and 9:
as shown in fig. 9, on the basis of the dilation-erosion operation, an on operation and an off operation may be generated. Firstly, carrying out corrosion operation, namely carrying out expansion operation, namely opening operation, and mainly eliminating long, narrow and small parts in an image; firstly, expansion operation is carried out, and then corrosion operation is carried out, namely closed operation is carried out, and the method is mainly used for connecting broken outlines or filling fine blank areas. The invention utilizes the on operation to eliminate the non-defect points in the image, so as to facilitate the next step of feature extraction.
3. Feature extraction
Common end plug defects include scratches, bruises, foreign objects, burrs, and other defects. The geometrical characteristics of scratch defects are obvious, the characteristics of impact defects are complex, the gray scale characteristics of pit defects are obvious, and the morphological characteristics of foreign matter defects and burr defects are obvious. Therefore, the length-width ratio T, the circularity E, the area a, the gray mean m, and the gray standard deviation δ are selected as characteristic parameters and extracted.
● Length to width ratio T
The length-width ratio T of the defect refers to the ratio of the length to the width of the minimum circumscribed rectangle of the defect area, and the formula is as follows:
where L and W represent the length and width of the defect region, respectively.
● Degree of circularity E
The circularity E is a parameter for describing how similar the defect shape is to a circular shape, and is expressed by the formula:
wherein P is the perimeter of the defect region, and E is 1 when the defect shape is circular; the larger the difference between the defect shape and the circular shape is, the smaller E is;
● Area A
The area of the image defect is a variable describing the size of the whole defect area, and the number of pixel points occupied by the defect area is generally calculated by the following formula:
wherein Ω is the set of pixels in the image defect region.
● Mean value of gray scale m
The gray level mean value m of the image refers to a gray level mean value in a defect area, reflects the brightness of defect distribution, and has the formula:
wherein N represents the number of pixels in the image area, and f (i, j) represents the gray value of the pixel of the coordinate (i, j);
● Gray scale standard deviation sigma
The standard deviation sigma of the gray level of the image reflects the discrete degree of the gray level in the defect area, and the formula is as follows:
where m represents the average value of the gradations and N represents the total number of pixels.
Defect identification and classification
After the extraction of the end plug surface defect characteristics is completed, a classifier is required to classify and identify the defects. The common classifiers mainly include: support Vector Machines (SVMs), binary trees, naive bayes classifiers. The method selects an SVM classifier to identify and classify the end plug defects. The classical support vector machine is a two-class classifier, and a multi-class SVM classifier is established by utilizing an indirect method because various defects such as scratches, bruises, pits, foreign matters and burrs need to be classified, namely n classes are classified, the classifier needs to be designed, the interior of the classifier is judged by adopting a voting mechanism, and the structural schematic diagram of the SVM classifier is shown in FIG. 10.
Five characteristic parameters of length-width ratio T, circularity E, area A, gray mean m and gray standard deviation sigma are input, and output parameters y 1-y 5 respectively represent scratch, bruise, pit, foreign matter and burr type defects.
Test result display and update
After the upper computer receives the detection result data packet output by the FPGA main control module 12, the upper computer analyzes the data packet, displays the detection result of the current end plug on one hand, and stores the detection result in a background database on the other hand. And the detection interface displays the label of the current end plug and displays the defect type and the defect number of the current end plug.
The invention takes the FPGA main control module 12 as a core to finish the acquisition and pretreatment of the end plug image, the feature extraction and the identification and classification of the defects, thereby finishing the detection of the defects of the end plug. Due to the characteristics of high speed and real-time performance of the FPGA, the method has stronger real-time performance and higher defect identification accuracy.
The invention fully utilizes the characteristic that the FPGA processes data at a high speed in parallel, acquires the images of the end plugs in real time, accurately detects the defects of the end plugs at a high speed, eliminates unqualified end plug products, effectively eliminates the defects of missing detection and false detection existing in the traditional human eye detection method, and improves the real-time performance and the accuracy of an end plug detection system.
The machine vision technology is applied to the end plug defect detection, and the end plug defect detection system developed based on the machine vision technology has the characteristics of non-contact and no damage, can ensure that the surface of the end plug is not damaged while detecting the surface defect of the end plug, and effectively ensures the quality of the end plug.
Compared with the traditional detection mode of the end plug defect based on human eyes, the detection system provided by the invention can liberate people from the detection work with repeatability and high strength, eliminates the influence of the visual fatigue of people on the detection result, effectively improves the precision and efficiency of defect detection, better ensures the consistency of products, and improves the intelligence and automation degree of the detection system.
The upper computer of the detection system has a data management function, and workers can analyze past fault data, so that production links which are prone to faults can be quickly located, and the detection system has important guiding significance for the production process of the end plugs.
The above-mentioned contents are only for illustrating the technical idea and processing flow of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea and processing flow proposed by the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. An end plug defect detection device based on FPGA is characterized by comprising a rotary detection table, an image acquisition module, an upper computer (13) and an FPGA main control module (12) containing an image processing module; the FPGA main control module is respectively interacted with the image acquisition module and the upper computer (13);
the image acquisition module comprises an area-array camera for acquiring images of the holes of the end plugs and a line-array camera for acquiring images of the side faces of the end plugs; the area-array camera is positioned right above the rotary detection table, and the line-array camera is positioned laterally above the rotary detection table;
the FPGA main control module is used for transmitting the collected images to the image processing module and transmitting the defects detected by the image processing module to an upper computer (13);
the image processing module is used for detecting defects in the image and comprises an image preprocessing unit, a feature extraction unit and a classification unit;
the image preprocessing unit is used for carrying out noise reduction and background compensation on the image acquired by the image acquisition module;
the feature extraction unit is used for extracting defect features of the filtered and background-compensated image;
the classification unit is used for identifying and classifying the extracted defect characteristics.
2. The FPGA-based end plug defect detection device of claim 1, wherein the feature extraction unit comprises an image segmentation subunit, a morphology processing subunit and a defect extraction subunit which are connected in sequence;
the image segmentation subunit is used for extracting suspected defects in the image;
the morphology processing subunit is used for removing non-defects in the suspected defects;
the defect feature extraction subunit is used for extracting the aspect ratio feature, the circularity feature, the area feature, the gray mean feature and the gray standard deviation feature of the defect.
3. The FPGA-based end plug defect detecting device of claim 1, wherein the rotary inspection station comprises an inspection platform (8) and a motor (10); the motor (10) is arranged below the detection platform and drives the detection platform (8) to rotate.
4. The FPGA-based end plug defect detection device is characterized in that an encoder (9) is connected to the motor (10), and the encoder (9) is connected with the FPGA main control module (12);
the FPGA main control module (12) also comprises a motor control module and a trigger control module; the motor control module is used for controlling the motor (10); the trigger control module is used for receiving the rotating speed information of the motor (10) collected by the encoder (9) and outputting a line trigger signal to trigger the linear array camera according to the rotating speed information.
5. The FPGA-based end plug defect detecting device of claim 1, further comprising a first light source (7) and a second light source (6); the first light source (7) is arranged on the detection platform and vertically irradiates the hole of the end plug; the second light source is arranged above the side of the detection platform (8) and horizontally irradiates the side face of the end plug.
6. The FPGA-based end plug defect detection device of claim 1, wherein the image acquisition module interacts with an FPGA main control module (12) through a signal patch board (11); the signal adapter plate (11) comprises a control signal module, a serial communication module and an image data module.
7. The FPGA-based end plug defect detection device of claim 1, wherein the area-array camera (1) and the line-array camera (3) are both connected with a camera fine adjustment device for adjusting shooting angles.
8. A method for detecting a defect detection device of an end plug according to claim 2, comprising the steps of:
s1, collecting an image of an object to be detected;
s2, carrying out noise reduction on the acquired image by adopting an improved median filtering algorithm, and compensating the background by adopting a polynomial fitting mode;
s3, extracting suspected defects from the image obtained in the step S2 by adopting a Soble operator combined double-threshold segmentation method;
s4, eliminating non-defects in the suspected defects by adopting opening and closing operation;
s5, extracting aspect ratio features, circularity features, area features, gray mean features and gray standard deviation features of the defects in the suspected defects;
and S6, recognizing and classifying the defect characteristics extracted in the step S5 by adopting an SVM classifier.
9. The detection method according to claim 8, wherein the specific method for extracting suspected defects by combining the Soble operator and the dual-threshold segmentation method in step S3 is as follows:
1. edge gradient calculation
Calculating gradient values in the x direction and the y direction and gradient directions of each pixel point in the image, wherein the calculation formula is as follows:
wherein P is a pixel matrix after noise reduction, G X And G Y Respectively representing the gray gradient values in the horizontal direction and the vertical direction, G is the size of the gradient value of the processing pixel point, and theta represents the gradient direction;
2. defect edge detection
Processing the gradient value of the pixel point by adopting a dual-threshold segmentation method, determining whether the pixel point is a defect edge, and outputting a binary image, wherein the calculation formula is as follows:
wherein, P m Is the value of a pixel, T 1 、T 2 ,T 1 <T 2 For a set dual threshold, if the gray value G of the pixel point>T 2 Or G<T 1 If the pixel point is the edge of the defect, otherwise, the pixel point is the normal background;
3. defect localization and segmentation
After obtaining a binary image of the end plug image, performing defect positioning and segmentation processing on the end plug image, traversing the end plug image data, and determining the upper left corner coordinate { X ] of a defect area min ,Y min The coordinates of the lower right corner { X } max ,Y max Finishing the primary positioning of the defects; further extracting { X in end plug image min -m,Y min -m } and { X } max +m,Y max A rectangular area between + m where m represents the number of expanded pixel values as a defective area.
10. The method according to claim 8, wherein the defect of step S5 is extracted by the following method:
length to width ratio T
The length-width ratio T of the defect refers to the ratio of the length to the width of the minimum circumscribed rectangle of the defect area, and the formula is as follows:
wherein L and W represent the length and width of the defect region, respectively;
degree of circularity E
The circularity E is a parameter for describing how similar the defect shape is to a circular shape, and is expressed by the formula:
wherein P is the perimeter of the defect region, and E is 1 when the defect shape is circular; the larger the difference between the defect shape and the circular shape is, the smaller E is;
area A
The area of the image defect is a variable describing the size of the whole defect area, and the number of pixel points occupied by the defect area is generally calculated by the following formula:
wherein Ω is a set of pixel points in the image defect region;
mean value of gray scale m
The gray level mean value m of the image refers to a gray level mean value in a defect area, reflects the brightness of defect distribution, and has the formula:
wherein N represents the number of pixels in the image area, and f (i, j) represents the gray value of the pixel of the coordinate (i, j);
gray scale standard deviation sigma
The standard deviation sigma of the gray level of the image reflects the discrete degree of the gray level in the defect area, and the formula is as follows:
where m represents the average value of the gradations, and N represents the total number of pixels.
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