CN107959649A - Timing synchronization in ofdm system receiver simplifies method - Google Patents

Timing synchronization in ofdm system receiver simplifies method Download PDF

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Publication number
CN107959649A
CN107959649A CN201711329685.4A CN201711329685A CN107959649A CN 107959649 A CN107959649 A CN 107959649A CN 201711329685 A CN201711329685 A CN 201711329685A CN 107959649 A CN107959649 A CN 107959649A
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mrow
msub
mtd
signal
value
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CN107959649B (en
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李睿
唐晓柯
王海玉
王连成
周春良
迟海明
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State Grid Corp of China SGCC
State Grid Information and Telecommunication Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
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State Grid Corp of China SGCC
State Grid Information and Telecommunication Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2662—Symbol synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2602—Signal structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses the timing synchronization in a kind of ofdm system receiver to simplify method, which is a kind of symbol timing synchronization method based on special training sequence, is comprised the following steps：Receive every signal value R of signaln+kAccumulating operation is carried out after taking absolute value, obtains the first operation result；Length is the value T of each sign bit of local special sequence of lkIt is sign optimization computings, every signal value R for receiving signaln+kWith sign (Tk) value does multiplication operation, and then does accumulating operation and take absolute value, obtain the second operation result；Second operation result and first operation result are divided by, to division result Q 'nSymbol timing signal is obtained after carrying out peak detection.Timing synchronization in ofdm system receiver simplifies method and simplifies timing synchronization algorithm and its hardware realization structure based on training sequence.

Description

Timing synchronization in ofdm system receiver simplifies method
Technical field
The present invention relates to the communications field, the timing synchronization simplification side in more particularly to a kind of ofdm system receiver Method.
Background technology
Orthogonal Frequency Division Multiplexing (OFDM) is the high speed transmission technology under a kind of wireless environment.Technological core is to break a channel into High-speed data signal, is converted into parallel low speed sub-data flow by some orthogonal sub-channels, be modulated on each of the sub-channels into Row transmission.Orthogonal signalling can so reduce the phase between subchannel by being separated in receiving terminal using correlation technique Mutually interference.Signal bandwidth on per sub-channels is less than the correlation bandwidth of channel, therefore can regard flatness as per sub-channels Decline, so as to eliminate intersymbol interference, and since the bandwidth of every sub-channels is only the sub-fraction of former channel width, Channel equalization becomes relatively easy.Due to these features, the technology is particularly suitable for there are multipath transmisstion and Doppler frequency shift Wireless mobile channel communicates, and is the core technology of current fourth generation mobile communication technology.
In an ofdm system, due to keep the orthogonality between each sub-channel signal, receiving terminal is needed when signal demodulates Synchronism that will be very high.The deviation of timing synchronization can cause intersymbol interference, can cause under serious situation between subcarrier Interference, so as to cause the decline of system performance.
Existing ofdm system symbol timing synchronization method is all based on the timing synchronization algorithm of training sequence, is to send out Special training sequence known to sending end transmission data, receives complete training symbol to carry out the algorithm of timing synchronization. The existing timing synchronization algorithm accuracy based on special training sequence is higher, but computation complexity is too during hardware realization Greatly.
Every signal of reception signal carries out accumulating operation after taking absolute value, and obtains an operation result, receives signal Each signal adds up and takes absolute value after making multiplication operation with local special training every signal of sequence, obtains a computing knot Fruit, two operation results are divided by, symbol timing signal is obtained after peak detection.
The symbol timing signal algorithm is as follows：
Wherein, QnIt is symbol timing signal, R(n+k)It is to receive signal, TkIt is local special training sequence, l is local special Training sequence length, receives signal R(n+k)With local training sequence TkAll it is real number signal.
Illustrate by 1024 ofdm system of a sub- variable number, when taking the timing synchronization of standard, often make Once successful symbol timing detection is, it is necessary to make 1024 multiplication, if complex multiplication, multiplier number will turn over 4 times, with And 1024 cumulative and computings that take absolute value of rear end.During general Digital Implementation multiplier, multiplier and multiplicand are all quantized into n The signed number or unsigned number of position bit wide, so, quantization bit wide is wider, and the complexity of multiplication operation is higher.
Although have at present it is various there is simplified algorithm to occur, be essentially all for rear end peak detection and detection method On simplification, the real arithmetic that front end mutually multiplies accumulating all be difficult get around.The hardware realization of this timing synchronization algorithm is Extremely complex.
The information for being disclosed in the background section is merely intended to understanding of the increase to the general background of the present invention, without answering It has been the prior art well known to persons skilled in the art when being considered as recognizing or implying the information structure in any form.
The content of the invention
It is an object of the invention to provide the timing synchronization in a kind of ofdm system receiver to simplify method, simplifies Timing synchronization algorithm and its hardware realization structure based on training sequence.
To achieve the above object, the present invention provides a kind of timing synchronization to simplify method, which is a kind of Based on the symbol timing synchronization method of special training sequence, comprise the following steps：
Receive every signal value R of signaln+kAccumulating operation is carried out after taking absolute value, obtains the first operation result；
Length is the value T of each sign bit of local special sequence of lkSign optimization computings are done, algorithm is as follows；
Every signal value R for receiving signaln+kWith sign (Tk) value does multiplication operation, and then does accumulating operation and take Absolute value, obtains the second operation result；And
Second operation result and first operation result are divided by, to division result Q 'nAfter carrying out peak detection Obtain symbol timing signal, Q 'nFormula is as follows：
Preferably, in above-mentioned technical proposal, every signal for receiving signal and sign (Tk) when doing multiplication operation, no Need multiplier, it is only necessary to which if sentences can be achieved：As sign (Tk) be 1 when, to it is described reception signal this signal value Rn+k Initial value is taken just to obtain the result of the multiplication operation；As sign (Tk) be -1 when, to it is described reception signal this signal value Rn+k Negate the result for just obtaining the multiplication operation；As sign (Tk) be 2 when, to it is described reception signal this signal value Rn+kInto Row displacement just obtains the result of the multiplication operation；As sign (Tk) be -2 when, to it is described reception signal this signal value Rn+kShifted and negated the result for just obtaining the multiplication operation.
Compared with prior art, the present invention has the advantages that：
Multiplier is not required, enormously simplify the algorithm and its hardware realization knot of the timing synchronization based on training sequence Structure.
Brief description of the drawings
Fig. 1 is the hardware principle of the symbol timing synchronization method based on training sequence according to an embodiment of the present invention Figure.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in detail, it is to be understood that the guarantor of the present invention Protect scope and from the limitation of embodiment.
Explicitly indicated that unless otherwise other, otherwise in entire disclosure and claims, term " comprising " or its change Change such as "comprising" or " including " etc. and will be understood to comprise stated element or part, and do not exclude other members Part or other parts.
The present invention proposes a kind of calculating signal-timing method, makes simplification to computing, multiplier is cast aside from principle not With hardware realization complexity can be greatly simplified.
Fig. 1 is the hardware of the simplification algorithm of the timing synchronization based on training sequence according to an embodiment of the present invention Schematic diagram.
The ingenious part of the algorithm is：Local special training sequence TkIt is the additional character sequence that have passed through well-designed mistake Row, are usually that autocorrelation performance is very good, the sequence composition that cross correlation can be bad.Receive signal RnIt is after over-sampling Value, this signal cannot simplify.But local training sequence TkIt then can in advance do and optimize, be allowed to and RnAfter multiplication, symbol is fixed When signal results it is unaffected, so as to simplify fall multiplier.
Timing synchronization algorithm based on special training sequence is as follows：
1, receive every signal value R of signaln+kAccumulating operation is carried out after taking absolute value, obtains the first operation result；
2, length is the value T of each sign bit of local special sequence of lkSign optimization computings are done, algorithm is as follows；
If local special sequence TkThe value of each sign bit is more than or equal to 0 and is less than 1, is directly quantized into 1.If TkEach The value of sign bit is more than 1, is directly quantized into 2.If local special sequence TkThe value of each sign bit is more than or equal to -1 and is less than 0, Directly it is quantized into -1.If TkThe value of each sign bit is less than -1, is directly quantized into -2.Sign bit is both remained after so handling Attribute, while also remain amplitude attribute.
3, receive every signal value R of signaln+kWith sign (Tk) value does multiplication operation, and then does accumulating operation and take absolutely To value, the second operation result is obtained；And
4, the second operation result and the first operation result are divided by, to division result Q 'nAccorded with after carrying out peak detection Number timing signal, Q 'nFormula is as follows.
According to formula analysis, multiplier is not required in algorithm.Initial value is taken with an if sentence or is negated or shifting processing, you can Instead of the multiplier of original n positions, operand is set to have obtained the simplification of essence.
Peak detection is greatly simplified after simplifying above, with two peak intervals is a FFT/ during judgement IFFT is used as judgment condition.
Timing synchronization in the ofdm system receiver simplifies method and multiplier is not required, and enormously simplify and is based on The algorithm and its hardware configuration of the timing synchronization of training sequence.
It is foregoing to the present invention specific exemplary embodiment description be in order to illustrate and illustration purpose.These descriptions It is not wishing to limit the invention to disclosed precise forms, and it will be apparent that according to the above instruction, can be much changed And change.The purpose of selecting and describing the exemplary embodiment is that explain that the certain principles of the present invention and its reality should With so that those skilled in the art can realize and utilize the present invention a variety of exemplaries and Various chooses and changes.The scope of the present invention is intended to be limited by claims and its equivalents.

Claims (2)

  1. It is a kind of symbol based on special training sequence 1. the timing synchronization in a kind of ofdm system receiver simplifies method Time synchronization method, it is characterised in that comprise the following steps：
    Receive every signal value R of signaln+kAccumulating operation is carried out after taking absolute value, obtains the first operation result；
    Length is the value T of each sign bit of local special sequence of lkSign optimization computings are done, algorithm is as follows；
    <mrow> <mi>s</mi> <mi>i</mi> <mi>g</mi> <mi>n</mi> <mrow> <mo>(</mo> <msub> <mi>T</mi> <mi>k</mi> </msub> <mo>)</mo> </mrow> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <mn>1</mn> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mn>0</mn> <mo>&amp;le;</mo> <msub> <mi>T</mi> <mi>k</mi> </msub> <mo>&lt;</mo> <mn>1</mn> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mn>2</mn> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>T</mi> <mi>k</mi> </msub> <mo>&gt;</mo> <mn>1</mn> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>-</mo> <mn>1</mn> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mo>-</mo> <mn>1</mn> <mo>&amp;le;</mo> <msub> <mi>T</mi> <mi>k</mi> </msub> <mo>&lt;</mo> <mn>0</mn> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>-</mo> <mn>2</mn> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>T</mi> <mi>k</mi> </msub> <mo>&lt;</mo> <mo>-</mo> <mn>1</mn> </mrow> </mtd> </mtr> </mtable> </mfenced> </mrow>
    Every signal value R for receiving signaln+kWith sign (Tk) value does multiplication operation, and then does accumulating operation and take definitely Value, obtains the second operation result；And
    Second operation result and first operation result are divided by, to division result Q 'nAccorded with after carrying out peak detection Number timing signal, Q 'nFormula is as follows：
    <mrow> <msubsup> <mi>Q</mi> <mi>n</mi> <mo>&amp;prime;</mo> </msubsup> <mo>=</mo> <mfrac> <mrow> <msubsup> <mi>&amp;Sigma;</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>0</mn> </mrow> <mrow> <mi>l</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <msub> <mi>R</mi> <mrow> <mo>(</mo> <mi>n</mi> <mo>+</mo> <mi>k</mi> <mo>)</mo> </mrow> </msub> <mo>&amp;times;</mo> <mi>s</mi> <mi>i</mi> <mi>g</mi> <mi>n</mi> <mrow> <mo>(</mo> <msub> <mi>T</mi> <mi>k</mi> </msub> <mo>)</mo> </mrow> </mrow> <mrow> <msubsup> <mi>&amp;Sigma;</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>0</mn> </mrow> <mrow> <mi>l</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>|</mo> <msub> <mi>R</mi> <mrow> <mo>(</mo> <mi>n</mi> <mo>+</mo> <mi>k</mi> <mo>)</mo> </mrow> </msub> <mo>|</mo> </mrow> </mfrac> <mo>.</mo> </mrow>
  2. 2. the symbol timing synchronization method according to claim 1 based on special training sequence, it is characterised in that described to connect Every signal of the collection of letters number and sign (Tk) when doing multiplication operation, it is not necessary to multiplier, it is only necessary to which if sentences can be achieved：
    As sign (Tk) be 1 when, to it is described reception signal this signal value Rn+kInitial value is taken just to obtain the knot of the multiplication operation Fruit；
    As sign (Tk) be -1 when, to it is described reception signal this signal value Rn+kNegate the knot for just obtaining the multiplication operation Fruit；
    As sign (Tk) be 2 when, to it is described reception signal this signal value Rn+kShifted and just obtain the multiplication operation As a result；
    As sign (Tk) be -2 when, to it is described reception signal this signal value Rn+kShifted and negated and just obtain the phase The result of multiplication.
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CN114374591A (en) * 2022-03-17 2022-04-19 北京科技大学 Low-complexity OFDM symbol synchronization method and synchronization device

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CN111064686A (en) * 2018-10-16 2020-04-24 力同科技股份有限公司 Symbol timing synchronization method and device
CN111064686B (en) * 2018-10-16 2022-05-27 力同科技股份有限公司 Symbol timing synchronization method and device
CN114374591A (en) * 2022-03-17 2022-04-19 北京科技大学 Low-complexity OFDM symbol synchronization method and synchronization device
CN114374591B (en) * 2022-03-17 2022-07-01 北京科技大学 Low-complexity OFDM symbol synchronization method and synchronization device

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