CN107958100A - Calculate the method, apparatus and computer-readable medium of crust steady state heat resistance - Google Patents
Calculate the method, apparatus and computer-readable medium of crust steady state heat resistance Download PDFInfo
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- CN107958100A CN107958100A CN201711080654.XA CN201711080654A CN107958100A CN 107958100 A CN107958100 A CN 107958100A CN 201711080654 A CN201711080654 A CN 201711080654A CN 107958100 A CN107958100 A CN 107958100A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/10—Geometric CAD
- G06F30/17—Mechanical parametric or variational design
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- G—PHYSICS
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- G06F2119/08—Thermal analysis or thermal optimisation
Abstract
A kind of method, apparatus and computer-readable medium of the crust steady state heat resistance for calculating power module, the power module include multiple layerings, and the method for the crust steady state heat resistance for calculating power module includes：Obtain the parameter of the multiple layering；The thermal resistance of the multiple layering is calculated according to the parameter of the multiple layering based on thermal diffusion angle principle；According to the crust steady state heat resistance of power module described in the thermal resistance calculation of the multiple layering.By the thermal resistance for calculating the multiple layering according to the parameter of the multiple layering based on thermal diffusion angle principle, crust steady state heat resistance calculating can be achieved in the threedimensional model that power module need not be established, and is shortened compared to conventional method and calculates time and the versatility with higher.
Description
Technical field
A kind of this disclosure relates to power device technology field, and in particular to side for the crust steady state heat resistance for calculating power module
Method, calculate power module crust steady state heat resistance device and computer-readable medium.
Background technology
With the requirement of present energy-saving and environment-friendly social development, energy-saving and emission-reduction become the technology that enterprise widelys popularize.Power
Current transformer is an important technology of energy-saving and emission-reduction.Power converter is applied to be driven in industry-by-industry, such as Switching Power Supply, motor
Dynamic, uninterrupted power source (UPS, Uninterruptible Power Supply), photovoltaic DC-to-AC converter etc..Power module is as power
The core of current transformer, the reliability of the whole power converter of fine or not direct relation of its thermal reliability, so the heat of power module
Design is very important part in current transformer design.In practical applications, the junction temperature Tj of power module be cannot be by direct
Measurement means and obtain, and often to be calculated by crusting steady state heat resistance Rjc, and the actual measurement for the steady state heat resistance that crusts is not
Manpower and materials are only spent, and the testing time is grown, and concurrently there are the deviation of the test result produced by manual operation mistake.
So not only can quick response, but also testing cost can be greatlyd save in time using emulation tool.
Conventional method needs first to establish complete and detailed three of power module when calculating the thermal characteristic of power module
Dimension module, it is not higher using only threshold, and also it is also relatively time consuming to establish threedimensional model.
The content of the invention
In view of this, present disclose provides a kind of method for the crust steady state heat resistance for calculating power module, the power mould
Block includes multiple layerings, the described method includes：Obtain the parameter of the multiple layering；Based on thermal diffusion angle principle according to described more
The parameter of a layering calculates the thermal resistance of the multiple layering；According to the knot of power module described in the thermal resistance calculation of the multiple layering
Shell steady state heat resistance.
Preferably, the parameter of the multiple layering includes one of the size that is each layered and thermal conductivity factor, the layering and is
Chip, the parameter of the chip further include the rated voltage of the chip.
Preferably, the heat for calculating the multiple layering according to the parameter of the multiple layering based on thermal diffusion angle principle
Resistance includes：The size of heat source on chip is determined according to the size of the chip and rated voltage；According to the size of each layering and
The thermal diffusion angle of each layering of the Size calculation of thermal conductivity factor and heat source；And size according to each layering, thermal conductivity factor
The thermal resistance of each layering is calculated with thermal diffusion angle.
Preferably, the size and rated voltage according to the chip determines that the size of heat source includes on chip：According to
Size of the rated voltage of the chip using the default amount of the size reduction of the chip as the heat source.
Preferably, the heat of each layering of Size calculation of the size and thermal conductivity factor and heat source according to each layering
Angle of flare includes：The thermal diffusion angle of each layering is calculated according to below equation
Wherein, i represents the i-th layering, and x and y represent first direction and second direction in layering respectively,K tables
Show the thermal conductivity factor of layering, l represents the half of heat source length, and L represents the half of the length of layering, and w represents layering
Thickness.
Preferably, the thermal resistance bag that each layering is calculated according to the size of each layering, thermal conductivity factor and thermal diffusion angle
Include：Work as li_x=li_yAnd Li_x=Li_yWhen, the i-th thermal resistance Rth being layered is calculated by below equationi：
Wherein αi=αi_x=αi_y, li=li_x=li_y。
Preferably, the thermal resistance bag that each layering is calculated according to the size of each layering, thermal conductivity factor and thermal diffusion angle
Include：Work as li_x≠li_yAnd/or Li_x≠Li_yWhen, the i-th thermal resistance Rth being layered is calculated by below equationi：
Wherein,
Preferably, the parameter for obtaining the multiple layering includes：Receive encapsulated type, size and the volume of the chip
Constant voltage, and obtained and the corresponding the multiple layering of the encapsulated type of the chip according to the look-up table pre-established
Size and thermal conductivity factor.
Preferably, the look-up table is based on excel platform constructions.
Preferably, the look-up table includes：Alternative at least one encapsulated type；It is corresponding with every kind of encapsulated type
Each layering size and thermal conductivity factor；And alternative at least one rated voltage.
Preferably, the crust steady state heat resistance of power module according to the thermal resistance calculation of each layering includes：By each point
Crust steady state heat resistance of the sum of the thermal resistance of layer as the power module.
Preferably, encapsulated type, size and the rated voltage for receiving chip includes receiving use via user interface
Encapsulated type, size and the rated voltage of the chip of family input, the method is further included provides a user meter via user interface
The crust steady state heat resistance of the power module calculated.
According to another aspect of the present disclosure, there is provided a kind of device for the crust steady state heat resistance for calculating power module, it is described
Power module includes multiple layerings, it is characterised in that described device includes：Parameter acquisition module, for obtaining the multiple point
The parameter of layer；Individual layer computing module, it is the multiple for being calculated based on thermal diffusion angle principle according to the parameter of the multiple layering
The thermal resistance of layering；Summarizing module, the crust steady state heat resistance for power module described in the thermal resistance calculation according to the multiple layering.
Preferably, the parameter of the multiple layering includes one of the size that is each layered and thermal conductivity factor, the layering and is
Chip, the parameter of the chip further include the rated voltage of the chip.
Preferably, the individual layer computing module includes：Heat source computing module, for the size according to the chip and specified
Voltage determines the size of heat source on chip；Thermal diffusion angle computing module, for the size according to each layering and thermal conductivity factor with
And the thermal diffusion angle of each layering of Size calculation of heat source；And thermal resistance calculation module, for the size according to each layering, lead
Hot coefficient and thermal diffusion angle calculate the thermal resistance of each layering.
Preferably, the heat source computing module is used for the size reduction of the chip according to the rated voltage of the chip
Size of the default amount as the heat source.
Preferably, the parameter acquisition module includes：Interactive module, for receiving encapsulated type, the size of the chip
And rated voltage；Searching module, it is corresponding with the encapsulated type of the chip for being obtained according to the look-up table pre-established
The multiple layering size and thermal conductivity factor.
Preferably, the look-up table is based on excel platform constructions.
Preferably, the look-up table includes：Alternative at least one encapsulated type；It is corresponding with every kind of encapsulated type
Each layering size and thermal conductivity factor；And alternative at least one rated voltage.
Preferably, the interactive module is used for encapsulated type, the size that chip input by user is received via interactive interface
And rated voltage, and it is additionally operable to provide a user the crust steady state thermal of the power module calculated via user interface
Resistance.
According to another aspect of the present disclosure, there is provided a kind of computer-readable medium, is stored thereon with instruction, described instruction
The method for making processor perform the crust steady state heat resistance described above for calculating power module when being executed by processor.
Brief description of the drawings
In order to illustrate more clearly of the technical solution of the embodiment of the present disclosure, simple be situated between will be made to the attached drawing of embodiment below
Continue, it should be apparent that, the attached drawing in description below only relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.
Fig. 1 shows the schematic configuration diagram of the power module according to the embodiment of the present disclosure.
Fig. 2 shows the exemplary flow of the method for the crust steady state heat resistance of the calculating power module according to the embodiment of the present disclosure
Figure.
Fig. 3 shows the signal of the method for the crust steady state heat resistance of the calculating power module according to another embodiment of the disclosure
Flow chart.
Fig. 4 A to Fig. 4 D show the example of the look-up table according to the embodiment of the present disclosure.
Fig. 5 A and 5B show the example of the user interface according to the embodiment of the present disclosure.
Fig. 6 A and Fig. 6 B respectively illustrate the sectional view on long and cross direction according to the power module of the embodiment of the present disclosure.
Fig. 7 shows the schematic construction of the device of the crust steady state heat resistance of the calculating power module according to the embodiment of the present disclosure
Figure.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present disclosure clearer, below in conjunction with the embodiment of the present disclosure
Attached drawing, clear, complete description is carried out to the technical solution of the embodiment of the present disclosure.Obvious described embodiment is the disclosure
Part of the embodiment, instead of all the embodiments.Based on described embodiment of the disclosure, ordinary skill people
Member's all other embodiments obtained on the premise of without creative work, belong to the scope of disclosure protection.
Present disclose provides a kind of method and computer-readable medium of the crust steady state heat resistance for calculating power module, pass through
The thermal resistance of the multiple layering is calculated according to the parameter of the multiple layering based on thermal diffusion angle principle, without establishing power module
Threedimensional model crust steady state heat resistance can be achieved calculate, shortened compared to conventional method and calculate the time and with higher
Versatility.
Fig. 1 shows the schematic configuration diagram of the power module according to the embodiment of the present disclosure.Power module can be applied to
The power of power inverter integrates (PIM, Power Integrated Module) module, and in the present embodiment, it can have
Eight Rotating fields, i.e. be followed successively by chip 1, solder layer 2, upper layers of copper 3, ceramic layer 4, lower layers of copper 5, solder layer 6, copper-based from top to bottom
Plate 7, thermal grease layer 8, the lower section of thermal grease layer 8 can be heat sink (not shown).But those skilled in the art should be clear
Chu, is only an exemplary construction of power module above, the power module not limited to this of the embodiment of the present disclosure, it can basis
Need different and there are a variety of structures, such as there can be five-layer structure.
Fig. 2 shows the exemplary flow of the method for the crust steady state heat resistance of the calculating power module according to the embodiment of the present disclosure
Figure.Power module can have multiple layerings, and one of layering is chip.According to the difference of type of package for chips, layering knot
Structure is different, such as can have the hierarchy shown in Fig. 1, naturally it is also possible to has other any desired structures.
In step S201, the parameter of multiple layerings of power module is obtained.Such as the encapsulation class of the chip can be received
Type, size and rated voltage, and obtained and the corresponding institute of the encapsulated type of the chip according to the look-up table pre-established
State the size and thermal conductivity factor of multiple layerings.Look-up table can include：It is alternative at least one encapsulated type and with it is every
The size and thermal conductivity factor of the kind corresponding each layering of encapsulated type.In certain embodiments, look-up table can also include can
Selective at least one rated voltage.
In step S202, the heat based on thermal diffusion angle principle according to the multiple layering of the parameter of the multiple layering calculating
Resistance.Such as the size of heat source on chip can be determined according to the size and rated voltage of the chip, according to the ruler of each layering
The very little and thermal diffusion angle of the thermal conductivity factor and heat source each layering of Size calculation, and according to the size of each layering, heat conduction system
Number and thermal diffusion angle calculate the thermal resistance of each layering.
In step S203, according to the crust steady state heat resistance of power module described in the thermal resistance calculation of the multiple layering.Such as
Crust steady state heat resistance that can be using the sum of thermal resistance of each layering as the power module.Preferably, user circle can be provided
Face, via user interface to receive the encapsulated type of chip, size and rated voltage, and provides a user meter via user interface
The crust steady state heat resistance of the power module calculated.
Fig. 3 shows the signal of the method for the crust steady state heat resistance of the calculating power module according to another embodiment of the disclosure
Flow chart.
In step S301, look-up table is established.The look-up table can be established manually by user.Look-up table can include：At least
A kind of encapsulated type, and with the corresponding hierarchy of every kind of encapsulated type, such as the type of each layering, position, size,
Thermal conductivity factor.
Fig. 4 A to Fig. 4 D show the example of the look-up table according to the embodiment of the present disclosure.In the embodiment of Fig. 4 A to 4D,
Look-up table is based on excel platform constructions.Certain embodiment of the disclosure not limited to this, can also be as needed based on any
Other platforms build look-up table.
As shown in Fig. 4 A to 4D, by taking the encapsulated type shown in Fig. 1 as an example, the hierarchy under the encapsulated type is 8 layers, point
It is not chip, solder layer, upper layers of copper, ceramic layer, lower layers of copper, solder layer, copper base, thermal grease layer, the lower section of thermal grease layer 8
Can be heat sink.Look-up table is divided into four parts, be respectively designated as in the present embodiment " thermophysical parameter ", " rated voltage ", " point
Layer length " and " layering width ".
As shown in Figure 4 A, " thermophysical parameter " partly includes the thermal conductivity factor K and thickness T of each layering, in the present embodiment
Middle thermal conductivity factor K by watt/ meter Du in units of, thickness T is in units of millimeter.It illustrate only in Figure 4 A for envelope shown in Fig. 1
The thermophysical parameter being respectively layered of dress type, but the present embodiment not limited to this, can fill in for other encapsulation as needed
Each layering thermophysical parameter of type, such as each point for another encapsulated type can be inserted on E, F, G, H column of Fig. 4 A
Layer thermophysical parameter, and so on.Preferably for the thermal conductivity factor of two kinds of encapsulated type same hierarchical levels, can be not repeated
Setting, because the thermal conductivity factor of identical material is identical, and thickness can be reset as needed.
As shown in Figure 4 B, " rated voltage " partly includes at least one rated voltage, the column be it is optional, its be used for
Option is provided to the user during the follow-up input rated voltage in family, to facilitate user to select.If the not partial data, Ke Yi
User is made to be manually entered desired load voltage value in user interface.Illustrate only in the example of Fig. 4 B 3 it is alternative
Rated voltage, but embodiment of the disclosure not limited to this, can provide any alternative rated voltage as needed.
Such as it can arrange to continue below in the data of Fig. 4 B and fill in other alternative load voltage values.
As shown in Figure 4 C, " layering length " partly includes the length of each layering in a first direction, in the present embodiment
Can be in units of millimeter.Fig. 4 C illustrate only each length being layered in a first direction for encapsulated type shown in Fig. 1, so
And embodiment of the disclosure not limited to this, it can as needed fill in and be layered in a first direction for each of other encapsulated types
Length, such as can be inserted on E, F, G, H column of Fig. 4 C for another encapsulated type each layering in a first direction
Length, and so on.
As shown in Figure 4 D, similar to Fig. 4 C, " layering width " partly includes the length of each layering in a second direction,
Being respectively layered second for other encapsulated types equally can be as needed filled in the present embodiment in units of millimeter
Width on direction.
In certain embodiments, above-described " length on first direction " and " length in second direction " can be
Refer to the length and width of blocking.Certain embodiment of the present disclosure not limited to this, first direction and second direction can appoint as needed
Meaning is set, as long as size of delamination can be embodied.
In step S302, size, encapsulated type and the rated voltage of chip are received.Such as it can come via user interface real
The now operation.Fig. 5 A and 5B show the example of the user interface according to the embodiment of the present disclosure.As shown in Figure 5A, input field
5011st, 5012 and 5013 it is respectively used to make user to input the length and width and thickness of chip；Option column 502 is used to make user select the phase
The type of package for chips of prestige；Option column 503 is used to make user select desired chip rated voltage.When user fills in and has selected
After finishing, the calculating of crust steady state heat resistance can be triggered by button 504, by pop-up window 505 to user after the completion of calculating
Result of calculation is presented.In certain embodiments, look-up table can also be presented in the lump in the user interface, to facilitate user to check.
As shown in Figure 5 B, the user interface shown in Fig. 4 A to the look-up table shown in 4D and Fig. 5 A can be together presented to user, one
In a little embodiments, it can also be set on Fig. 4 A to the look-up table page shown in 4D for starting crust steady state heat resistance calculation process
Button 506.When user complete look-up table fill in after click button 506, eject interface as shown in Figure 5A afterwards, so as to
Family inputs the parameter of chip, button 504 is clicked on after user's input parameter to start to calculate crust steady state heat resistance, crust steady state thermal
Resistance can similarly eject the window 505 shown in Fig. 5 A after the completion of calculating.
In step S303, corresponding the multiple point of the encapsulated type obtained with step S302 is obtained according to look-up table
The size and thermal conductivity factor of layer.For example, it can be obtained according to such as Fig. 4 A under encapsulated type shown in Fig. 1 to the look-up table shown in 4D
The size and thermal conductivity factor of each layering, i.e. chip 1, solder layer 2, upper layers of copper 3, ceramic layer 4, lower layers of copper 5, solder layer 6, copper
Substrate 7, the thermal conductivity factor of thermal grease layer 8, thickness, length and width.
In step S304, the heat based on thermal diffusion angle principle according to the multiple layering of the parameter of the multiple layering calculating
Resistance.As an example, step S304 can include step S3041 to S3046.
In step S3041, the size of heat source on chip is determined according to the size of chip and rated voltage.Such as can basis
Size of the rated voltage of chip using the default amount of the size reduction of chip as heat source.Specific reduction volume can be come as needed
It is any to set, such as can be set according to the width of chip protection ring.
It is each according to the Size calculation of the size of layering and thermal conductivity factor and heat source since first layer in step S3042
The thermal diffusion angle of a layering.For example, i is initially 1, the thermal diffusion angle of the i-th layering is calculated according to below equation (1) and (2)：
Wherein, i represents the i-th layering, and x and y represent first direction in layering and second direction (in the present embodiment respectively
In, can be the length of layering and wide direction),K represents the thermal conductivity factor of layering, and l represents two points of heat source length
One of, L represents the half of the length of layering, and w represents lift height.
In step S3043, judge whether substrate and heat source are square, i.e., whether meet li_x=li_yAnd Li_x=
Li_y, step S3044 is if it is performed, otherwise performs step S3045.
In step S3044, the i-th thermal resistance Rth being layered is calculated by below equation (3)i：
Wherein αi=αi_x=αi_y, li=li_x=li_y。
In step S3044, the i-th thermal resistance Rth being layered is calculated by below equation (4)i：
Wherein,
In step S3045, carry out to next layering, i.e. i=i+1.
In step S3046, judge whether to complete the thermal resistance calculation of last layering, i.e. whether meet i ＞ N, wherein
N represents the sum of layering, such as the structure for Fig. 1, N=8.If it is perform step S305 to sum, otherwise return
Step S3043 continues to calculate the thermal resistance of next layering.
In step S305, by the thermal resistance Rth of layeringiSummation is to obtain the crust steady state heat resistance of whole power module, specifically
Ground can obtain the knot of power module-shell stable state crust steady state heat resistance Rjc by below equation (5)：
But embodiment of the disclosure not limited to this, heat of other calculations from each layering can be used as needed
Resistance obtains the crust steady state heat resistance of whole power module, such as weighted sum etc..
Step S304 is described in detail below with reference to the example of Fig. 6 A and Fig. 6 B.Fig. 6 A and Fig. 6 B respectively illustrate root
According to sectional view of the power module of the embodiment of the present disclosure on long and cross direction.As shown in Figure 6 A and 6B, power module includes two
A layering 601 and 602, wherein layering 601 is chip, thereon with heat source 603.The thermal conductivity factor of layering 601 is k1, thickness is
w1, length is 2L on first direction1_x, length is 2L in second direction1_y.The thermal conductivity factor of layering 602 is k2, thickness w2, the
Length is 2L on one direction2_x, length is 2L in second direction2_y.Length 2l on the first direction of heat source 603x, in second direction
Length is 2ly.In this example, it is assumed that x and y represent the length of rectangle and wide direction respectively.
First can be according to the size of the rated voltage of chip 601 come by the long L of chip 6011_xWith wide L1_yReduce pre-
Fixed value, the long l using obtained result as heat source 603xWith wide ly.Specific reduction volume can come any setting, example as needed
It can such as be set according to the width of chip protection ring.Then the thermal diffusion of above equation (1) and (2) computing chip 601 is passed through
Angle α1With the thermal diffusion angle α of the lower section of chip 601 layering 6022.Judge whether chip 601 and heat source 603 are square, i.e. be
It is no to meet L1_x=L1_yAnd lx=ly, if it is, being layered come computing chip 601 and below 602 using above-mentioned equation (3)
Thermal resistance Rth1, otherwise come the computing chip 601 and below thermal resistance Rth of layering 602 using above-mentioned equation (4)2.By Rth1With
Rth2It is cumulative to obtain the crust steady state heat resistance of whole power module.
Fig. 7 shows the schematic construction of the device of the crust steady state heat resistance of the calculating power module according to the embodiment of the present disclosure
Figure.Power module can have multiple layerings, and one of layering is chip.According to the difference of type of package for chips, layering knot
Structure is different, such as can have the hierarchy shown in Fig. 1, naturally it is also possible to has other any desired structures.Such as
Shown in Fig. 7, calculating the device of the crust steady state heat resistance of power module includes：Parameter acquisition module 701, individual layer computing module 702,
Summarizing module 703.
Parameter acquisition module 701 is used for the parameter for obtaining the multiple layering.The parameter of multiple layerings includes each layering
Size and thermal conductivity factor, it is described layering one of be chip, the parameter of the chip further includes the rated voltage of the chip.
In the example of Fig. 7, parameter acquisition module 701 can include interactive module 7011 and searching module 7012.Interactive module 7011 is used
In the encapsulated type, size and the rated voltage that receive the chip.In certain embodiments, interactive module 7011 can be arranged to
Can receive encapsulated type, size and the rated voltage of chip input by user via interactive interface, and can also via with
Family interface provides a user the crust steady state heat resistance of the power module calculated.Interactive interface can use the phase as needed
The form of prestige, such as interactive interface as shown in Figure 5 A and 5B can be used.Searching module 7012 is used for what basis pre-established
Look-up table obtains size and thermal conductivity factor with the corresponding the multiple layering of the encapsulated type of the chip.Look-up table can
With including：The size and heat conduction of alternative at least one encapsulated type and the corresponding each layering of every kind of encapsulated type
Coefficient and alternative at least one rated voltage.Such as can be using the look-up table as shown in Fig. 4 A to Fig. 4 D.
Individual layer computing module 702 is used to be calculated according to the parameter of the multiple layering based on thermal diffusion angle principle the multiple
The thermal resistance of layering.In the example in figure 7, individual layer computing module 702 can include heat source computing module 7021, thermal diffusion angle calculates
Module 7022 and thermal resistance calculation module 7023.Heat source computing module 7021 is true for the size and rated voltage according to the chip
Determine the size of heat source on chip, for example, can according to the rated voltage of chip using the default amount of the size reduction of the chip as
The size of the heat source.Thermal diffusion angle computing module 7022 is used for according to the size and thermal conductivity factor of each layering and heat source
The thermal diffusion angle of each layering of Size calculation, such as the thermal diffusion of each layering can be calculated according to above-mentioned equation (1) and (2)
Angle.Thermal resistance calculation module 7023 is used for the heat that each layering is calculated according to the size of each layering, thermal conductivity factor and thermal diffusion angle
Resistance, such as the thermal resistance of each layering can be calculated according to above-mentioned equation (3) and (4).
Summarizing module 703 is used for the crust steady state heat resistance of the power module according to the thermal resistance calculation of the multiple layering.
Such as the crust steady state heat resistance of power module can be obtained according to above-mentioned equation (5).But embodiment of the disclosure is not limited to
This, can obtain the crust steady state thermal of whole power module using the thermal resistance of other calculations from each layering as needed
Resistance, such as weighted sum etc..
Embodiment of the disclosure additionally provides a kind of computer-readable medium, is stored thereon with instruction, described instruction is in quilt
Processor can make the method that processor performs the crust steady state heat resistance described above for calculating power module when performing.The disclosure
Part that the technical solution of embodiment substantially either contributes the prior art or change the part of technical solution can be with
The form of software product embodies, which is stored in storage medium, including some instructions, described instruction exists
Make during execution computer equipment (can be computer, processor or other possess electronic equipment of computing function etc.) perform this public affairs
Open all or part of step of the method described in embodiment.The storage medium includes read-only storage (ROM, Read Only
Memory), random access memory (RAM, Random Access Memory), USB flash disk, mobile hard disk, disk or CD etc. can
With the medium of store instruction.
Embodiment of the disclosure is the multiple by being calculated based on thermal diffusion angle principle according to the parameter of the multiple layering
The thermal resistance of layering, the threedimensional model without establishing power module can be achieved crust steady state heat resistance and calculate, compared to conventional method
Shorten and calculate time and the versatility with higher.
Embodiment of the disclosure is by the judgement for square and non-square structures, for the chip and heat of square
Source structure can reduce a part of calculation amount, there is provided crust steady state heat resistance computational efficiency.
Embodiment of the disclosure is by receiving chip parameter input by user via user interface and providing a user knot
Shell steady state heat resistance result of calculation, realizes user mutual in a manner of simple efficient, improves work efficiency.By in user interface
In provide search list item in the lump, what more convenient user checked power module is divided into structure and parameters, the user with higher
Friendly.
The foregoing is merely preferred embodiment of the present disclosure, is not limited to the disclosure, for those skilled in the art
For, the disclosure can have various modifications and changes.All any modifications made within the spirit and principle of the disclosure, be equal
Replace, improve etc., it should be included within the protection domain of the disclosure.
Claims (21)
1. a kind of method for the crust steady state heat resistance for calculating power module, the power module include multiple layerings, its feature exists
In, the described method includes：
Obtain the parameter of the multiple layering；
The thermal resistance of the multiple layering is calculated according to the parameter of the multiple layering based on thermal diffusion angle principle；
According to the crust steady state heat resistance of power module described in the thermal resistance calculation of the multiple layering.
2. the method for the crust steady state heat resistance according to claim 1 for calculating power module, it is characterised in that
It is chip that the parameter of the multiple layering, which includes one of the size that is each layered and thermal conductivity factor, the layering, the core
The parameter of piece further includes the rated voltage of the chip.
3. the method for the crust steady state heat resistance according to claim 2 for calculating power module, it is characterised in that described to be based on
The thermal resistance that thermal diffusion angle principle calculates the multiple layering according to the parameter of the multiple layering includes：
The size of heat source on chip is determined according to the size of the chip and rated voltage；
According to the thermal diffusion angle of each layering of the Size calculation of the size of each layering and thermal conductivity factor and heat source；And
The thermal resistance of each layering is calculated according to the size of each layering, thermal conductivity factor and thermal diffusion angle.
4. the method for the crust steady state heat resistance according to claim 3 for calculating power module, it is characterised in that the basis
The size and rated voltage of the chip determine that the size of heat source includes on chip：According to the rated voltage of the chip by described in
Size of the default amount of size reduction of chip as the heat source.
5. the method for the crust steady state heat resistance according to claim 3 for calculating power module, it is characterised in that the basis
The thermal diffusion angle of each layering of Size calculation of the size and thermal conductivity factor and heat source of each layering includes：According to below equation
Calculate the thermal diffusion angle of each layering
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<mi>&rho;</mi>
<mi>i</mi>
</msub>
<mrow>
<mn>1</mn>
<mo>+</mo>
<msub>
<mi>&rho;</mi>
<mi>i</mi>
</msub>
</mrow>
</mfrac>
<mo>&rsqb;</mo>
</mrow>
<mo>&CenterDot;</mo>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
</mrow>
<mrow>
<msub>
<mi>w</mi>
<mi>i</mi>
</msub>
<mo>+</mo>
<mrow>
<mo>&lsqb;</mo>
<mfrac>
<mn>1</mn>
<mrow>
<mn>1</mn>
<mo>+</mo>
<msub>
<mi>&rho;</mi>
<mi>i</mi>
</msub>
</mrow>
</mfrac>
<mo>&rsqb;</mo>
</mrow>
<mo>&CenterDot;</mo>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
</mrow>
</mfrac>
<mo>&CenterDot;</mo>
<mo>(</mo>
<mrow>
<mn>1</mn>
<mo>-</mo>
<mfrac>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
<msub>
<mi>L</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
</mfrac>
</mrow>
<mo>)</mo>
</mrow>
<mrow>
<mo>(</mo>
<msub>
<mi>tan&alpha;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
<mo>)</mo>
<mo>=</mo>
<mfrac>
<mrow>
<msub>
<mi>w</mi>
<mi>i</mi>
</msub>
<mo>+</mo>
<mrow>
<mo>&lsqb;</mo>
<mfrac>
<msub>
<mi>&rho;</mi>
<mi>i</mi>
</msub>
<mrow>
<mn>1</mn>
<mo>+</mo>
<msub>
<mi>&rho;</mi>
<mi>i</mi>
</msub>
</mrow>
</mfrac>
<mo>&rsqb;</mo>
</mrow>
<mo>&CenterDot;</mo>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
</mrow>
<mrow>
<msub>
<mi>w</mi>
<mi>i</mi>
</msub>
<mo>+</mo>
<mrow>
<mo>&lsqb;</mo>
<mfrac>
<mn>1</mn>
<mrow>
<mn>1</mn>
<mo>+</mo>
<msub>
<mi>&rho;</mi>
<mi>i</mi>
</msub>
</mrow>
</mfrac>
<mo>&rsqb;</mo>
</mrow>
<mo>&CenterDot;</mo>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
</mrow>
</mfrac>
<mo>&CenterDot;</mo>
<mo>(</mo>
<mrow>
<mn>1</mn>
<mo>-</mo>
<mfrac>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
<msub>
<mi>L</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
</mfrac>
</mrow>
<mo>)</mo>
</mrow>
Wherein, i represents the i-th layering, and x and y represent first direction and second direction in layering respectively,K represents to divide
The thermal conductivity factor of layer, l represent the half of heat source length, and L represents the half of the length of layering, and w represents lift height.
6. the method for the crust steady state heat resistance according to claim 5 for calculating power module, it is characterised in that the basis
The thermal resistance that size, thermal conductivity factor and the thermal diffusion angle of each layering calculate each layering includes：Work as li_x=li_yAnd Li_x=
Li_yWhen, the i-th thermal resistance Rth being layered is calculated by below equationi：
Wherein αi=αi_x=αi_y, li=li_x=li_y。
7. the method for the crust steady state heat resistance according to claim 5 for calculating power module, it is characterised in that the basis
The thermal resistance that size, thermal conductivity factor and the thermal diffusion angle of each layering calculate each layering includes：Work as li_x≠li_yAnd/or Li_x≠
Li_yWhen, the i-th thermal resistance Rth being layered is calculated by below equationi：
<mrow>
<msub>
<mi>Rth</mi>
<mi>i</mi>
</msub>
<mo>=</mo>
<mfrac>
<mn>1</mn>
<mrow>
<mn>4</mn>
<msub>
<mi>k</mi>
<mi>i</mi>
</msub>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
</mrow>
</mfrac>
<mrow>
<mo>&lsqb;</mo>
<mrow>
<mfrac>
<mn>1</mn>
<mrow>
<mo>(</mo>
<msub>
<mi>&gamma;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>e</mi>
</mrow>
</msub>
<mo>(</mo>
<mrow>
<msub>
<mi>tan&alpha;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
</mrow>
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<mrow>
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<mi>tan&alpha;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
</mrow>
<mo>)</mo>
<mo>)</mo>
</mrow>
</mfrac>
<mo>&CenterDot;</mo>
<mi>ln</mi>
<mfrac>
<mrow>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
<mo>+</mo>
<msub>
<mi>w</mi>
<mi>i</mi>
</msub>
<mrow>
<mo>(</mo>
<msub>
<mi>tan&alpha;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
<mo>)</mo>
</mrow>
</mrow>
<mrow>
<msub>
<mi>l</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>x</mi>
</mrow>
</msub>
<mo>+</mo>
<msub>
<mi>w</mi>
<mi>i</mi>
</msub>
<mrow>
<mo>(</mo>
<msub>
<mi>tan&alpha;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>y</mi>
</mrow>
</msub>
<mo>)</mo>
</mrow>
<mo>/</mo>
<msub>
<mi>&gamma;</mi>
<mrow>
<mi>i</mi>
<mo>_</mo>
<mi>e</mi>
</mrow>
</msub>
</mrow>
</mfrac>
</mrow>
<mo>&rsqb;</mo>
</mrow>
</mrow>
Wherein,
8. the method for the crust steady state heat resistance according to claim 2 for calculating power module, it is characterised in that the acquisition
The parameter of the multiple layering includes：Receive encapsulated type, size and the rated voltage of the chip, and according to pre-establishing
Look-up table obtains size and thermal conductivity factor with the corresponding the multiple layering of the encapsulated type of the chip.
9. the method for the crust steady state heat resistance according to claim 8 for calculating power module, it is characterised in that the lookup
Table is based on excel platform constructions.
10. the method for the crust steady state heat resistance according to claim 8 for calculating power module, it is characterised in that described to look into
Table is looked for include：
Alternative at least one encapsulated type；
With the size and thermal conductivity factor of the corresponding each layering of every kind of encapsulated type；And
Alternative at least one rated voltage.
11. the method for the crust steady state heat resistance according to any one of claim 1 to 10 for calculating power module, its feature
It is, is included according to the crust steady state heat resistance of power module described in the thermal resistance calculation of each layering：By the thermal resistance of each layering it
With the crust steady state heat resistance as the power module.
12. the method for the crust steady state heat resistance according to any one of claim 1 to 10 for calculating power module, its feature
It is, encapsulated type, size and the rated voltage for receiving chip includes receiving core input by user via user interface
Encapsulated type, size and the rated voltage of piece, described in the method further includes and provides a user and calculate via user interface
The crust steady state heat resistance of power module.
13. a kind of device for the crust steady state heat resistance for calculating power module, the power module include multiple layerings, its feature exists
In described device includes：
Parameter acquisition module, for obtaining the parameter of the multiple layering；
Individual layer computing module, for based on thermal diffusion angle principle, the multiple layering to be calculated according to the parameter of the multiple layering
Thermal resistance；
Summarizing module, the crust steady state heat resistance for power module described in the thermal resistance calculation according to the multiple layering.
14. the device of the crust steady state heat resistance according to claim 13 for calculating power module, it is characterised in that described more
It is chip that the parameter of a layering, which includes one of size and the thermal conductivity factor being each layered, the layering, and the parameter of the chip is also
Include the rated voltage of the chip.
15. the device of the crust steady state heat resistance according to claim 14 for calculating power module, it is characterised in that the list
Layer computing module includes：
Heat source computing module, the size of heat source on chip is determined for the size according to the chip and rated voltage；
Thermal diffusion angle computing module, each point of the Size calculation for the size according to each layering and thermal conductivity factor and heat source
The thermal diffusion angle of layer；And
Thermal resistance calculation module, the thermal resistance of each layering is calculated for the size according to each layering, thermal conductivity factor and thermal diffusion angle.
16. the device of the crust steady state heat resistance according to claim 15 for calculating power module, it is characterised in that the heat
Source computing module is used for the rated voltage according to the chip using the default amount of the size reduction of the chip as the heat source
Size.
17. the device of the crust steady state heat resistance according to claim 14 for calculating power module, it is characterised in that the ginseng
Number acquisition module includes：
Interactive module, for receiving encapsulated type, size and the rated voltage of the chip；
Searching module is corresponding described more with the encapsulated type of the chip for being obtained according to the look-up table pre-established
The size and thermal conductivity factor of a layering.
18. the device of the crust steady state heat resistance according to claim 17 for calculating power module, it is characterised in that described to look into
It is based on excel platform constructions to look for table.
19. the device of the crust steady state heat resistance according to claim 17 for calculating power module, it is characterised in that described to look into
Table is looked for include：
Alternative at least one encapsulated type；
With the size and thermal conductivity factor of the corresponding each layering of every kind of encapsulated type；And
Alternative at least one rated voltage.
20. the device of the crust steady state heat resistance of the calculating power module according to any one of claim 13 to 19, it is special
Sign is that the interactive module is used for encapsulated type, size and the specified electricity that chip input by user is received via interactive interface
Pressure, and it is additionally operable to provide a user the crust steady state heat resistance of the power module calculated via user interface.
21. a kind of computer-readable medium, is stored thereon with instruction, described instruction performs processor when being executed by processor
The method of the crust steady state heat resistance according to any one of claim 1 to 12 for calculating power module.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109583004A (en) * | 2018-10-15 | 2019-04-05 | 杭州士兰集成电路有限公司 | The method and apparatus for calculating the temperature value and time value relationship of semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090319964A1 (en) * | 2008-06-24 | 2009-12-24 | Vinod Kariat | Method and apparatus for thermal analysis |
| CN105718694A (en) * | 2016-01-28 | 2016-06-29 | 重庆大学 | Thermal-network parameter identification method based on IGBT junction temperature information |
| CN107219016A (en) * | 2017-05-24 | 2017-09-29 | 湖南大学 | Calculate the method and system of IGBT module transient state junction temperature |
| CN107315877A (en) * | 2017-06-28 | 2017-11-03 | 华北电力大学 | A kind of method and system for predicting power device junction temperature |
-
2017
- 2017-11-06 CN CN201711080654.XA patent/CN107958100A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090319964A1 (en) * | 2008-06-24 | 2009-12-24 | Vinod Kariat | Method and apparatus for thermal analysis |
| CN105718694A (en) * | 2016-01-28 | 2016-06-29 | 重庆大学 | Thermal-network parameter identification method based on IGBT junction temperature information |
| CN107219016A (en) * | 2017-05-24 | 2017-09-29 | 湖南大学 | Calculate the method and system of IGBT module transient state junction temperature |
| CN107315877A (en) * | 2017-06-28 | 2017-11-03 | 华北电力大学 | A kind of method and system for predicting power device junction temperature |
Non-Patent Citations (2)
| Title |
|---|
| XU Y ET AL: "Misconception of thermal spreading angle and misapplication to IGBT power modules", 《IEEE APPLIED POWER ELECTRONICS CONFERENCE & EXPOSITION-APEC》 * |
| 童学根: "矿用变频器传热研究及水冷换热器优化分析", 《中国优秀硕士学位论文全文数据库工程科技Ⅰ辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109583004A (en) * | 2018-10-15 | 2019-04-05 | 杭州士兰集成电路有限公司 | The method and apparatus for calculating the temperature value and time value relationship of semiconductor devices |
| CN109583004B (en) * | 2018-10-15 | 2022-12-30 | 杭州士兰集成电路有限公司 | Method and device for calculating relation between temperature value and time value of semiconductor device |
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