CN107946332B - Semiconductor structure, CMOS image sensor and preparation method thereof - Google Patents

Semiconductor structure, CMOS image sensor and preparation method thereof Download PDF

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Publication number
CN107946332B
CN107946332B CN201711175153.XA CN201711175153A CN107946332B CN 107946332 B CN107946332 B CN 107946332B CN 201711175153 A CN201711175153 A CN 201711175153A CN 107946332 B CN107946332 B CN 107946332B
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layer
metal
dielectric layer
groove
barrier layer
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CN107946332A (en
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彭琬婷
林宗德
黄仁德
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Huaian Xide Industrial Design Co ltd
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Huaian Imaging Device Manufacturer Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Abstract

The invention provides a semiconductor structure, a CMOS image sensor and a preparation method thereof, comprising the following steps: 1) providing a semiconductor substrate, and sequentially forming a first dielectric layer and a second dielectric layer on the upper surface of the semiconductor substrate; 2) forming grooves in the first dielectric layer and the second dielectric layer; 3) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer; 4) forming a conductive metal layer on the surface of the first metal barrier layer; 5) removing part of the conductive metal layer by adopting a back etching process to form a conductive plug; 6) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug; 7) forming a metal connecting line layer on the surface of the second metal barrier layer; 8) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer. The invention can greatly save the production cost; compared with the prior art, the method has fewer process steps and simpler process.

Description

Semiconductor structure, CMOS image sensor and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure, a CMOS (complementary metal oxide semiconductor) image sensor and a preparation method thereof.
Background
CMOS image sensors are semiconductor devices that convert optical images into electrical signals, and are currently widely used in various fields.
In the prior art, after a CMOS image sensor is formed on a semiconductor substrate, the CMOS image sensor is protected by forming a passivation layer at a rear stage, and at this time, a conductive plug and a metal wiring layer are required to be prepared to connect and lead out the CMOS image sensor, and the conventional process for preparing the conductive plug and the metal wiring layer includes the following steps:
1) providing a semiconductor substrate 10, wherein a plurality of CMOS image sensor units are prepared in the semiconductor substrate 10, as shown in FIG. 1;
2) forming a TEOS (tetraethylorthosilicate) layer 11 in the semiconductor substrate 10, and forming a first through-hole 12 in the TEOS layer 11, as shown in fig. 2;
3) forming a first metal barrier layer 13 on the bottom and sidewalls of the first via 12 and the upper surface of the TEOS layer 11, as shown in fig. 3;
4) forming a W (tungsten) metal layer 14 on the upper surface of the first metal barrier layer 13, as shown in fig. 4;
5) removing the first metal barrier layer 13 and the W metal layer 14 on the upper surface of the TEOS layer 11 by using a Chemical Mechanical Polishing (CMP) process to form a W plug 15, as shown in fig. 5;
6) forming a SiN layer 16 and a plasma enhanced Undoped Silicate Glass (USG) layer 17 on the upper surface of the structure obtained in step 5), as shown in fig. 6;
7) forming a second via 18 in the SiN layer 16 and the undoped silicate glass layer 17, wherein the second via 18 exposes the W plug 15, as shown in fig. 7; the undoped silicon glass layer 17 and the TEOS layer 11 are mainly silicon dioxide, and the SiN layer 16 is arranged between the undoped silicon glass layer 17 and the TEOS layer 11, so that the capture of an etching end point (end point) is facilitated;
8) forming a second metal barrier layer 19 on the bottom and sidewall of the second via 18 and the upper surface of the undoped silicate glass layer 17, as shown in fig. 8;
9) forming a Cu metal layer 110 on the upper surface of the second metal barrier layer 19, as shown in fig. 9;
10) the Cu metal layer 110 on the upper surface of the undoped silicate glass layer 17 is removed by a chemical mechanical polishing process to form a metal interconnection layer 111, as shown in fig. 10.
However, the above method is complicated in process steps, and the above method uses a chemical mechanical polishing process for W, and the W chemical mechanical polishing apparatus consumes more water and electricity during use, so that the cost of the whole method is high.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure, a CMOS image sensor and a method for manufacturing the same, which are used to solve the problems of the prior art that the process steps are relatively complicated and the cost is relatively high.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
1) providing a semiconductor substrate, and sequentially forming a first dielectric layer and a second dielectric layer on the upper surface of the semiconductor substrate;
2) forming a groove in the first dielectric layer and the second dielectric layer, wherein the groove exposes part of the semiconductor substrate;
3) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer;
4) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer;
5) removing part of the conductive metal layer by adopting a back etching process to form a conductive plug, wherein the upper surface of the conductive plug is lower than that of the groove;
6) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug;
7) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer;
8) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer.
As a preferable aspect of the present invention, the step 2) includes the steps of:
2-1) forming a first groove part in the first dielectric layer and the second dielectric layer, wherein the first groove part penetrates through the second dielectric layer and extends into the first dielectric layer;
2-2) forming a second groove part below the bottom of the first groove part, wherein the second groove part is communicated with the first groove part and penetrates through the first medium layer; the lateral dimension of the second groove portion is smaller than the lateral dimension of the first groove portion.
As a preferable scheme of the present invention, in step 8), the first metal barrier layer, the second metal barrier layer, and the metal interconnection layer on the upper surface of the second dielectric layer are removed by using a chemical mechanical polishing process.
As a preferred embodiment of the present invention, the first dielectric layer and the second dielectric layer are both undoped silicon glass layers, the conductive metal layer is a tungsten metal layer, and the metal connecting line layer is a copper metal layer.
The present invention also provides a semiconductor structure on an upper surface of a semiconductor substrate, the semiconductor structure comprising:
the first dielectric layer is positioned on the upper surface of the semiconductor substrate;
the second dielectric layer is positioned on the upper surface of the first dielectric layer;
the groove is positioned in the first dielectric layer and the second dielectric layer and vertically penetrates through the first dielectric layer and the second dielectric layer to expose part of the semiconductor substrate;
the first metal barrier layer is positioned on the side wall of the groove;
the conductive plug is positioned in the groove on the inner side of the first metal barrier layer, and the upper surface of the conductive plug is lower than that of the groove;
the second metal barrier layer is positioned on the upper surface of the conductive plug and the surface of the first metal barrier layer above the conductive plug;
and the metal connecting wire layer is filled in the groove on the inner side of the second metal barrier layer.
As a preferable aspect of the present invention, the trench includes a first trench portion and a second trench portion located above the first trench portion and communicating with the first trench portion, wherein a lateral dimension of the first trench portion is smaller than a lateral dimension of the second trench portion.
In a preferred embodiment of the present invention, an upper surface of the conductive plug is flush with an upper surface of the first trench portion.
As a preferred embodiment of the present invention, the first dielectric layer and the second dielectric layer are both undoped silicon glass layers, the conductive plug is a tungsten metal plug, and the metal wiring layer is a copper metal layer.
As a preferable aspect of the present invention, an upper surface of the metal wiring layer is flush with an upper surface of the second dielectric layer.
The invention also provides a preparation method of the CMOS image sensor, which comprises the following steps:
1) providing a semiconductor substrate;
2) forming a CMOS image sensor unit in the semiconductor substrate, wherein a connecting welding pad electrically connected with an internal functional device of the CMOS image sensor unit is formed in the CMOS image sensor unit;
3) forming a first dielectric layer on the upper surface of the semiconductor substrate, and forming a second dielectric layer on the upper surface of the first dielectric layer;
4) forming grooves in the first dielectric layer and the second dielectric layer, wherein the grooves expose the connecting welding pads;
5) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer;
6) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer;
7) removing part of the conductive metal layer by adopting a back etching process to obtain a conductive plug, wherein the upper surface of the conductive plug is lower than that of the groove;
8) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug;
9) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer;
10) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer.
As a preferable aspect of the present invention, the step 4) includes the steps of:
4-1) forming a first groove part in the first dielectric layer and the second dielectric layer, wherein the first groove part penetrates through the second dielectric layer and extends into the first dielectric layer;
4-2) forming a second groove part below the bottom of the first groove part, wherein the second groove part is communicated with the first groove part and penetrates through the first medium layer; the lateral dimension of the second groove portion is smaller than the lateral dimension of the first groove portion.
As a preferable mode of the present invention, in step 7), an upper surface of the conductive plug is flush with an upper surface of the first trench portion.
As a preferable scheme of the present invention, in step 10), the first metal barrier layer, the second metal barrier layer, and the metal interconnection layer on the upper surface of the second dielectric layer are removed by using a chemical mechanical polishing process.
As a preferred embodiment of the present invention, the first dielectric layer and the second dielectric layer are both undoped silicon glass layers, the conductive metal layer is a tungsten metal layer, and the metal connecting line layer is a copper metal layer.
The present invention also provides a CMOS image sensor including:
the CMOS image sensor comprises a semiconductor substrate, a CMOS image sensor unit and a connecting welding pad, wherein the CMOS image sensor unit is internally provided with the connecting welding pad which is electrically connected with an internal functional device;
a plurality of semiconductor structures as described in any of the above, said conductive plugs in said semiconductor structures being in contact connection with said connection pads.
As described above, the semiconductor structure, the CMOS image sensor and the method for manufacturing the same provided by the present invention have the following advantages:
the semiconductor structure does not relate to a chemical mechanical grinding process of W in the preparation process, so that the production cost can be greatly saved; meanwhile, compared with the prior art, the preparation method of the semiconductor structure has fewer process steps and simpler process;
the CMOS image sensor does not involve a W chemical mechanical grinding process in the preparation process, so that the production cost can be greatly saved; meanwhile, compared with the prior art, the preparation method of the CMOS image sensor has fewer process steps and simpler process.
Drawings
Fig. 1 to 10 are flow charts illustrating the preparation of conductive plugs and metal interconnection layers in the prior art.
Fig. 11 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.
Fig. 12 to 21 are schematic partial cross-sectional views illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the invention; fig. 21 is a partial cross-sectional structural diagram of the semiconductor structure of the present invention.
Fig. 22 is a flowchart illustrating a method for manufacturing a CMOS image sensor according to a third embodiment of the present invention.
Fig. 23 to 33 are schematic partial cross-sectional structures corresponding to steps of a semiconductor structure manufacturing method according to a third embodiment of the present invention, where fig. 33 is a schematic partial cross-sectional structure of a CMOS image sensor according to the present invention.
Description of component reference numerals
10 semiconductor substrate
11 TEOS layer
12 first through hole
13 first metal barrier layer
14W metal layer
15W plug
16 SiN layer
17 USG layer
18 second through hole
19 second metal barrier layer
110 Cu metal layer
111 metal interconnection layer
20 semiconductor substrate
21 first dielectric layer
22 second dielectric layer
23 groove
231 first groove part
232 second groove part
24 first metal barrier layer
25 conductive metal layer
26 conductive plug
27 second metal barrier layer
28 Metal Wiring layer
29 CMOS image sensor cell
291 connection pad
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 11 to 33. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 11, the present invention provides a method for fabricating a semiconductor structure, which includes the following steps:
1) providing a semiconductor substrate, and sequentially forming a first dielectric layer and a second dielectric layer on the upper surface of the semiconductor substrate;
2) forming a groove in the first dielectric layer and the second dielectric layer, wherein the groove exposes part of the semiconductor substrate;
3) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer;
4) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer;
5) removing part of the conductive metal layer by adopting a back etching process to form a conductive plug, wherein the upper surface of the conductive plug is lower than that of the groove;
6) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug;
7) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer;
8) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer.
In step 1), referring to step S1 in fig. 11 and fig. 12 and 13, a semiconductor substrate 20 is provided, and a first dielectric layer 21 and a second dielectric layer 22 are sequentially formed on the upper surface of the semiconductor substrate 20.
By way of example, the semiconductor substrate 20 may be a silicon substrate, a sapphire substrate, a gallium nitride substrate, or the like; device structures requiring electrical extraction may be formed within the semiconductor substrate 20.
As an example, the first dielectric layer 21 may be, but is not limited to, an undoped silicate glass layer (USG layer), preferably, the first dielectric layer 21 is a TEOS (tetraethylorthosilicate) layer, and more preferably, in this embodiment, the first dielectric layer 21 is a TEOS (plasma enhanced tetraethylorthosilicate) layer formed by a PECVD (plasma enhanced chemical vapor deposition) process; the second dielectric layer 22 may be, but is not limited to, a USG (undoped silicate glass) layer, and more preferably, in this embodiment, the second dielectric layer 22 is an undoped silicate glass layer formed by a PECVD process.
In step 2), referring to step S2 in fig. 11 and fig. 14 to 15, a trench 23 is formed in the first dielectric layer 21 and the second dielectric layer 22, and the trench 23 exposes a portion of the semiconductor substrate 20.
As an example, forming a trench 23 in the first dielectric layer 21 and the second dielectric layer 22, wherein the trench 23 exposes a portion of the semiconductor substrate 20 includes the following steps:
2-1) forming a first trench 231 in the first dielectric layer 21 and the second dielectric layer 22 by using a photolithography and etching process, where the first trench 231 penetrates through the second dielectric layer 22 and extends into the first dielectric layer 21, as shown in fig. 14; specifically, a photoresist may be formed on the upper surface of the second dielectric layer 22, then the photoresist is patterned by a photolithography process to obtain a patterned photoresist, the patterned photoresist defines the shape and the position of the first trench portion 231, and finally, the second dielectric layer 22 and the first dielectric layer 21 are sequentially etched by a dry etching process, a wet etching process or a dry and wet combined etching process according to the patterned photoresist to form the first trench portion 231;
2-2) forming a second trench portion 232 below the bottom of the first trench portion 231 by using a photolithography and etching process, wherein the second trench portion 232 is communicated with the first trench portion 231 and penetrates through the first dielectric layer 21; the lateral dimension of the second groove portion 232 is smaller than the lateral dimension of the first groove portion 231; the first groove portion 231 and the second groove portion 232 commonly groove the groove 23, as shown in fig. 15; specifically, a photoresist may be formed on the upper surface of the structure obtained in step 3-1), then the photoresist is patterned by a photolithography process to obtain a patterned photoresist, the patterned photoresist defines the shape and the position of the second trench portion 232, and finally, the first dielectric layer 21 is etched by a dry etching process, a wet etching process, or an etching process combining a dry method and a wet method according to the patterned photoresist to form the second trench portion 232.
It should be noted that the trench 23 is used to form an interconnect structure to electrically lead out an electrical device in the semiconductor substrate 20, and therefore, the trench 23 needs to expose the electrical device that needs to be electrically led out.
In the invention, because the first dielectric layer 21 and the second dielectric layer 22 are etched together, a silicon nitride covering layer is not required to be arranged to facilitate the capture of an etching end point like the prior art, namely, compared with the prior art, the step of arranging the silicon nitride covering layer between the first dielectric layer 21 and the second dielectric layer 22 can be omitted, and compared with the prior art, the method has fewer process steps and is simpler in process.
In step 3), referring to step S3 of fig. 11 and fig. 16, a first metal barrier layer 24 is formed on the bottom and sidewalls of the trench 23 and the upper surface of the second dielectric layer 22.
For example, the first metal barrier layer 24 may be formed on the bottom and the sidewall of the trench 23 and the upper surface of the second dielectric layer 22 by any conventional deposition process, and preferably, in this embodiment, the first metal barrier layer 24 is formed on the bottom and the sidewall of the trench 23 and the upper surface of the second dielectric layer 22 by a chemical vapor deposition process.
As an example, the first metal barrier layer 24 may be any one that can block a subsequently formed conductive plug from diffusing into the first dielectric layer 21 and the semiconductor substrate 20, and does not affect the electrical connection between the conductive plug and the connection pad; the material of the first metal barrier layer 24 may be, but is not limited to, titanium nitride, titanium/titanium nitride, and the like.
By way of example, the thickness of the first metal barrier layer 24 may be set according to actual needs, and is not limited herein.
In step 4), please refer to step S4 in fig. 11 and fig. 17, a conductive metal layer 25 is formed on the surface of the first metal barrier layer 24, and the trench 23 is filled with the conductive metal layer 25.
As an example, any conventional deposition process may be used to form the conductive metal layer 25 on the surface of the first metal barrier layer 24, and preferably, in this embodiment, a chemical vapor deposition process is used to form the conductive metal layer 25 on the surface of the first metal barrier layer 24.
As an example, the conductive metal layer 25 may be, but is not limited to, a tungsten metal layer; in other examples, the conductive metal layer 25 may also be a copper metal layer, an aluminum metal layer, or the like.
In step 5), referring to step S5 in fig. 11 and fig. 18, a back etching process is performed to remove a portion of the conductive metal layer 25 to form a conductive plug 26, wherein an upper surface of the conductive plug 26 is lower than an upper surface of the trench 23.
As an example, a dry etching back process or a wet etching back process is used to remove a portion of the conductive metal layer 25, and the dry etching back process and the wet etching back process are well known to those skilled in the art and will not be described herein again.
As an example, an upper surface of the conductive plug 26 may be flush with an upper surface of the first trench portion 231. Of course, in other examples, the upper surface of the conductive plug 26 may also be adjusted according to actual needs to adjust the thickness of the conductive plug 26.
In the step, the chemical mechanical polishing process of W is replaced by the back etching process, so that high-loss W chemical mechanical polishing equipment with water consumption, power consumption and the like can be avoided, and the production cost can be greatly saved.
In step 6), referring to step S6 of fig. 11 and fig. 19, a second metal barrier layer 27 is formed on the surface of the first metal barrier layer 24 and the upper surface of the conductive plug 26.
For example, any conventional deposition process may be used to form the second metal barrier layer 27 on the surface of the first metal barrier layer 24 and the upper surface of the conductive plug 26, and preferably, in this embodiment, a chemical vapor deposition process is used to form the second metal barrier layer 27 on the surface of the first metal barrier layer 24 and the upper surface of the conductive plug 26.
As an example, the second metal barrier layer 27 may be any one that can prevent a metal interconnection layer formed subsequently from diffusing into the second dielectric layer 22 and the conductive plug 25, and does not affect the electrical connection between the metal interconnection layer and the conductive plug 25; the material of the second metal barrier layer 27 may be, but is not limited to, titanium nitride, tantalum nitride, titanium/titanium nitride, or the like.
By way of example, the thickness of the second metal barrier layer 27 may be set according to actual needs, and is not limited herein.
In step 7), please refer to step S7 in fig. 11 and fig. 20, a metal interconnection layer 28 is formed on the surface of the second metal barrier layer 27, and the metal interconnection layer 28 fills the trench 23.
For example, any conventional deposition process may be used to form the metal interconnection layer 28 on the surface of the second metal barrier layer 27, and preferably, in this embodiment, a chemical vapor deposition process is used to form the metal interconnection layer 28 on the surface of the second metal barrier layer 27.
By way of example, the metal interconnect layer 28 may be, but is not limited to, a copper metal layer; in other examples, the metal wiring layer 28 may also be an aluminum metal layer or the like.
In step 8), referring to step S8 in fig. 11 and fig. 21, the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnection layer 28 on the upper surface of the second dielectric layer 22 are removed.
For example, a chemical mechanical polishing process or an etching process may be used to remove the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnect layer 28 on the upper surface of the second dielectric layer 22, and preferably, in this embodiment, a chemical mechanical polishing process is used to remove the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnect layer 28 on the upper surface of the second dielectric layer 22.
As an example, the upper surfaces of the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnect layer 28 remaining after this step are all flush with the upper surface of the second dielectric layer 22.
Example two
With continuing reference to fig. 21 in conjunction with fig. 15, the present invention further provides a semiconductor structure on the upper surface of a semiconductor substrate 20, wherein the semiconductor structure can be prepared by, but is not limited to, the method for preparing a semiconductor structure described in the first embodiment, and the semiconductor structure comprises: the first dielectric layer 21, the first dielectric layer 21 is located on the upper surface of the semiconductor substrate 20; the second medium layer 22, the second medium layer 22 is positioned on the upper surface of the first medium layer 21; the trench 23 is located in the first dielectric layer 21 and the second dielectric layer 22, and penetrates through the first dielectric layer 21 and the second dielectric layer 22 up and down to expose a part of the semiconductor substrate 20; a first metal barrier layer 24, the first metal barrier layer 24 being located on sidewalls of the trench 23; a conductive plug 26, wherein the conductive plug 26 is located in the trench 23 inside the first metal barrier layer 24, and an upper surface of the conductive plug 26 is lower than an upper surface of the trench 23; a second metal barrier layer 27, said second metal barrier layer 27 being located on an upper surface of said conductive plug 26 and on a surface of said first metal barrier layer 24 above said conductive plug 26; a metal wiring layer 28, wherein the metal wiring layer 28 is filled in the trench 23 inside the second metal barrier layer 27.
By way of example, the semiconductor substrate 20 may be a silicon substrate, a sapphire substrate, a gallium nitride substrate, or the like; device structures requiring electrical extraction may be formed within the semiconductor substrate 20.
As an example, the groove 23 includes a first groove portion 231 and a second groove portion 232 located above the first groove portion 231 and communicating with the first groove portion 232, wherein a lateral dimension of the first groove portion 231 is smaller than a lateral dimension of the second groove portion 232.
It should be noted that the trench 23 is used to form an interconnect structure to electrically lead out an electrical device in the semiconductor substrate 20, and therefore, the trench 23 needs to expose the electrical device that needs to be electrically led out.
By way of example, the material of the first metal barrier layer 24 may be, but is not limited to, titanium nitride, titanium/titanium nitride, etc.; the material of the second metal barrier layer 27 may be, but is not limited to, titanium nitride, tantalum nitride, titanium/titanium nitride, or the like.
As an example, an upper surface of the conductive plug 26 is flush with an upper surface of the first groove portion 231.
As an example, the first dielectric layer 21 may be, but is not limited to, an undoped silicate glass layer (USG layer), preferably, the first dielectric layer 21 is a TEOS (tetraethylorthosilicate) layer, and more preferably, in this embodiment, the first dielectric layer 21 is a TEOS (plasma enhanced tetraethylorthosilicate) layer formed by a PECVD (plasma enhanced chemical vapor deposition) process, the second dielectric layer 22 is an undoped silicate glass layer, the conductive plug 26 is a tungsten metal plug, and the metal connecting line layer 28 is a copper metal layer.
Illustratively, the upper surface of the metal interconnect layer 28 is flush with the upper surface of the second dielectric layer 22.
It should be noted that the semiconductor structure of this embodiment refers to the portion of fig. 21 where the semiconductor substrate 20 is removed, that is, the semiconductor structure does not include the semiconductor substrate 20, and the semiconductor substrate 20 is shown only for convenience of showing the position of the semiconductor structure.
EXAMPLE III
Referring to fig. 22, the present invention further provides a method for manufacturing a CMOS image sensor, where the method for manufacturing a CMOS image sensor includes the following steps:
1) providing a semiconductor substrate;
2) forming a CMOS image sensor unit in the semiconductor substrate, wherein a connecting welding pad electrically connected with an internal functional device of the CMOS image sensor unit is formed in the CMOS image sensor unit;
3) forming a first dielectric layer on the upper surface of the semiconductor substrate, and forming a second dielectric layer on the upper surface of the first dielectric layer;
4) forming grooves in the first dielectric layer and the second dielectric layer, wherein the grooves expose the connecting welding pads;
5) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer;
6) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer;
7) removing part of the conductive metal layer by adopting a back etching process to obtain a conductive plug, wherein the upper surface of the conductive plug is lower than that of the groove;
8) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug;
9) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer;
10) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer.
In step 1), referring to step S1 in fig. 22 and fig. 23, a semiconductor substrate 20 is provided.
By way of example, the semiconductor substrate 20 may be, but is not limited to, a silicon substrate, a sapphire substrate, a gallium nitride substrate, or the like.
In step 2), referring to step S2 in fig. 22 and fig. 24, a CMOS image sensor unit 29 is formed in the semiconductor substrate 20, and a connection pad 291 electrically connected to an internal functional device of the CMOS image sensor unit 29 is formed in the CMOS image sensor unit 29.
As an example, the connection pad 291 may be, but is not limited to, an aluminum pad (Al pad).
The specific method for forming the CMOS image sensor cell 29 in the semiconductor substrate 20 is well known to those skilled in the art and will not be described herein.
In step 3), referring to step S3 of fig. 22 and fig. 25, a first dielectric layer 21 is formed on the upper surface of the semiconductor substrate 20, and a second dielectric layer 22 is formed on the upper surface of the first dielectric layer 21.
As an example, the first dielectric layer 21 may be, but is not limited to, an undoped silicate glass layer (USG layer), preferably, the first dielectric layer 21 is a TEOS (tetraethylorthosilicate) layer, and more preferably, in this embodiment, the first dielectric layer 21 is a TEOS (plasma enhanced tetraethylorthosilicate) layer formed by a PECVD (plasma enhanced chemical vapor deposition) process; the second dielectric layer 22 may be, but is not limited to, a USG (undoped silicate glass) layer, and more preferably, in this embodiment, the second dielectric layer 22 is an undoped silicate glass layer.
In step 4), referring to step S4 in fig. 22 and fig. 26 and 27, a trench 23 is formed in the first dielectric layer 21 and the second dielectric layer 22, and the trench 23 exposes the connection pad 291.
As an example, forming the trench 23 in the first dielectric layer 21 and the second dielectric layer 22, wherein the trench 23 exposes the connection pad 291 includes the following steps:
4-1) forming a first trench 231 in the first dielectric layer 21 and the second dielectric layer 22 by using a photolithography and etching process, where the first trench 231 penetrates through the second dielectric layer 22 and extends into the first dielectric layer 21, as shown in fig. 26; specifically, a photoresist may be formed on the upper surface of the second dielectric layer 22, then the photoresist is patterned by a photolithography process to obtain a patterned photoresist, the patterned photoresist defines the shape and the position of the first trench portion 231, and finally, the second dielectric layer 22 and the first dielectric layer 21 are sequentially etched by a dry etching process, a wet etching process or a dry and wet combined etching process according to the patterned photoresist to form the first trench portion 231;
4-2) forming a second trench portion 232 below the bottom of the first trench portion 231 by using a photolithography and etching process, wherein the second trench portion 232 is communicated with the first trench portion 231 and penetrates through the first dielectric layer 21; the lateral dimension of the second groove portion 232 is smaller than the lateral dimension of the first groove portion 231; the first groove portion 231 and the second groove portion 232 commonly groove the groove 23, as shown in fig. 27; specifically, a photoresist may be formed on the upper surface of the structure obtained in step 4-1), then the photoresist is patterned by a photolithography process to obtain a patterned photoresist, the patterned photoresist defines the shape and the position of the second trench portion 232, and finally, the first dielectric layer 21 is etched by a dry etching process, a wet etching process, or an etching process combining a dry method and a wet method according to the patterned photoresist to form the second trench portion 232.
In the invention, because the first dielectric layer 21 and the second dielectric layer 22 are etched together, a silicon nitride covering layer is not required to be arranged to facilitate the capture of an etching end point like the prior art, namely, compared with the prior art, the step of arranging the silicon nitride covering layer between the first dielectric layer 21 and the second dielectric layer 22 can be omitted, and compared with the prior art, the method has fewer process steps and is simpler in process.
In step 5), referring to step S5 in fig. 22 and fig. 28, a first metal barrier layer 24 is formed on the bottom and sidewalls of the trench 23 and the upper surface of the second dielectric layer 22.
For example, the first metal barrier layer 24 may be formed on the bottom and the sidewall of the trench 23 and the upper surface of the second dielectric layer 22 by any conventional deposition process, and preferably, in this embodiment, the first metal barrier layer 24 is formed on the bottom and the sidewall of the trench 23 and the upper surface of the second dielectric layer 22 by a chemical vapor deposition process.
As an example, the first metal barrier layer 24 may be any one that can block a subsequently formed conductive plug from diffusing into the first dielectric layer 21 and the semiconductor substrate 20, and does not affect the electrical connection between the conductive plug and the connection pad; the material of the first metal barrier layer 24 may be, but is not limited to, titanium nitride, titanium/titanium nitride, and the like.
By way of example, the thickness of the first metal barrier layer 24 may be set according to actual needs, and is not limited herein.
In step 6), referring to step S6 in fig. 22 and fig. 29, a conductive metal layer 25 is formed on the surface of the first metal barrier layer 24, and the trench 23 is filled with the conductive metal layer 25.
As an example, any conventional deposition process may be used to form the conductive metal layer 25 on the surface of the first metal barrier layer 24, and preferably, in this embodiment, a chemical vapor deposition process is used to form the conductive metal layer 25 on the surface of the first metal barrier layer 24.
As an example, the conductive metal layer 25 may be, but is not limited to, a tungsten metal layer; in other examples, the conductive metal layer 25 may also be a copper metal layer, an aluminum metal layer, or the like.
In step 7), referring to step S7 in fig. 22 and fig. 30, a back etching process is used to remove a portion of the conductive metal layer 25 to obtain a conductive plug 26, wherein an upper surface of the conductive plug 26 is lower than an upper surface of the trench 23.
As an example, a dry etching back process or a wet etching back process is used to remove a portion of the conductive metal layer 25, and the dry etching back process and the wet etching back process are well known to those skilled in the art and will not be described herein again.
As an example, an upper surface of the conductive plug 26 may be flush with an upper surface of the first trench portion 231. Of course, in other examples, the upper surface of the conductive plug 26 may also be adjusted according to actual needs to adjust the thickness of the conductive plug 26.
In the step, the chemical mechanical polishing process of W is replaced by the back etching process, so that high-loss W chemical mechanical polishing equipment with water consumption, power consumption and the like can be avoided, and the production cost can be greatly saved.
In step 8), referring to step S8 in fig. 22 and fig. 31, a second metal barrier layer 27 is formed on the surface of the first metal barrier 24 and the upper surface of the conductive plug 26.
For example, any conventional deposition process may be used to form the second metal barrier layer 27 on the surface of the first metal barrier layer 24 and the upper surface of the conductive plug 26, and preferably, in this embodiment, a chemical vapor deposition process is used to form the second metal barrier layer 27 on the surface of the first metal barrier layer 24 and the upper surface of the conductive plug 26.
As an example, the second metal barrier layer 27 may be any one that can prevent a metal interconnection layer formed subsequently from diffusing into the second dielectric layer 22 and the conductive plug 25, and does not affect the electrical connection between the metal interconnection layer and the conductive plug 25; the material of the second metal barrier layer 27 may be, but is not limited to, titanium nitride, tantalum nitride, titanium/titanium nitride, or the like.
By way of example, the thickness of the second metal barrier layer 27 may be set according to actual needs, and is not limited herein.
In step 9), please refer to S9 in fig. 22 and fig. 32, a metal interconnection layer 28 is formed on the surface of the second metal barrier layer 27, and the metal interconnection layer 28 fills the trench 23.
For example, any conventional deposition process may be used to form the metal interconnection layer 28 on the surface of the second metal barrier layer 27, and preferably, in this embodiment, a chemical vapor deposition process is used to form the metal interconnection layer 28 on the surface of the second metal barrier layer 27.
By way of example, the metal interconnect layer 28 may be, but is not limited to, a copper metal layer; in other examples, the metal wiring layer 28 may also be an aluminum metal layer or the like.
In step 10), referring to step S10 in fig. 22 and fig. 33, the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnection layer 28 on the upper surface of the second dielectric layer 22 are removed.
For example, a chemical mechanical polishing process or an etching process may be used to remove the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnect layer 28 on the upper surface of the second dielectric layer 22, and preferably, in this embodiment, a chemical mechanical polishing process is used to remove the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnect layer 28 on the upper surface of the second dielectric layer 22.
As an example, the upper surfaces of the first metal barrier layer 24, the second metal barrier layer 27 and the metal interconnect layer 28 remaining after this step are all flush with the upper surface of the second dielectric layer 22.
Example four
With continuing reference to fig. 33, the present invention further provides a CMOS image sensor, comprising:
a semiconductor substrate 20, a CMOS image sensor unit 29 is formed in the semiconductor substrate 20, and a connection pad 291 electrically connected with an internal functional device of the CMOS image sensor unit 29 is formed in the CMOS image sensor unit 29;
a plurality of semiconductor structures as described in embodiment two, the conductive plugs 26 in the semiconductor structures are connected to the connection pad contacts 291. For a specific structure of the semiconductor structure, please refer to embodiment two, which will not be described herein.
As an example, the connection pad 291 may be, but is not limited to, an aluminum pad.
In summary, the present invention provides a semiconductor structure, a CMOS image sensor and a method for manufacturing the same, wherein the method for manufacturing the semiconductor structure includes the following steps: 1) providing a semiconductor substrate, and sequentially forming a first dielectric layer and a second dielectric layer on the upper surface of the semiconductor substrate; 2) forming a groove in the first dielectric layer and the second dielectric layer, wherein the groove exposes part of the semiconductor substrate; 3) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer; 4) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer; 5) removing part of the conductive metal layer by adopting a back etching process to form a conductive plug, wherein the upper surface of the conductive plug is lower than that of the groove; 6) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug; 7) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer; 8) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer. The semiconductor structure does not relate to a chemical mechanical grinding process of W in the preparation process, so that the production cost can be greatly saved; meanwhile, compared with the prior art, the preparation method of the semiconductor structure has fewer process steps and simpler process; the CMOS image sensor does not involve a W chemical mechanical grinding process in the preparation process, so that the production cost can be greatly saved; meanwhile, compared with the prior art, the preparation method of the CMOS image sensor has fewer process steps and simpler process.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A method for manufacturing a semiconductor structure, the method comprising:
1) providing a semiconductor substrate, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the upper surface of the semiconductor substrate, the first dielectric layer is a TEOS layer, and the second dielectric layer is a USG layer;
2) forming a groove in the first dielectric layer and the second dielectric layer, wherein the groove exposes part of the semiconductor substrate, the groove comprises a first groove part and a second groove part which is positioned below the first groove part and communicated with the first groove part, and the transverse dimension of the second groove part is smaller than that of the first groove part;
3) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer;
4) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer;
5) removing a part of the conductive metal layer by adopting a back etching process to form a conductive plug, wherein the upper surface of the conductive plug is lower than the upper surface of the groove, and the upper surface of the conductive plug is flush with the upper surface of the second groove part;
6) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug;
7) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer;
8) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein in step 8), the first metal barrier layer, the second metal barrier layer and the metal interconnection layer on the upper surface of the second dielectric layer are removed by a chemical mechanical polishing process.
3. The method of claim 1, wherein the conductive metal layer is a tungsten metal layer and the metal interconnect layer is a copper metal layer.
4. A semiconductor structure on an upper surface of a semiconductor substrate, the semiconductor structure comprising:
the first dielectric layer is positioned on the upper surface of the semiconductor substrate and is a TEOS layer;
the second dielectric layer is positioned on the upper surface of the first dielectric layer and is a USG layer;
the groove is positioned in the first dielectric layer and the second dielectric layer and penetrates through the first dielectric layer and the second dielectric layer up and down to expose part of the semiconductor substrate, the groove comprises a first groove part and a second groove part which is positioned below the first groove part and communicated with the first groove part, and the transverse size of the second groove part is smaller than that of the first groove part;
the first metal barrier layer is positioned on the side wall of the groove;
the conductive plug is positioned in the groove on the inner side of the first metal barrier layer, the upper surface of the conductive plug is lower than that of the groove, and the upper surface of the conductive plug is flush with that of the second groove part;
the second metal barrier layer is positioned on the upper surface of the conductive plug and the surface of the first metal barrier layer above the conductive plug;
and the metal connecting wire layer is filled in the groove on the inner side of the second metal barrier layer.
5. The semiconductor structure of claim 4, wherein the conductive plug is a tungsten metal plug and the metal interconnect layer is a copper metal layer.
6. The semiconductor structure of claim 4, wherein an upper surface of the metal wiring layer is flush with an upper surface of the second dielectric layer.
7. A method for manufacturing a CMOS image sensor is characterized by comprising the following steps:
1) providing a semiconductor substrate;
2) forming a CMOS image sensor unit in the semiconductor substrate, wherein a connecting welding pad electrically connected with an internal functional device of the CMOS image sensor unit is formed in the CMOS image sensor unit;
3) forming a first dielectric layer on the upper surface of the semiconductor substrate, and forming a second dielectric layer on the upper surface of the first dielectric layer, wherein the first dielectric layer is a TEOS layer, and the second dielectric layer is a USG layer;
4) forming a groove in the first dielectric layer and the second dielectric layer, wherein the groove exposes the connecting welding pad, the groove comprises a first groove part and a second groove part which is positioned below the first groove part and communicated with the first groove part, and the transverse size of the second groove part is smaller than that of the first groove part;
5) forming a first metal barrier layer on the bottom and the side wall of the groove and the upper surface of the second dielectric layer;
6) forming a conductive metal layer on the surface of the first metal barrier layer, wherein the groove is filled with the conductive metal layer;
7) removing part of the conductive metal layer by adopting a back etching process to obtain a conductive plug, wherein the upper surface of the conductive plug is lower than the upper surface of the groove, and the upper surface of the conductive plug is flush with the upper surface of the second groove part;
8) forming a second metal barrier layer on the surface of the first metal barrier layer and the upper surface of the conductive plug;
9) forming a metal connecting line layer on the surface of the second metal barrier layer, wherein the groove is filled with the metal connecting line layer;
10) and removing the first metal barrier layer, the second metal barrier layer and the metal connecting line layer which are positioned on the upper surface of the second dielectric layer.
8. The method for manufacturing a CMOS image sensor according to claim 7, wherein in step 10), the first metal barrier layer, the second metal barrier layer and the metal interconnection layer on the upper surface of the second dielectric layer are removed by a chemical mechanical polishing process.
9. The method of claim 7, wherein the conductive metal layer is a tungsten metal layer and the metal interconnect layer is a copper metal layer.
10. A CMOS image sensor, comprising:
the CMOS image sensor comprises a semiconductor substrate, a CMOS image sensor unit and a connecting welding pad, wherein the CMOS image sensor unit is internally provided with the connecting welding pad which is electrically connected with an internal functional device;
a number of semiconductor structures as claimed in any one of claims 4 to 6, the electrically conductive plugs within the semiconductor structures being in contact connection with the connection pads.
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