CN107946234A - Semiconductor interconnection structure and preparation method thereof - Google Patents
Semiconductor interconnection structure and preparation method thereof Download PDFInfo
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- CN107946234A CN107946234A CN201711155061.5A CN201711155061A CN107946234A CN 107946234 A CN107946234 A CN 107946234A CN 201711155061 A CN201711155061 A CN 201711155061A CN 107946234 A CN107946234 A CN 107946234A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 218
- 239000002184 metal Substances 0.000 claims abstract description 218
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000000151 deposition Methods 0.000 claims abstract description 32
- 238000011049 filling Methods 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 230000006911 nucleation Effects 0.000 claims abstract description 9
- 238000010899 nucleation Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims description 15
- 238000004062 sedimentation Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000000376 reactant Substances 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 21
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005429 filling process Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
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- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- CCEKAJIANROZEO-UHFFFAOYSA-N sulfluramid Chemical group CCNS(=O)(=O)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)F CCEKAJIANROZEO-UHFFFAOYSA-N 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of semiconductor interconnection structure and preparation method thereof.Preparation method includes step：1）A substrate is provided, substrate is interior need to carry out metal filled contact hole formed with least one, and contact hole has hole side wall and bottom hole portion；2）In formation metal nucleation layer on the hole side wall and bottom hole portion of the upper surface of substrate and contact hole；3）In depositing the first metal layer on nucleating layer under the first temperature conditionss；4）In depositing second metal layer on the first metal layer under the conditions of second temperature, wherein, second temperature is more than the first temperature.Bonding between each film layer of semiconductor interconnection structure prepared by the preparation method of semiconductor interconnection structure using the present invention is more close, and there is no hole, therefore the overall resistivity for the contact hole that final filling is completed declines, it is avoided that the problems such as open circuit, loose contact or even component failure for causing device because of hole and high resistance, so as to effectively improve device performance and production yield, production cost is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor interconnection structure and preparation method thereof.
Background technology
In semiconductor devices manufacture, the manufacture of interconnection structure is very important part.So-called interconnection structure
(interconnect) typically refer to connect each absolute construction in same chip so that device can realize certain work(
The structure of energy, and the interconnection structure positioned at diverse location is generally assigned different titles, such as active area, polysilicon and metal
Interconnection structure between layer is commonly referred to as contact hole (contact), and the connection between different metal layers is then frequently referred to through hole
(via).Either contact hole or through hole, it is typically all to pass through toward filling metal in contact hole/through hole so that different knots
Realize and be electrically connected between structure.With the rapid development of semiconductor fabrication, the integrated level of semiconductor product is higher and higher, component
Critical dimension reduction to less than 30 nanometers so that interconnection structure manufacture facing challenges it is increasing.Because in unit area
Component count be continuously increased, original plane routing cannot meet the requirements and can only use polylaminate wiring technique, that is, fill
Divide the vertical space of expensive chip, be largely electrically connected between the wiring of each layer using interconnection structures such as contact hole/through holes, with
The integration density of device is further improved, but in Miltilayer wiring structure, the depth-to-width ratio (aspect ratio) of contact hole/through hole is more
Carry out bigger, contact hole/through hole with existing PVD sputtering methods or single high temperature CVD deposition method toward this high-aspect-ratio
Interior filling metal is increasingly difficult to, and is easy to hole as shown in Figure 1 occur with contact hole/through hole that existing method is filled
Hole 10 (void) causes device generation open circuit etc. bad, in addition, because the resistance of the metal of filling is too high so that device contacts
It is bad, delay increase the problems such as cause device performance decline in addition fail, and ultimately result in production yield decline and production cost
Rise.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of semiconductor interconnection structure and its
Preparation method, for solving easily occur hole and filling in the metal fill process of contact hole/through hole in the prior art
Metallic resistance too it is high cause device occur open circuit, loose contact even component failure the problems such as.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of semiconductor interconnection structure,
The preparation method of the semiconductor interconnection structure includes at least following steps：1) substrate is provided, the substrate is interior formed with extremely
Few need carry out metal filled contact hole, and the contact hole has hole side wall and bottom hole portion；2) in the upper table of the substrate
Metal nucleation layer is formed on the hole side wall and the bottom hole portion of face and the contact hole；3) in institute under the first temperature conditionss
State and the first metal layer is deposited on nucleating layer；Wherein, the first metal layer covers the nucleating layer, and the first metal layer includes
Positioned at the first position in the bottom hole portion and positioned at the hole side wall and the second position of the connection first position, described the
One position vertically to thickness and the second position be more than or equal to 1 in both ratios of horizontal direction thickness, it is and described
First position vertically to thickness be less than or equal to the contact hole the vertical half to depth；4) in second temperature bar
In depositing second metal layer on the first metal layer under part, the second metal layer fills up the contact hole and is forming described the
Gap after one metal layer, deposits material identical of the material of the second metal layer with depositing the first metal layer, described
Second temperature is more than first temperature.
Preferably, in the step 1), the depth-to-width ratio of the contact hole is more than 2.
Preferably, in the step 2), in the step 2), the nucleating layer is formed using chemical vapor deposition method,
Reactant for forming the nucleating layer includes tungsten hexafluoride (WF6) and silane (SiH4)；In the step 3), using chemistry
Gas-phase deposition deposits the first metal layer, and the reactant for forming the first metal layer includes tungsten hexafluoride
(WF6) and hydrogen (H2)；In the step 4), the second metal layer is deposited using chemical vapor deposition method, for being formed
The reactant for stating second metal layer includes tungsten hexafluoride (WF6) and hydrogen (H2)。
Preferably, in the step 2), the temperature of the nucleating layer is formed between 250 DEG C~300 DEG C, the nucleating layer
Sedimentation time between 40s~50s, the thickness of the nucleating layer between
Preferably, in the step 3), first temperature is between 250 DEG C~300 DEG C；In the step 4), described
Two temperature are between 390 DEG C~400 DEG C.
It is highly preferred that in the step 3), the sedimentation time of the first metal layer is between 80s~90s, first gold medal
Belong to layer thickness betweenIn the step 4), the sedimentation time of the second metal layer between 120s~
150s, the thickness of the second metal layer between
Preferably, further include before the step 2) and stop in forming bonding on the substrate surface and in the contact hole
The step of layer, in the step 2), the nucleating layer is formed on the bonding barrier layer.
Preferably, also included step after the step 4)：The structure obtained to the step 4) carries out chemical machinery
Grinding, to remove the nucleating layer of the substrate top surface, the first metal layer and the second metal layer.
Preferably, the resistivity of the first metal layer of the step 3) deposition is less than the described of the step 4) deposition
The resistivity of second metal layer, and the contact hole that the step 4) fills completion afterwards does not have hole.
The present invention also provides a kind of semiconductor interconnection structure, the semiconductor interconnection structure includes：Substrate, nucleating layer,
One metal layer and second metal layer；There is hole side wall and hole formed with least one contact hole, the contact hole in the substrate
Bottom；The nucleating layer is covered in the hole side wall of the contact hole and the bottom hole portion；The first metal layer is located at institute
State in contact hole and cover the nucleating layer in the contact hole；The first metal layer includes being located at the bottom hole portion
First position and positioned at the hole side wall and the second position of the connection first position, the first position vertically to
Thickness and the second position be more than or equal to 1 in both ratios of horizontal direction thickness, and the first position is vertical
To thickness be less than or equal to the contact hole the vertical half to depth；The second metal layer is located at the contact hole
The first metal layer interior and that covering is in the contact hole, the second metal layer fill up the contact hole and are forming institute
State the gap after the first metal layer and the material of the second metal layer is identical with the material of the first metal layer.
Preferably, the depth-to-width ratio of the contact hole in the semiconductor interconnection structure is more than 2.
Preferably, the second metal layer and the phase same material of the first metal layer include tungsten.
Preferably, the semiconductor interconnection structure further includes bonding barrier layer, and the bonding barrier layer is located at the contact
In hole and it is formed between the nucleating layer and the substrate, to be used as the engagement liner between the nucleating layer and the substrate
And separation layer and play the protection substrate.
The present invention also provides another semiconductor interconnection structure, the semiconductor interconnection structure includes：Substrate, nucleation
Layer, the first metal layer and second metal layer；There is hole side wall formed with least one contact hole, the contact hole in the substrate
With bottom hole portion；The nucleating layer is covered in upper surface and the hole side wall of the contact hole and the bottom hole of the substrate
Portion；The first metal layer is located in top and the contact hole of the substrate, and positioned at the upper surface of the nucleating layer；Its
In, the first metal layer is included positioned at the first position in the bottom hole portion and positioned at the hole side wall and connection described first
The second position at position, the first position vertically to thickness and the second position horizontal direction thickness both ratio
Value is more than or equal to 1, and the thickness of the first metal layer is more than the thickness of the nucleating layer；The second metal layer is positioned at described
On substrate and in the contact hole and the first metal layer in the contact hole is covered, and two metal layer is also
Covering is located at the first metal layer of the top of the substrate, and the second metal layer fills up the contact hole described in formation
Gap after the first metal layer；The material of the second metal layer is identical with the material of the first metal layer and second gold medal
The thickness for belonging to layer is more than the thickness of the first metal layer.
Preferably, the depth-to-width ratio of the contact hole in the semiconductor interconnection structure is more than 2.
Preferably, the second metal layer of the semiconductor interconnection structure and the phase same material bag of the first metal layer
Tungstenic.
Preferably, the semiconductor interconnection structure further includes bonding barrier layer, and the bonding barrier layer is located at the nucleation
Between layer and the substrate, using as described in the engagement liner between the nucleating layer and the substrate and separation layer and a protection
The effect of substrate.
As described above, semiconductor interconnection structure of the present invention and preparation method thereof, has the advantages that：The present invention's
The preparation method of semiconductor interconnection structure, the metal filled of contact hole/through hole is carried out the step of by increasing low temperature depositing, can be kept away
Exempt to produce hole in the filling process of contact hole/through hole, and the resistance of contact hole/through hole of filling can be reduced, to avoid
The problems such as causing the open circuit, loose contact or even component failure of device because of hole and high resistance, and preparation method is simple；Using this
Semiconductor interconnection structure prepared by the preparation method of the semiconductor interconnection structure of invention does not have a hole, and resistance it is relatively low so that
The performance of device is greatly improved and effectively improves production yield.
Brief description of the drawings
Fig. 1 is shown as the hole schematic diagram produced in the contact metal filling process of the prior art.
Fig. 2 is shown as the flow chart of the preparation method of the semiconductor interconnection structure of the embodiment of the present invention one.
Fig. 3 and Fig. 7 is shown as each step in the preparation method of the semiconductor interconnection structure of the embodiment of the present invention one and is presented
The cross section structure schematic diagram of the semiconductor interconnection structure gone out.
Fig. 8 is shown as the cross section structure schematic diagram of the semiconductor interconnection structure of the embodiment of the present invention two.
Fig. 9 is shown as the cross section structure schematic diagram of the semiconductor interconnection structure of the embodiment of the present invention three.
Reference numerals explanation
1 substrate
10 holes
11 contact holes
11a bottom holes portion
11b holes side wall
121 nucleating layers
122 the first metal layers
122a first positions
122b second positions
123 second metal layers
124 pits
13 bonding barrier layers
2 semiconductor structures
3 semiconductor structures
D1 first positions vertically to thickness
H1 second positions are in horizontal direction thickness
The bottom thickness of d2 second metal layers
The sidewall thickness of h2 second metal layers
D3 is located at the thickness of the first metal layer in substrate top surface
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
1 is referred to Fig. 9.It should be noted that the diagram provided in the present embodiment only illustrates this hair in a schematic way
Bright basic conception, then in schema only the display component related with the present invention rather than component count during according to actual implementation,
Shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its component
Arrangement form may also be increasingly complex.
Embodiment one
It refer to Fig. 2 and Fig. 9.As shown in Fig. 2, the present invention provides a kind of preparation method of semiconductor interconnection structure, it is described
The preparation method of semiconductor interconnection structure includes at least following steps：
1) substrate is provided, the substrate is interior need to carry out metal filled contact hole, the contact formed with least one
Hole has hole side wall and bottom hole portion；
2) in the hole side wall of the upper surface of the substrate and the contact hole with the bottom hole portion formed metal into
Stratum nucleare；
3) under the first temperature conditionss in depositing the first metal layer on the nucleating layer；Wherein, the first metal layer covers
The nucleating layer is covered, the first metal layer is included positioned at the first position in the bottom hole portion and positioned at the hole side wall and company
Connect the second position of the first position, the first position vertically to thickness and the second position it is thick in horizontal direction
Both ratios of degree are more than or equal to 1, and the first position vertically to thickness be less than or equal to the vertical of the contact hole
To the half of depth；
4) filled up under the conditions of second temperature in depositing second metal layer on the first metal layer, the second metal layer
Gap of the contact hole after the first metal layer is formed, deposits the material and deposition described first of the second metal layer
The material identical of metal layer, the second temperature are more than first temperature.
Refer to the step S1 and Fig. 3 in Fig. 2, carry out step S1 first, there is provided a substrate 1, in the substrate 1 formed with
At least one to carry out metal filled contact hole 11, the contact hole 11 has hole side wall 11b and bottom hole portion 11a.
As an example, 1 surface of substrate is generally also formed with other structures in addition to the contact hole 11, for example, it is active
Layer, oxide skin(coating) and dielectric layer, and the contact hole 11 is usually formed by etching the oxide skin(coating) and the dielectric layer.
The present embodiment is only for emphasis introduces the metal filled method of the contact hole 11 and the preparation process of other structures is not unfolded.
As an example, the contact hole 11 can be the contact hole of high-aspect-ratio, it is specifically, described to connect in the present embodiment
The depth-to-width ratio of contact hole 11 can with but be not limited only to be more than 2.
The step S2 and Fig. 5 in Fig. 2 are refer to, step S2 is then carried out, in the upper surface of the substrate 1 and the contact
Metal nucleation layer 121 is formed on the hole side wall 11b and the bottom hole portion 11a in hole 11.
The nucleating layer 121 usually plays Seed Layer, its material is usually that some resistance are relatively small, it is preferable to have
Electromigration resistance properties, the material for the advantages that being easy to deposit and etching, the common filling metal of early stage has aluminium and copper, but in height
The contact hole of depth-to-width ratio, especially depth-to-width ratio more than 2 it is metal filled in, the application of tungsten is more and more because tungsten have it is preferable
Electromigration resistance properties and preferable step coverage rate.Certainly, deposit 121 material of nucleating layer it is specific select need to consider and
The matching of metal is filled in follow-up filling process.
As an example, preferably whole filling process fills same metal, such as tungsten in the present embodiment.In this step due to
Reactant has the process of an original fusion with the substrate 1, therefore 121 surface of the nucleating layer formed is usually relatively rougher
And easily cause resistance higher containing impurity, therefore for so that the resistance reduction for the contact hole 11 finally filled, this step
In sedimentation time it is usually shorter so that the thicknesses of layers of deposition is as far as possible thin in the case where meeting that follow-up filling requires.Specifically
, in the step S2 of the present embodiment, using chemical vapor deposition method, under 250 DEG C~300 DEG C of technological temperature, lead to
Cross tungsten hexafluoride (WF6) and silane (SiH4) reaction generation tungsten, by the sedimentation time of 40s~50s in 1 upper table of substrate
Formed on the hole side wall 11b and the bottom hole portion 11a of face and the contact hole 11 thickness betweenInstitute
Nucleating layer 121 is stated, more preferably, the deposit thickness of the nucleating layer 121 isAnd the deposition process of the nucleating layer 121 is usual
It is to be carried out in a manner of multiple cycles (cycle), such as, in point 5 cycles, each cycle is 10s, is passed through within each cycle
Pulsed supply mode is passed through WF successively6And SiH4, and discharge exhaust gas and byproduct of reaction after each end cycle, with this
The nucleating layer 121 that the mode of the cycle deposition of sample deposits has relatively good uniformity and crystal orientation is good, can be described connect
The follow-up filling of contact hole 11 is laid a good foundation.
To make the nucleating layer 121 and the substrate 1 have preferable adhesion and avoiding carrying out the contact hole 11
Fluorine (F) atom or other corrosive materials cause to damage to the substrate 1 during filling hole, are forming the nucleating layer
It is additionally included in before 121 in 1 surface of substrate and the contact hole 11 and forms bonding barrier layer 13,121 shape of nucleating layer
Described in Cheng Yu bind barrier layer 13 upper surface, specifically refer to shown in Fig. 4, it is described bonding barrier layer 13 be formed at it is described into
Between stratum nucleare 121 and the substrate 1, using as the engagement liner between the nucleating layer 121 and the substrate 1 and separation layer and
Play the protection substrate 1.It is described bonding barrier layer 13 material include Ti and TiN, such as the Ti layers being sequentially depositing with
TiN layer, and the thickness on the bonding barrier layer 13 also should not be too thick, general control existsLeft and right.
It should be noted that it is for ease of measurement and management and control, the formation thickness described in the stepIt is described
Nucleating layer 121 refers to that the thickness that the nucleating layer 121 to be formed is located at the part of 1 upper surface of substrate isAnd
Schematic diagram in the present embodiment is only the position relationship of signal each several part rather than the considered critical to each structure.
The S3 and Fig. 6 in Fig. 2 are refer to, step S3 is then carried out, on the nucleating layer 121 under the first temperature conditionss
Deposit the first metal layer 122；Wherein, the first metal layer 122 covers the nucleating layer 121, and the first metal layer 122 wraps
Include positioned at the first position 122a of the bottom hole portion 11a and positioned at the hole side wall 11b and the connection first position 122a
Second position 122b, the first position 122a vertically to thickness d 1 and the second position 122b it is thick in horizontal direction
Both ratios for spending h1 are more than or equal to 1, and the first position 122a vertically to thickness d 1 be less than or equal to the contact
The vertical half to depth in hole 11.Specifically, this step uses H2And WF6, pass through H2Restore WF6In tungsten with heavy
Product forms tungsten layer.H in theory2Reduce WF6Process be that comparison is violent, especially technological temperature it is higher in the case of, H2With
WF6The tungsten film that fast reaction is formed easily seals the contact hole 11 so that gas molecule can not enter back into the contact hole 11
Hole is formed in the interior and metal layer that causes finally to fill.But make in the step S3 in this implementation because technological temperature is reduced
Obtain WF6Thermal decomposition reduce, H2Reduce WF6Reaction slow down so as to 11 upper end of contact hole opening portion formed tungsten film
Reduce without the opening of the contact hole 11 is sealed, more H2Molecule and WF6Molecule enters described 11 times petiolareas of contact hole
Domain simultaneously reacts, and finally forms one layer of fine and close the first metal layer 122 in the upper surface of the nucleating layer 121.Described first
Metal layer 122 not only binds very well with the nucleating layer 121, but also resistance ratio is relatively low, and relatively low technological temperature can cause F
The damage of substrate 1 described in atom pair and the bonding barrier layer 13 reduces and avoids producing volcanic crater (Volcano) defect.But compared with
Low technological temperature causes sedimentation time elongated, and to take into account productivity, the sedimentation time of this step is also unsuitable too long.Specifically,
In the step S3 of the present embodiment, using chemical vapor deposition method, under 250 DEG C~300 DEG C of technological temperature, pass through
WF6And H2Reaction, by 80s~90s sedimentation time in the nucleating layer 121 upper surface formed thickness beThe first metal layer 122, more preferably, the deposit thickness of the first metal layer 122 isEqually
, in this step also preferably the first metal layer 122 is formed by the way of the cycle deposits.Also, the institute deposited under the conditions of this
The first metal layer 122 is stated, it is located at the thickness d 1 of the bottom hole portion 11a of the contact hole 11 with being located at the hole side of the contact hole 11
The ratio between thickness h 1 of wall 11b is greater than or equal to 1.
As an example, the side-wall step coverage rate of the first metal layer 122 can be but be not limited only to 1.Need to illustrate
, " the side-wall step coverage rate of the first metal layer 122 " described herein refer to the hole side wall 11b positioned at the contact hole 11
The first metal layer 122 thickness h 1 and the thickness d 3 of the first metal layer 122 on 1 upper surface of substrate
Ratio.In addition, the formation thickness described in the step isThe first metal layer 122 refer to the institute to be formed
The thickness for stating the part that the first metal layer 122 is located at 1 upper surface of substrate is
Step S4 and Fig. 7 in please referring to Fig.2, then carry out step S4, in first gold medal under the conditions of second temperature
Belong to depositing second metal layer 123 on layer 122, the second metal layer 123 fills up the contact hole 11 and forming first gold medal
Belong to the gap after layer 122, deposit material identical of the material of the second metal layer 123 with depositing the first metal layer 122,
The second temperature is more than first temperature.In the present embodiment, H is also used in this step2And WF6Deposition forms tungsten layer.Because
The first metal layer 122 has been laid a solid foundation, therefore the technological temperature in this step can be raised to accelerate metal fill velocity.And
In view of H under the technological temperature of higher2And WF6Reaction it is more violent, H2And WF6Flow set may be slightly larger than the step S3
In flow.More specifically, in the step S4 of the present embodiment, using chemical vapor deposition method, at 390 DEG C~400 DEG C
Technological temperature under, pass through WF6And H2Reaction, by the sedimentation time of 120s~150s in the upper of the first metal layer 122
Surface forms thicknessThe second metal layer 123.Likewise, also deposited in this step using the cycle
Mode form the second metal layer 123.Certainly, the deposit thickness of the second metal layer 123 need to be according to the contact hole
11 The concrete specification and set, but not influence productivity, most of filling of the contact hole 11 be all by this step come
Complete.Under the conditions of this, because sedimentation time is longer and depositing temperature is higher, therefore the second metal layer 123 deposited is positioned at described
The ratio between the thickness h 2 of hole side wall 11a of the thickness d 2 of the bottom hole portion 11b of contact hole 11 with being located at the contact hole 11 is more than 1.Also
It should be noted that although the total thickness for the metal layer that deposition is formed is more than on the substrate 1 in the contact hole 11
The thickness of the metal layer of formation is deposited on surface, but remains difficult to avoid the production of pit 124 completely in the top of the contact hole 11
It is raw, it can only reduce as far as possible.In addition, although the resistivity that the second metal layer 123 of formation is deposited in this step is typically larger than
The resistivity of the first metal layer 122 of formation is deposited in the step S3, but uses and is made under the preparation method of the present embodiment
Bonding between standby each film layer is more close, and does not have hole, therefore the contact hole 11 of final filling completion is whole
Body resistivity declines, be avoided that because hole and high resistance cause the open circuit of device, loose contact even component failure the problems such as, from
And device performance and production yield are effectively improved, reduce production cost.
It should be noted that the nucleating layer 121 formed in the present embodiment, the first metal layer 122 and described
Two metal layers 123 be tungsten film layer to be finally completed the filling of the contact hole 11, but be practically used for filling the contact hole
11 metal can also have other selections, such as aluminium and copper, or the mixing of various metals, such as 121 He of the nucleating layer
The material of the first metal layer 122 can be different, but deposit the first metal layer 122 and the second metal layer 123
Material is preferably tried one's best unanimously, and the setting of the specific process conditions deposited every time needs to set according to the characteristic of the material used.This
Outside, the formation thickness described in the step isThe second metal layer 123 refer to be formed described second
The thickness that metal layer 123 is located at the part of the upper surface of the substrate 1 is
The step S2, step S3 and step S4 are because be related to different process conditions, to avoid frequent technique tune
The whole interference made troubles and avoid each operation stage, usually preferably carries out in different reaction pedestals.
After the step S4 is completed, the step that chemical mechanical grinding is carried out to obtained body structure surface is also typically included
Suddenly, the degree specifically ground is different and different according to required obtained structure.For example if being only contact hole 11 needed for filling, lead to
Cross other redundant structures that chemical mechanical grinding removes the upper surface of the substrate 1, including the bonding barrier layer 13, it is described into
Stratum nucleare 121, the first metal layer 122 and the second metal layer 123, final obtained structure are as shown in Figure 8；If it need to be made
The structure with the contact hole 11 and conducting wire, then the out-of-flatness of 1 upper surface of substrate is removed by chemical mechanical grinding
Part, especially with the part of pit 124, final obtained structure is as shown in Figure 9.
The preparation method of the semiconductor interconnection structure of the present embodiment is especially suitable for the contact hole for filling high-aspect-ratio, such as deeply
The wide contact hole than more than 2, because the contact hole filling that preparation method through this embodiment is completed can effectively remove hole, drops
The resistance of low contact hole to avoid because hole and high resistance cause the open circuit of device, loose contact even component failure the problems such as,
So as to effectively improve device performance and production yield, production cost is reduced.Although what is discussed in the present embodiment is all contact hole
It is metal filled, but the method is also fully applicable for the filling of through hole (via) and the system of other similar semiconductor interconnection structures
It is standby.
The preparation method of the semiconductor interconnection structure of the present embodiment can be also used for simple metal film deposition, specifically,
Such as the deposition of tungsten film.The metal film prepared using this method has preferable uniformity and relatively low resistance, and because only by portion
Point deposition process, which is placed under the process conditions of relative low temperature, to be completed, therefore will not cause the extension of whole process time, will not be caused
The decline of productivity.
Embodiment two
As shown in figure 8, the present invention also provides a kind of semiconductor interconnection structure 2, the semiconductor interconnection structure 2 includes substrate
1, nucleating layer 121, the first metal layer 122 and second metal layer 123.Specifically, formed with least one contact in the substrate 1
Hole 11, the contact hole 11 have hole side wall 11b and bottom hole portion 11a；The nucleating layer 121 is covered in the institute of the contact hole 11
State hole side wall 11b and the bottom hole portion 11a；The first metal layer 122 is located in the contact hole 11 and covers positioned at described
The nucleating layer 121 in contact hole 11；The first metal layer 122 includes the first position positioned at the bottom hole portion 11a
122a and positioned at the hole side wall 11b and the second position 122b of the connection first position 122a, the first position
122a vertically to thickness d 1 and the second position 122b be more than or equal to 1 in both ratios of horizontal direction thickness h 1, and
And the first position 122a vertically to thickness d 1 be less than or equal to the contact hole 11 the vertical half to depth；
The second metal layer 123 is located in the contact hole 11 and covers the first metal layer in the contact hole 11
122, the second metal layer 122 fills up gap of the contact hole 11 after the first metal layer 122 is formed and described the
The material of two metal layers 123 is identical with the material of the first metal layer 122.More specifically, the depth-to-width ratio of the contact hole 11
More than 2 and the nucleating layer 121, the first metal layer 122 and the second metal layer 123 are tungsten layer.Certainly, it is necessary to say
Bright, the schematic diagram in the present embodiment is only the position relationship of signal each several part rather than the considered critical to each structure.
As an example, 1 surface of substrate is also formed with bonding barrier layer 13, the bonding barrier layer 13 connects positioned at described
In contact hole 11 and be formed between the nucleating layer 121 and the substrate 1 using as the nucleating layer 121 and the substrate 1 it
Between engagement liner and separation layer and play the protection substrate 1, the bonding barrier layer 13 generally includes to be sequentially depositing
Ti layers and TiN layer.
There is preferable bonding between each film layer structure in semiconductor interconnection structure in the present embodiment and filled with gold
There is no hole in the contact hole of category, resistivity is relatively low so that be avoided that because hole and high resistance cause device open circuit, contact not
The problems such as good or even component failure, so as to effectively improve device performance and production yield, reduce production cost.
Embodiment three
As shown in figure 9, the present invention also provides another semiconductor interconnection structure 3, the semiconductor interconnection structure 3 includes：
Substrate 1, nucleating layer 121, the first metal layer 122 and second metal layer 123.Specifically, the contact hole 11 has hole side wall 11b
With bottom hole portion 11a；The nucleating layer 121 is covered in the upper surface of the substrate 1 and the hole side wall 11b of the contact hole 11
With the bottom hole portion 11a；The first metal layer 122 is located in top and the contact hole 11 of the substrate 1, and is located at institute
State the upper surface of nucleating layer 121；Wherein, the first metal layer 122 includes the first position 122a positioned at the bottom hole portion 11a
And the second position 122b positioned at the hole side wall 11b and the connection first position 122a, the first position 122a exist
Vertically to thickness d 1 and the second position 122b be more than or equal to 1 in both ratios of horizontal direction thickness h 1, and described the
The thickness of one metal layer 122 is more than the thickness of the nucleating layer 121；The second metal layer 123 is located on the substrate 1 and institute
State in contact hole and cover the first metal layer in the contact hole, and two metal layer is also covered positioned at institute
The first metal layer 122 of the top of substrate 1 is stated, the second metal layer 123 fills up the contact hole 11 described in formation
Gap after the first metal layer 122；The material of the second metal layer 123 it is identical with the material of the first metal layer 122 and
The thickness of the second metal layer 123 is more than the thickness of the first metal layer 122.More specifically, the depth of the contact hole 11
It is wide than more than 2 and the nucleating layer 121, the first metal layer 122 and the second metal layer 123 be tungsten layer.Equally need
It is noted that the schematic diagram in the present embodiment only for the position relationship of signal each several part rather than limits the stringent of each structure
It is fixed.
As an example, 1 surface of substrate be also formed with bonding barrier layer 13, it is described bonding barrier layer 13 positioned at it is described into
Between stratum nucleare 121 and the substrate 1 using as the engagement liner between the nucleating layer 121 and the substrate 1 and separation layer and
Play the protection substrate 1, the bonding barrier layer 13 generally includes Ti layers and the TiN layer being sequentially depositing.The present embodiment
In semiconductor interconnection structure in each film layer structure between have in preferable bonding and contact hole filled with metal and do not have
Hole, resistivity is relatively low, so as to be avoided that because hole and high resistance cause open circuit, loose contact even component failure etc. of device
Problem, and film surface has good uniformity, and is conducive to being smoothed out for the techniques such as follow-up photoetching, so as to effectively improve device
Performance and production yield, reduce production cost.
In conclusion the preparation method of the semiconductor interconnection structure of the present invention, including step：1) substrate is provided, it is described
Metal filled contact hole need to be carried out formed with least one in substrate, the contact hole has hole side wall and bottom hole portion；2) in
Metal nucleation layer is formed on the hole side wall and the bottom hole portion of the upper surface of the substrate and the contact hole；3) first
In depositing the first metal layer on the nucleating layer under temperature conditionss；Wherein, the first metal layer covers the nucleating layer, described
The first metal layer including the first position positioned at the bottom hole portion and positioned at the hole side wall and connects the first position
Second position, the first position vertically to thickness and the second position be more than in both ratios of horizontal direction thickness
Equal to 1, and the first position vertically to thickness be less than or equal to the contact hole the vertical half to depth；
4) under the conditions of second temperature the contact is filled up in depositing second metal layer on the first metal layer, the second metal layer
Gap of the hole after the first metal layer is formed, deposits the material of the second metal layer with depositing the first metal layer
Material identical, the second temperature are more than first temperature.The preparation method system of semiconductor interconnection structure using the present invention
Bonding between each film layer of standby semiconductor interconnection structure is more close, and does not have hole, therefore final filling completion
The overall resistivity of the contact hole declines, and is avoided that because hole and high resistance cause open circuit, the loose contact even device of device
The problems such as part fails, so as to effectively improve device performance and production yield, reduces production cost.Semiconductor interconnection in the present invention
There is no hole in the contact hole filled in structure and resistivity is relatively low, film layer is more uniform, so as to be avoided that because of hole and height electricity
Caused by resistance the problems such as device open circuit, loose contact or even component failure, the device of semiconductor interconnection structure using the present invention
Performance significant increase.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (17)
1. a kind of preparation method of semiconductor interconnection structure, it is characterised in that include the following steps：
1) substrate is provided, the substrate is interior need to carry out metal filled contact hole, the contact hole tool formed with least one
There are hole side wall and bottom hole portion；
2) in formation metal nucleation layer on the hole side wall and the bottom hole portion of the upper surface of the substrate and the contact hole；
3) under the first temperature conditionss in depositing the first metal layer on the nucleating layer；Wherein, the first metal layer covering institute
Nucleating layer is stated, the first metal layer is included positioned at the first position in the bottom hole portion and positioned at the hole side wall and connection institute
State the second position of first position, the first position vertically to thickness and the second position in horizontal direction thickness
Both ratios are more than or equal to 1, and the first position vertically to thickness be less than or equal to the vertical to depth of the contact hole
The half of degree；
4) in depositing second metal layer on the first metal layer under the conditions of second temperature, the second metal layer is filled up described
Gap of the contact hole after the first metal layer is formed, deposits the material of the second metal layer with depositing first metal
The material identical of layer, the second temperature are more than first temperature.
2. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：In the step 1), institute
The depth-to-width ratio for stating contact hole is more than 2.
3. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：In the step 2), adopt
The nucleating layer is formed with chemical vapor deposition method, the reactant for forming the nucleating layer includes tungsten hexafluoride (WF6)
With silane (SiH4)；In the step 3), the first metal layer is deposited using chemical vapor deposition method, it is described for being formed
The reactant of the first metal layer includes tungsten hexafluoride (WF6) and hydrogen (H2)；In the step 4), using chemical vapor deposition work
Skill deposits the second metal layer, and the reactant for forming the second metal layer includes tungsten hexafluoride (WF6) and hydrogen
(H2)。
4. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：In the step 2), shape
Into the nucleating layer temperature between 250 DEG C~300 DEG C, the sedimentation time of the nucleating layer is between 40s~50s, the nucleation
Layer thickness between
5. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：In the step 3), institute
The sedimentation time of the first metal layer is stated between 80s~90s, the thickness of the first metal layer betweenThe step
It is rapid 4) in, the sedimentation time of the second metal layer between 120s~150s, the thickness of the second metal layer between
6. the preparation method of semiconductor interconnection structure according to claim 5, it is characterised in that：In the step 3), institute
The first temperature is stated between 250 DEG C~300 DEG C；In the step 4), the second temperature is between 390 DEG C~400 DEG C.
7. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：Before the step 2) also
Including the step of：Barrier layer is binded in being formed on the substrate surface and in the contact hole, in the step 2), the nucleation
Layer is formed on the bonding barrier layer.
8. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：After the step 4) also
Including the step of：The structure obtained to the step 4) carries out chemical mechanical grinding, to remove described in the substrate top surface
Nucleating layer, the first metal layer and the second metal layer.
9. the preparation method of semiconductor interconnection structure according to claim 1, it is characterised in that：Step 3) the deposition
The resistivity of the first metal layer is less than the resistivity of the second metal layer of the step 4) deposition, and the step 4)
The contact hole for filling completion afterwards does not have hole.
10. a kind of semiconductor interconnection structure, it is characterised in that the semiconductor interconnection structure includes：
Substrate, the substrate is interior to have hole side wall and bottom hole portion formed with least one contact hole, the contact hole；
Nucleating layer, is covered in the hole side wall of the contact hole and the bottom hole portion；
The first metal layer, in the contact hole and covering is located at the nucleating layer in the contact hole；First gold medal
Category layer including the first position positioned at the bottom hole portion and positioned at the hole side wall and connects second of the first position
Position, the first position vertically to thickness and the second position be more than or equal to 1 in both ratios of horizontal direction thickness,
And the first position vertically to thickness be less than or equal to the contact hole the vertical half to depth；And
Second metal layer, in the contact hole and covers the first metal layer in the contact hole, and described the
Two metal layers fill up gap of the contact hole after the first metal layer is formed；The material of the second metal layer with it is described
The material of the first metal layer is identical.
11. semiconductor interconnection structure according to claim 10, it is characterised in that：The depth-to-width ratio of the contact hole is more than 2.
12. semiconductor interconnection structure according to claim 10, it is characterised in that：The second metal layer and described first
The phase same material of metal layer includes tungsten.
13. semiconductor interconnection structure according to claim 10, it is characterised in that：The semiconductor interconnection structure further includes
Barrier layer is binded, the bonding barrier layer is located in the contact hole and is formed between the nucleating layer and the substrate, with
As the engagement liner between the nucleating layer and the substrate and play the protection substrate.
14. a kind of semiconductor interconnection structure, it is characterised in that the semiconductor interconnection structure includes：
Substrate, the substrate is interior to have hole side wall and bottom hole portion formed with least one contact hole, the contact hole；
Nucleating layer, is covered in the upper surface of the substrate and the hole side wall of the contact hole and the bottom hole portion；
The first metal layer, in the top of the substrate and the contact hole, and positioned at the upper surface of the nucleating layer；Its
In, the first metal layer is included positioned at the first position in the bottom hole portion and positioned at the hole side wall and connection described first
The second position at position, the first position vertically to thickness and the second position horizontal direction thickness both ratio
Value is more than or equal to 1, and the thickness of the first metal layer is more than the thickness of the nucleating layer；And
Second metal layer, on the substrate and in the contact hole and covering is located at first gold medal in the contact hole
Belong to layer, and two metal layer also covers the first metal layer positioned at the top of the substrate, the second metal layer
Fill up gap of the contact hole after the first metal layer is formed；The material of the second metal layer and first metal
The material of layer is identical and the thickness of the second metal layer is more than the thickness of the first metal layer.
15. semiconductor interconnection structure according to claim 14, it is characterised in that：The depth-to-width ratio of the contact hole is more than 2.
16. semiconductor interconnection structure according to claim 14, it is characterised in that：The second metal layer and described first
The phase same material of metal layer includes tungsten.
17. semiconductor interconnection structure according to claim 14, it is characterised in that：The semiconductor interconnection structure further includes
Bind barrier layer, it is described bonding barrier layer between the nucleating layer and the substrate, using as the nucleating layer with it is described
Engagement liner and separation layer between substrate and play the protection substrate.
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