CN107945759B

CN107945759B - Shifting register unit, grid driving circuit and display device

Info

Publication number: CN107945759B
Application number: CN201810002024.9A
Authority: CN
Inventors: 古宏刚; 陈俊生; 邵贤杰; 薛伟
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2018-01-02
Filing date: 2018-01-02
Publication date: 2021-01-22
Anticipated expiration: 2038-01-02
Also published as: CN107945759A

Abstract

The invention relates to a shift register unit, a grid driving circuit and a display device. The unit includes: the cascade input module is used for providing a cascade signal received by the cascade signal input end to the pull-up node; the driving output module is used for providing the clock signal received by the clock signal input end to the driving signal output end; the driving reset module is used for providing a third voltage signal received by a third power supply end to the driving signal output end; the cascade reset module is used for providing a second voltage signal received by the second power supply end to the pull-up node; the pull-down module is used for providing a first voltage signal or a second voltage signal received by a first power supply end to a pull-down node; the cascade output module is used for providing the third voltage signal or the clock signal to the cascade signal output end. The embodiment can meet the requirements of cascade connection and driving on the driving signal in a low-temperature environment. In addition, in this embodiment, the voltage signals of the second power source terminal and the third power source terminal can be adjusted, so as to improve the adaptability of the unit.

Description

Shifting register unit, grid driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a grid driving circuit and a display device.

Background

Currently, the output terminal of each stage of shift register unit in a basic Driver circuit (Gate Driver on Array, GOA) of a Thin Film Transistor Liquid Crystal Display (TFT-LCD) Array has the following connections: connecting one to the grid of the transistor in the pixel unit in the row to control the data line to write pixel voltage into the pixel unit; the second connection is connected with the input end of the next-stage shift register unit so as to trigger the next-stage shift register unit to generate a driving signal; and the third connection is connected with the reset end of the upper-stage shift register unit so as to trigger the upper-stage shift register unit to recover to the initial state. However, in a low temperature state, the driving capability of each stage of the shift register unit is limited due to the reduced working capability of each TFT, and the driving signal output by the shift register unit is not enough to simultaneously implement the three connection corresponding functions, thereby affecting the normal display function of the display.

Disclosure of Invention

The invention provides a shift register unit, a gate driving circuit and a display device, which are used for solving the defects in the related art.

According to a first aspect of embodiments of the present invention, there is provided a shift register unit, the unit comprising: the device comprises a cascade input module, a cascade output module, a cascade reset module, a drive output module, a drive reset module and a pull-down module;

the cascade input module is connected with a cascade signal input end and a pull-up node and used for responding to a cascade signal received by the cascade signal input end and providing the cascade signal to the pull-up node; the pull-up node is a connection point between the cascade input module and the drive output module;

the driving output module is connected with the pull-up node, the clock signal input end and the driving signal output end and used for responding to a voltage signal of the pull-up node and providing a clock signal received by the clock signal input end to the driving signal output end;

the driving reset module is connected with a third power supply end, a driving signal reset end and the driving signal output end, and is used for responding to the voltage signal received by the driving signal reset end and providing the third voltage signal received by the third power supply end to the driving signal output end;

the cascade reset module is connected with a cascade signal reset terminal, the pull-up node and a second power terminal, and is used for responding to the voltage signal received by the cascade signal reset terminal, providing a second voltage signal received by the second power terminal to the pull-up node, so that the cascade output module outputs the second voltage signal in response to the voltage signal of the pull-up node;

the pull-down module is connected with the pull-up node, the first power end, the second power end and the pull-down node, and is used for responding to a voltage signal of the pull-up node and providing a first voltage signal received by the first power end or a second voltage signal to the pull-down node; the pull-down node is a connection point between the pull-down module and the cascade output module;

the cascade output module is electrically connected to the pull-up node, the pull-down node, the clock signal input end, the second power end and the cascade signal output end, and is configured to respond to the voltage signals of the pull-up node and the pull-down node and provide the second voltage signal or the clock signal to the cascade signal output end.

Optionally, the cascade input module comprises a first transistor; and the control electrode and the first electrode of the first transistor are connected to the cascade signal input end, and the second electrode of the second transistor is connected with the pull-up node.

Optionally, the driving output module comprises a second transistor and a capacitor; the capacitor is connected between the pull-up node and the drive signal output end in series; and the control electrode of the second transistor is connected with the pull-up node, the first electrode of the second transistor is connected with the clock signal input end, and the second electrode of the second transistor is connected with the driving signal output end.

Optionally, the driving reset module comprises a third transistor; and a control electrode of the third transistor is connected with the drive signal reset end, a first electrode of the third transistor is connected with the drive signal output end, and a second electrode of the third transistor is connected with the third power supply end.

Optionally the cascaded reset module comprises a fourth transistor; and a control electrode of the fourth transistor is connected with the cascade signal reset end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the second power supply end.

Optionally, the cascade output module comprises a fifth transistor and a sixth transistor;

a control electrode of the fifth transistor is connected with the pull-up node, a first electrode of the fifth transistor is connected with the clock signal input end, and a second electrode of the fifth transistor is connected with the cascade signal output end;

and a control electrode of the sixth transistor is connected with the pull-down node, a first electrode of the sixth transistor is connected with the cascade signal output end, and a second electrode of the sixth transistor is connected with the second power supply end.

Optionally, the pull-down module comprises a seventh transistor and an eighth transistor;

a control electrode and a first electrode of the seventh transistor are connected to the first power supply end, and a second electrode of the seventh transistor is connected to the pull-down node;

and a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the pull-down node, and a second electrode of the eighth transistor is connected with the second power supply end.

Optionally, the unit further includes a pull-down enhancing module, connected to the cascade signal input terminal, the second power terminal, and the pull-down node, for providing the second voltage signal to the pull-down node in response to the cascade signal.

Optionally, the pull-down enhancement module comprises a ninth transistor; and a control electrode of the ninth transistor is connected with the cascade signal input end, a first electrode of the ninth transistor is connected with the pull-down node, and a second electrode of the ninth transistor is connected with the second power supply end.

Optionally, the unit further comprises a cascade reset enhancement module; the cascade reset enhancement module is connected with the pull-up node, the pull-down node and the second power end, and is used for responding to a voltage signal of the pull-down node and providing the second voltage signal to the pull-up node.

Optionally, the cascaded reset boost module comprises a tenth transistor; a control electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the upper node, and a second electrode of the tenth transistor is connected to the second power supply terminal.

Optionally, the unit further comprises a drive reset enhancing module; the driving reset enhancement module is connected to the pull-down node, the driving signal output end and the third power end, and is configured to respond to a voltage signal of the pull-down node and provide the third voltage signal to the driving signal output end.

Optionally, the driving reset boost module comprises an eleventh transistor; a control electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the driving signal output end, and a second electrode of the eleventh transistor is connected to the third power supply end.

Optionally, the unit further comprises a noise removal module; the de-noising module is connected with the pull-up node, the second power end and the de-noising signal input end, and is used for responding to the de-noising signal received by the de-noising signal input end and providing the second voltage signal for the pull-up node.

Optionally, the denoising module comprises a twelfth transistor; and a control electrode of the twelfth transistor is connected with the denoising signal input end, a first electrode of the twelfth transistor is connected with the pull-up node, and a second electrode of the twelfth transistor is connected with the second power supply end.

According to a second aspect of the embodiments of the present invention, there is provided a gate driving circuit, comprising a plurality of cascaded shift register units; each shift register cell is a shift register cell as described in the first aspect;

the cascade signal input end of the first-stage shift register unit is connected with the initial signal end of the gate drive circuit, the cascade signal reset end of the first-stage shift register unit is connected with the cascade signal output end of the second-stage shift register unit, and the drive signal reset end of the first-stage shift register unit is connected with the drive signal output end of the second-stage shift register unit; the cascade signal input end of the last stage of shift register unit is connected with the cascade signal output end of the previous stage of shift register unit, and the drive signal reset end of the last stage of shift register unit is connected with the initial signal end;

except the first stage and the last stage of shift register units, the cascade signal input ends of the other shift register units at all stages are connected with the cascade signal output end of the shift register unit at one stage, the cascade signal reset end is connected with the cascade signal output end of the shift register unit at the next stage, and the drive signal reset end is connected with the drive signal output end of the shift register unit at the next stage.

According to a third aspect of the embodiments of the present invention, there is provided a display device including the gate driving circuit according to the second aspect.

According to the embodiments, the cascade part and the driving part are separated, the cascade input module, the cascade output module and the cascade reset module complete cascade driving and resetting, and the driving output module and the driving reset module complete output driving and resetting, so that the requirements of cascade and driving on driving signals in a low-temperature environment can be met, and the display can normally work. In addition, in this embodiment, the voltage signals received by the second power supply terminal and the third power supply terminal can be respectively adjusted according to the drift condition of the threshold voltage of the TFT in the low-temperature environment, so as to adjust the voltage signal output by the cascade output module or the driving output module, so that the voltage signal meets the requirements of cascade connection or driving, the adaptability of the shift register unit to the low-temperature environment is improved, and the reliability of the display operation is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating a shift register cell according to an embodiment of the present invention;

FIG. 3 is a timing diagram illustrating operation of the shift register unit of the embodiment of FIG. 2;

FIG. 4 is a schematic diagram of another shift register unit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a shift register unit according to another embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating a structure of another shift register unit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a structure of another shift register unit according to an embodiment of the present invention;

FIG. 8 is a circuit diagram illustrating yet another shift register cell according to an embodiment of the present invention;

fig. 9 is a connection diagram of a gate driving circuit according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention. Referring to fig. 1, an nth stage shift register unit is taken as an example for explanation, and the shift register unit includes: the cascade input module 100, the driving output module 200, the driving reset module 300, the cascade reset module 400, the cascade output module 500 and the pull-down module 600;

the cascade input module 100 is connected to the cascade signal input end Oc (n-1) and the pull-up node PU, and is configured to provide the cascade signal to the pull-up node PU in response to the cascade signal received by the cascade signal input end Oc (n-1); wherein, the pull-up node PU is a connection point between the cascade input module 100 and the driving output module 200;

the driving output module 200 is connected to the pull-up node PU, the clock signal input terminal CLK and the driving signal output terminal og (n), and is configured to provide the clock signal received by the clock signal input terminal CLK to the driving signal output terminal og (n) in response to the voltage signal of the pull-up node PU;

the driving reset module 300 is connected to the third power source terminal VGL, the driving signal reset terminal OG (n +1), and the driving signal output terminal OG (n), and is configured to provide the third voltage signal received by the third power source terminal VGL to the driving signal output terminal OG (n) in response to the voltage signal received by the driving signal reset terminal OG (n + 1);

the cascade reset module 400 is connected to the cascade signal reset terminal Oc (n +1), the pull-up node PU and the second power source terminal LVGL, and configured to provide the second voltage signal received by the second power source terminal LVGL to the pull-up node PU in response to the voltage signal received by the cascade signal reset terminal Oc (n +1), so that the cascade output module 500 outputs the second voltage signal in response to the voltage signal of the pull-up node PU;

the cascade output module 500 is electrically connected to the pull-up node PU, the pull-down node PD, the clock signal input terminal CLK, the second power terminal VGL, and the cascade signal output terminal oc (n), and is configured to provide a third voltage signal or a clock signal to the cascade signal output terminal oc (n) in response to voltage signals of the pull-up node PU and the pull-down node PD;

the pull-down module 600 is connected to the pull-down node PU, the first power terminal VDD, the second power terminal VGL and the pull-down node PD, and configured to provide the first voltage signal or the second voltage signal received by the first power terminal VDD to the pull-down node PU in response to the voltage signal of the pull-up node PU; the pull-down node PU is a connection point between the pull-down module 600 and the cascade output module 500.

Therefore, in the embodiment, the functions of the cascade part and the driving part in the shift register unit are separated, the cascade input module, the cascade output module and the cascade reset module complete the cascade driving and resetting of the shift register unit, and the drive output module and the drive reset module complete the output driving and resetting of the shift register unit, so that the requirements of the cascade part and the driving part of the shift register unit on the driving signals in a low-temperature environment can be met, and the display can work normally. In addition, in this embodiment, the voltage signals received by the second power supply terminal and the third power supply terminal can be respectively adjusted according to the drift condition of the threshold voltage of the TFT in the shift register unit in the low-temperature environment, so as to adjust the voltage signal output by the cascade output module or the driving output module, so that the voltage signal meets the requirements of cascade connection or driving, the adaptability of the shift register unit to the low-temperature environment is improved, and the reliability of the display operation is improved.

On the basis of the shift register unit shown in fig. 1, an embodiment of the present invention provides a circuit structure of a shift register unit, and fig. 2 is a circuit diagram of a shift register unit according to an embodiment of the present invention. It should be noted that the shift register unit shown in fig. 2 is implemented by using a transistor, and the transistor may be formed by one or more of an N-Metal-Oxide-Semiconductor (NMOS), a P-Metal-Oxide-Semiconductor (PMOS), or a bipolar transistor. For simplicity, the transistors in the present invention are all made of NMOS transistors, and the turn-on level of the NMOS transistor may be a high level, such as a first voltage signal; the turn-off level of the NMOS transistor may be a low level, such as the second voltage signal or the third voltage signal. See fig. 2, where:

in this embodiment, the cascade input module 100 comprises a first transistor M1, a control electrode and a first electrode of the first transistor M1 are connected in parallel to the cascade signal input end Oc (n-1), and a second electrode is connected to the pull-up node PU. Referring to fig. 2, when the first transistor M1 is an NMOS transistor, its source and drain are both connected to the cascade signal input terminal Oc (n-1), and the source is connected to the pull-up node PU, i.e., the first transistor M1 constitutes a diode connection. When the cascade signal received by the cascade signal input terminal Oc (n-1) is the first voltage signal, the first transistor M1 is turned on, so as to turn on the cascade signal input terminal Oc (n-1) and the pull-up node PU, thereby achieving the effect of providing the first voltage signal to the pull-up node PU. When the cascade signal received at the cascade signal input terminal Oc (n-1) is the second voltage signal, the first transistor M1 is turned off, so as to disconnect the cascade signal input terminal Oc (n-1) from the pull-up node PU, and when the source of the first transistor M1 has no voltage signal output, which can be understood as the effect of providing the second voltage signal to the pull-up node PU. It can be seen that the cascade input module 100 in this embodiment can respond to the cascade signal received by the cascade signal input terminal Oc (n-1) and provide the cascade signal to the pull-up node PU.

In this embodiment, the driving output module 200 includes a second transistor M2 and a capacitor C. The capacitor C is connected in series between the pull-up node PU and the driving signal output terminal og (n). The control electrode of the second transistor M2 is connected to the pull-up node PU, the first electrode is connected to the clock signal input terminal CLK, and the second electrode is connected to the driving signal output terminal og (n). With reference to fig. 2, when the second transistor M2 is an NMOS transistor, the gate of the NMOS transistor is connected to the pull-up node PU, the drain is connected to the clock signal input terminal CLK, the source is connected to the driving signal output terminal og (n), and the capacitor C is connected in series between the clock signal input terminal CLK and the driving signal output terminal og (n). When the pull-up node is the first voltage signal, the second transistor M2 turns on and turns on the clock signal input terminal CLK and the driving signal output terminal og (n), and the clock signal input terminal CLK can provide the received clock signal to the driving signal output terminal og (n). While capacitor C can maintain the voltage difference between the pull-up node and the driving signal output terminal og (n). It can be understood that when the clock signal is the first voltage signal, the voltage at the left end of the capacitor C (i.e. the end connected to the pull-up node PU) becomes higher due to the bootstrap effect of the capacitor C, so that the second transistor M2 is turned on to a greater extent. When the pull-up node is the second voltage signal, the second transistor M2 is turned off, and no signal is output from the source of the second transistor M2 (which can be understood as the second voltage signal in the clock signal).

It can be seen that the driving output module 200 in this embodiment can provide the clock signal of the clock signal input terminal CLK to the driving output module in response to the voltage signal of the pull-up node PU.

In this embodiment, the driving reset module 300 may include a third transistor M3. A control electrode of the third transistor M3 is connected to the driving signal reset terminal OG (n +1), a first electrode is connected to the driving signal output terminal OG (n), and a second electrode is connected to the third power source terminal VGL. With reference to fig. 2, when the third transistor M3 is an NMOS transistor, the gate of the third transistor M3 is connected to the driving signal reset terminal OG (n +1), the drain is connected to the driving signal output terminal OG (n), and the source is connected to the third power source terminal VGL. When the driving signal reset terminal OG (n +1) receives the first voltage signal, the third transistor M3 turns on and turns on the third power terminal VGL and the driving signal output terminal OG (n), and at this time, the driving reset module 300 can provide the third voltage signal to the driving signal output terminal OG (n). When the driving signal reset terminal OG (n +1) receives the second voltage signal, the third transistor M3 is turned off and disconnects the third power terminal VGL and the driving signal output terminal OG (n), and the drain of the third transistor M3 has no output.

As can be seen, the driving reset module 300 can provide a third voltage signal to the driving signal terminal OG (n) in response to the voltage signal received by the driving signal reset terminal OG (n + 1).

In this embodiment, the cascaded reset module 400 may include a fourth transistor M4. The fourth transistor M4 has a control electrode connected to the cascade signal reset terminal Oc (n +1), a first electrode connected to the pull-up node PU, and a second electrode connected to the second power source terminal LVGL. With reference to fig. 2, when the fourth transistor M4 is an NMOS transistor, the gate of the fourth transistor M4 is connected to the cascade signal reset terminal Oc (n +1), the drain is connected to the pull-up node PU, and the source is connected to the second power source terminal LVGL. When the cascode signal reset terminal Oc (n +1) receives the first voltage signal, the fourth transistor M4 turns on and turns on the cascode signal reset terminal Oc (n +1) and the second power terminal LVGL, and the cascode reset module 400 may provide the second voltage signal to the pull-up node PU. When the cascade signal reset terminal Oc (n +1) receives the second voltage signal, the fourth transistor M4 turns off and disconnects the cascade signal reset terminal Oc (n +1) and the second power source terminal LVGL, and the drain of the fourth transistor M4 does not output a signal.

As can be seen, the cascade reset module 400 may provide the second voltage signal received by the second power source terminal LVGL to the pull-up node in response to the voltage signal received by the cascade signal reset terminal Oc (n + 1).

In the present embodiment, the pull-down module 600 includes a seventh transistor M7 and an eighth transistor M8. The control electrode and the first electrode of the seventh transistor M7 are simultaneously connected to the first power terminal VDD, and the second electrode is connected to the pull-down node PD. A control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode thereof is connected to the pull-up node PD, and a second electrode thereof is connected to the second power source terminal LVGL. With continued reference to fig. 2, when the first voltage signal is present at the pull-up node PU, the eighth transistor M8 turns on and turns on the second power terminal LVGL and the pull-down node PD, which is the second voltage signal at the pull-down node PD. When the second voltage signal is at the pull-up node PU, the eighth transistor M8 turns off and disconnects the second power source terminal LVGL and the pull-down node PD, and the seventh transistor M7 pulls up the pull-down node PD to the first voltage signal.

In this embodiment, it can be seen that the pull-down module 600 can provide the first voltage signal received by the first power terminal VDD or the second voltage signal received by the second power terminal LVGL to the pull-down node PD in response to the voltage signal of the pull-up node PU.

In the present embodiment, the cascade output module 500 includes a fifth transistor M5 and a sixth transistor M6. A control electrode of the fifth transistor M5 is connected to the pull-up node PU, a first electrode is connected to the clock signal input terminal CLK, and a second electrode is connected to the cascade signal output terminal oc (n); a control electrode of the sixth transistor M6 is connected to the pull-down node PD, a first electrode is connected to the cascade signal output terminal oc (n), and a second electrode is connected to the second power source terminal LVGL. With continued reference to fig. 2, when the fifth transistor M5 and the sixth transistor M6 are NMOS transistors, the gate of the fifth transistor M5 is connected to the pull-up node PU, and the drain is connected to the clock signal input terminal CLK; the sixth transistor M6 has a gate connected to the pull-down node PD, a drain connected to the cascade signal output terminal oc (n), and a source connected to the second power source terminal LVGL. When the pull-up node PU is the first voltage signal and the pull-down node PD is the second voltage signal, the fifth transistor M5 is turned on, and the sixth transistor M6 is turned off, at this time, the cascade output module 500 may provide the clock signal to the cascade signal output terminal oc (n). When the pull-up node PU is the second voltage signal and the pull-down node PD is the first voltage signal, the fifth transistor M5 is turned off, and the sixth transistor M6 is turned on, at this time, the cascade output module 500 can provide the second voltage signal to the cascade signal output terminal oc (n).

It can be seen that the cascade output module 500 can provide a second voltage signal or clock signal to the cascade signal output terminal oc (n) in response to the voltage signals of the pull-up node PU and the pull-down node PD.

FIG. 3 is a timing diagram illustrating operation of the shift register unit of the embodiment of FIG. 2. Based on the timing, referring to fig. 2 and 3, the operation process of the shift register unit includes:

in the stage 1, the cascade signal input end Oc (n-1) receives a first voltage signal, and the first transistor M1 is turned on; the cascade signal reset terminal Oc (n +1) receives the second voltage signal, and the fourth transistor M4 is turned off; the driving signal reset terminal OG (n +1) receives the third voltage signal, and the third transistor M3 is turned off. Upon receiving the first voltage signal, the first transistor M1 is turned on, and the upper node PU is the first voltage signal. When the upper node PU is the first voltage signal, the second transistor M2 and the fifth transistor M5 are turned on, and the clock signal input terminal CLK receives the second voltage signal, so the driving signal output terminal og (n) outputs the second voltage signal. Since the upper node PU is the first voltage signal, the eighth transistor M8 is turned on, the pull-down node PD is pulled down to the second voltage signal, and the sixth transistor M6 is turned off, so that the cascade signal output terminal oc (n) can output the second voltage signal by adjusting the width-to-length ratio of the fifth transistor M5 to the sixth transistor M6.

Meanwhile, the capacitor C holds the first voltage signal.

In stage 2, the cascade signal input end Oc (n-1) receives the second voltage signal, and the first transistor M1 is turned off; the cascade signal reset terminal Oc (n +1) receives the second voltage signal, and the fourth transistor M4 is turned off; the driving signal reset terminal OG (n +1) receives the third voltage signal, and the third transistor M3 is turned off. Due to the holding function of the capacitor C, the first voltage signal is provided at the upper node PU, the second transistor M2 and the fifth transistor M5 are turned on, when the clock signal input terminal CLK receives the first voltage signal, the bootstrap function of the capacitor C increases the turn-on degree of the second transistor M2 and the fifth transistor M5, at this time, the driving signal output terminal og (n) outputs the first voltage signal, and the cascade signal output terminal oc (n) outputs the first voltage signal.

In this stage, the eighth transistor M8 is kept turned on, the second voltage signal is kept at the pull-down node PD, and the sixth transistor M6 is kept turned off.

In stage 3, the cascade signal input end Oc (n-1) receives the second voltage signal, and the first transistor M1 is turned off; when the cascade signal reset terminal Oc (n +1) receives the first voltage signal, the fourth transistor M4 is turned on, and the pull-up node PU becomes a second voltage signal; the driving signal reset terminal OG (n +1) receives the first voltage signal, the third transistor M3 is turned on, and the driving signal output terminal OG (n) drops to the third voltage signal. I.e. the capacitor C has finished discharging.

Since the upper node PU changes to the second voltage signal, the eighth transistor M8 is turned off, and since the seventh transistor M7 is turned on, the pull-down node PD is pulled up to the first voltage signal, the sixth transistor M6 is turned on, and the cascade signal output terminal oc (n) outputs the second voltage signal.

Stage 4, the cascade signal input end Oc (n-1) receives the second voltage signal, and the first transistor M1 is turned off; the cascade signal reset terminal Oc (n +1) receives the second voltage signal, the fourth transistor M4 is turned off, and the second voltage signal is maintained at the pull-up node PU; the driving signal reset terminal OG (n +1) receives the second voltage signal, the third transistor M3 is turned off, and the driving signal output terminal OG (n) holds the third voltage signal.

In this stage, the second voltage signal is maintained at the upper node PU, the eighth transistor M8 is turned off, the seventh transistor M7 is turned on, the first voltage signal is maintained at the pull-down node PD, the sixth transistor M6 is turned on, and the cascade signal output terminal oc (n) maintains outputting the second voltage signal.

In this embodiment, the cascade input module 100, the cascade output module 500, and the cascade reset module 400 in the shift register unit are used to complete the cascade driving and resetting of the shift register unit; meanwhile, the output driving and resetting of the shift register units are completed by the driving output module 200 and the driving reset module 300, so that the requirements of each level of shift register units on cascade signals and driving signals in a low-temperature environment can be met, and the display can work normally. In addition, in a low-temperature environment, the threshold voltage of the TFT in the shift register unit may drift, and this embodiment may respectively adjust the voltage signals received by the second power supply terminal and the third power supply terminal, and reduce the influence of the threshold voltage drift on the shift register unit, so that the voltage signal output by the cascade output module or the driving output module can meet the requirements of cascade connection or driving, thereby improving the adaptability of the shift register unit to the low-temperature environment and improving the reliability of the display.

Fig. 4 is a schematic diagram illustrating another shift register unit according to an embodiment of the present invention. Referring to fig. 4, the shift register unit further includes a pull-down enhancing module 700 on the basis of the shift register unit shown in fig. 1. The pull-down enhancing module 700 is connected to the cascade signal input terminal Oc (n-1), the pull-down node PD and the second power source terminal LVGL, and configured to provide the second voltage signal received by the second power source terminal LVGL to the pull-down node PD in response to the cascade signal received by the cascade signal input terminal Oc (n-1). In this embodiment, by providing the pull-down enhancing module 700, it is ensured that the pull-down node PD is the second voltage signal in the process of inputting the first voltage signal to the cascade signal input terminal Oc (n-1), i.e., the sixth transistor M6 is kept in the off state, so as to prevent the cascade signal output terminal Oc (n) from being output erroneously.

Fig. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. Referring to fig. 5, the shift register unit further includes a cascade reset enhancing module 800 on the basis of the shift register unit shown in fig. 1. The cascade reset boosting module 800 is connected to the pull-up node PU, the pull-down node PD, and the second power source terminal LVGL, and configured to provide a second voltage signal to the pull-up node PU in response to a voltage signal of the pull-down node PD. Thus, in this embodiment, the cascade reset enhancement module 800 is arranged, so as to keep synchronous action with the cascade signal reset terminal Oc (n +1), enhance the success rate of changing the pull-up node PU into the second voltage signal, and ensure the reliable operation of the shift register unit.

Fig. 6 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. Referring to fig. 6, the shift register unit further includes a driving reset enhancement module 900 on the basis of the shift register unit shown in fig. 1. The driving reset boost module 900 is connected to the pull-down node PD, the driving signal output terminal and the third power terminal, and is configured to provide the third voltage signal received by the third power terminal VGL to the driving signal output terminal og (n) in response to the voltage signal of the pull-down node PD.

Thus, in this embodiment, by providing the driving reset enhancement module 900, the driving output module 300 can be ensured to reliably output the third voltage signal, and the shift register unit can be ensured to reliably operate.

Fig. 7 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. Referring to fig. 7, the shift register unit further includes a noise removing module 1000 on the basis of the shift register unit shown in fig. 1. The denoising module 1000 is connected to the pull-up node PU, the second power source terminal LVGL and the denoising signal input terminal Trst, and configured to provide the second voltage signal received by the second power source terminal LVGL to the pull-up node PU in response to the denoising signal received by the denoising signal input terminal Trst. Thus, in this embodiment, by providing the denoising module 1000, the pull-up node PU can be denoised for multiple times between two frames of images, so as to eliminate the influence of noise, such as clock Coupling noise voltage, on the shift register unit, and ensure the stability of the output signal of the shift register unit.

It should be noted that the pull-down enhancing module 700, the cascade reset enhancing module 800, the driving reset enhancing module 900 or the denoising module 1000 may be implemented by using one or more NMOS transistors, and one or more of the pull-down enhancing module 700, the cascade reset enhancing module 800, the driving reset enhancing module 900 or the denoising module 1000 may be selected to be integrated in a shift register unit, so that the integrated shift register unit has corresponding functions. In order to facilitate understanding of the skilled person, in an embodiment of the present invention, the pull-down enhancing module 700, the cascade reset enhancing module 800, the driving reset enhancing module 900, and the denoising module 1000 are all implemented by using one NMOS transistor, and are simultaneously integrated into one shift register unit, so as to obtain a circuit diagram of the shift register unit shown in fig. 8. Referring to fig. 8 and 3, the operation process of the shift register unit includes:

in the stage 1, the cascade signal input end Oc (n-1) receives the first voltage signal, and the first transistor M1 and the ninth transistor M9 are turned on; the cascade signal reset terminal Oc (n +1) receives the second voltage signal, and the fourth transistor M4 is turned off; the driving signal reset terminal OG (n +1) receives the third voltage signal, and the third transistor M3 is turned off. When the first voltage signal is received, the upper node PU is the first voltage signal. When the upper node PU is the first voltage signal, the second transistor M2 and the fifth transistor M5 are turned on, and the clock signal input terminal CLK receives the second voltage signal, so the driving signal output terminal og (n) outputs the second voltage signal. Since the upper node PU is the first voltage signal, the eighth transistor M8 is turned on, and the pull-down node PD is pulled down to the second voltage signal, at which time the sixth transistor M6, the tenth transistor M10 and the eleventh transistor M11 are turned off. The fifth transistor M5 being turned on and the sixth transistor M6 being turned off may enable the cascade signal output terminal oc (n) to output the second voltage signal. Meanwhile, the capacitor C holds the first voltage signal.

The noise removing signal input terminal Trst receives the second voltage signal or the third voltage signal, and the twelfth transistor M12 is turned off.

In stage 2, the cascade signal input end Oc (n-1) receives the second voltage signal, and the first transistor M1 is turned off; the cascade signal reset terminal Oc (n +1) receives the second voltage signal, and the fourth transistor M4 is turned off; the driving signal reset terminal OG (n +1) receives the third voltage signal, and the third transistor M3 is turned off. Due to the holding effect of the capacitor C, the first voltage signal is at the upper node PU, and the second transistor M2, the fifth transistor M5 and the eighth transistor M8 are turned on. When the clock signal input terminal CLK receives the first voltage signal, the bootstrap action of the capacitor C increases the turn-on degree of the second transistor M2 and the fifth transistor M5, at this time, the driving signal output terminal og (n) outputs the first voltage signal, and the cascade signal output terminal oc (n) outputs the first voltage signal.

In this stage, the eighth transistor M8 remains turned on, the second voltage signal is maintained at the pull-down node PD, and the sixth transistor M6, the tenth transistor M10, and the eleventh transistor M11 remain turned off.

In stage 3, the cascade signal input end Oc (n-1) receives the second voltage signal, and the first transistor M1 is turned off; the cascade signal reset terminal Oc (n +1) receives the first voltage signal, the fourth transistor M4 is turned on, the pull-up node PU changes into the second voltage signal, and the second transistor M2, the fifth transistor M5 and the eighth transistor M8 are turned off; the driving signal reset terminal OG (n +1) receives the first voltage signal, the third transistor M3 is turned on, and the driving signal output terminal OG (n) drops to the third voltage signal. I.e. the capacitor C has finished discharging.

The eighth transistor M8 is turned off due to the change of the second voltage signal at the upper node PU, the seventh transistor M7 is turned on, the pull-down node PD is pulled up to the first voltage signal, the sixth transistor M6, the tenth transistor M10 and the eleventh transistor M11 are turned on, the cascade signal output terminal oc (n) outputs the second voltage signal when the tenth transistor M10 is turned on, and the pull-up node PU becomes the second voltage signal; when the eleventh transistor M11 is turned on, the driving signal output terminal og (n) drops to the third voltage signal.

Stage 4, the cascade signal input end Oc (n-1) receives the second voltage signal, and the first transistor M1 is turned off; the cascade signal reset terminal Oc (n +1) receives the second voltage signal, the fourth transistor M4 is turned off, the second voltage signal is maintained at the pull-up node PU, and the second transistor M2, the fifth transistor M5 and the eighth transistor M8 are turned off; the driving signal reset terminal OG (n +1) receives the second voltage signal, the third transistor M3 is turned off, and the driving signal output terminal OG (n) holds the third voltage signal.

In this stage, the second voltage signal is maintained at the upper node PU, the eighth transistor M8 is turned off, the seventh transistor M7 is turned on, the first voltage signal is maintained at the pull-down node PD, the sixth transistor M6, the tenth transistor M10 and the eleventh transistor M11 are turned on, the second voltage signal is maintained at the cascade signal output terminal oc (n), the second voltage signal is output from the cascade signal output terminal oc (n) when the tenth transistor M10 is turned on, and the second voltage signal is changed at the pull-up node PU; when the eleventh transistor M11 is turned on, the driving signal output terminal og (n) drops to the third voltage signal.

After stage 4, the noise-removal signal input terminal Trst receives the first voltage signal, and the twelfth transistor M12 is turned on, so that noise removal can be performed on the pull-up node PU for multiple times between two frames of images, the influence of noise, such as clock Coupling noise voltage, on the shift register unit is eliminated, and the stability of the output signal of the shift register unit is ensured.

An embodiment of the present invention further provides a gate driving circuit, and fig. 9 is a connection relationship diagram of the gate driving circuit according to the embodiment of the present invention. Referring to fig. 9, the gate driving circuit includes: a plurality of cascaded shift register units; each shift register unit can be the shift register unit shown in the embodiments of fig. 1 to 8;

a cascade signal input end of the first-stage shift register unit is connected with an initial signal end STV of the grid drive circuit, a cascade signal reset end Oc (1) of the first-stage shift register unit is connected with a cascade signal output end Oc (2) of the second-stage shift register unit, and a drive signal reset end OG (2) of the first-stage shift register unit is connected with a drive signal output end OG (1) of the second-stage shift register unit; a cascade signal input end Oc (m +1) of the last stage of shift register unit is connected with a cascade signal output end Oc (m) of the previous stage of shift register unit, and a drive signal reset end OG (m +1) of the last stage of shift register unit is connected with an initial signal end STV;

except the first stage and the last stage of shift register units, cascade signal input ends Oc (n) of the other shift register units at each stage are connected with a cascade signal output end Oc (n-1) of the shift register unit at the upper stage, cascade signal reset ends Oc (n +1) are connected with a cascade signal output end Oc (n +1) of the shift register unit at the lower stage, and driving signal reset ends OG (n) are connected with a driving signal output end OG (n +1) of the shift register unit at the lower stage.

The embodiment of the invention also provides a display device which comprises a display module and the gate drive circuit.

The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.

In the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims

1. A shift register cell, comprising: the device comprises a cascade input module, a cascade output module, a cascade reset module, a drive output module, a drive reset module and a pull-down module;

the cascade output module is electrically connected with the pull-up node, the pull-down node, the clock signal input end, the second power end and a cascade signal output end, and is used for responding to voltage signals of the pull-up node and the pull-down node and providing the second voltage signal or the clock signal to the cascade signal output end;

the unit also comprises a noise removal module; the de-noising module is connected with the pull-up node, the second power end and a de-noising signal input end, and is used for responding to a de-noising signal received by the de-noising signal input end and providing the second voltage signal to the pull-up node;

the voltage signals received by the second power supply terminal and the third power supply terminal are related to the threshold voltage of the transistors in the shift register unit.

2. The shift register cell of claim 1, wherein the cascade input module comprises a first transistor; and the control electrode and the first electrode of the first transistor are connected to the cascade signal input end, and the second electrode of the first transistor is connected with the pull-up node.

3. The shift register cell of claim 1, wherein the driving output module comprises a second transistor and a capacitor; the capacitor is connected between the pull-up node and the drive signal output end in series; and the control electrode of the second transistor is connected with the pull-up node, the first electrode of the second transistor is connected with the clock signal input end, and the second electrode of the second transistor is connected with the driving signal output end.

4. The shift register cell of claim 1, wherein the driving reset module comprises a third transistor; and a control electrode of the third transistor is connected with the drive signal reset end, a first electrode of the third transistor is connected with the drive signal output end, and a second electrode of the third transistor is connected with the third power supply end.

5. The shift register cell of claim 1, wherein the cascade reset module comprises a fourth transistor; and a control electrode of the fourth transistor is connected with the cascade signal reset end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the second power supply end.

6. The shift register cell of claim 1, wherein the cascade output module comprises a fifth transistor and a sixth transistor;

7. The shift register cell of claim 1, wherein the pull-down module comprises a seventh transistor and an eighth transistor;

8. The shift register cell of claim 1, further comprising a pull-down boost module connected to the cascade signal input terminal, the second power supply terminal, and the pull-down node for providing the second voltage signal to the pull-down node in response to the cascade signal.

9. The shift register cell of claim 8, wherein the pull-down enhancement module comprises a ninth transistor; and a control electrode of the ninth transistor is connected with the cascade signal input end, a first electrode of the ninth transistor is connected with the pull-down node, and a second electrode of the ninth transistor is connected with the second power supply end.

10. The shift register cell of claim 1, further comprising a cascaded reset enhancement module; the cascade reset enhancement module is connected with the pull-up node, the pull-down node and the second power end, and is used for responding to a voltage signal of the pull-down node and providing the second voltage signal to the pull-up node.

11. The shift register cell of claim 10, wherein the cascaded reset boost module comprises a tenth transistor; and a control electrode of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the pull-up node, and a second electrode of the tenth transistor is connected with the second power supply end.

12. The shift register cell of claim 1, further comprising a drive reset boost module; the driving reset enhancement module is connected to the pull-down node, the driving signal output end and the third power end, and is configured to respond to a voltage signal of the pull-down node and provide the third voltage signal to the driving signal output end.

13. The shift register cell of claim 12, wherein the driving reset boost block comprises an eleventh transistor; a control electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the driving signal output end, and a second electrode of the eleventh transistor is connected to the third power supply end.

14. The shift register cell of claim 1, wherein the coring module comprises a twelfth transistor; and a control electrode of the twelfth transistor is connected with the denoising signal input end, a first electrode of the twelfth transistor is connected with the pull-up node, and a second electrode of the twelfth transistor is connected with the second power supply end.

15. A gate drive circuit is characterized by comprising a plurality of cascaded shift register units; each shift register cell is a shift register cell according to any one of claims 1 to 14;

16. A display device comprising the gate driver circuit according to claim 15.