CN107924699A - Part/complete array/block erasing for 2D/3D hierarchy types NAND - Google Patents

Abstract

A kind of novel 2D/3D hierarchy types BL NAND arrays, with at least one plane in independent substrate P, including multiple LG groups associated with multiple local bitlines (LBL) respectively, the multiple LBL is arranged in the multiple disconnections for being connected to page buffer or does not disconnect the level below global bit line (GBL).Every LG groups include multiple pieces and independent power supply line are connected to each in the multiple LBL.Each piece includes the N positions 2D/3D NAND strings each with S unit, and the unit is connected in series and is terminated by two string selection devices and be coupled to common source line.Exactly, random size partial block WL is each piece that is used to wipe of the random selected LG groups of a plane selected from the 2D/3D NAND arrays, while border WL optionally by pre-read and is programmed into another plane of the 2D/3D NAND arrays or is preserved optionally outside chip and write-back is for data safety.

Description

Part/complete array/block erasing for 2D/3D hierarchy types NAND

Cross reference to related applications

It is described this application claims the priority of the 62/152nd, No. 744 U.S. Provisional Application filed in 24 days April in 2015 Application is commonly assigned and is incorporated herein by reference for all purposes.

This application involves No. 14/283,209, No. 14/316,936, No. 14/341,739, the 14/487,078th Number, No. 14/583,178, No. 14/806,629, No. 14/828,427, No. 14/859,237 and the 14/970th, No. 525 U.S. Patent applications, above U.S. Patent application are created and for all purposes by reference by same inventor It is incorporated herein.

Technical field

The present invention relates to a kind of NAND array, particularly relates to one kind and is based on 2 level part/global bit line (BL) hierarchy type framves In part/complete battle array while programming and read operation is performed at the same time on another part array in the 2D/3D NAND arrays of structure The 3D of improved part/complete array on some randomly selected complete or partial memory blocks/block erasing scheme in row NAND array.

Background technology

Prior art 2D nand memories and system based on NAND are not only feasible options, but have been changed to use In desktop and laptop computer, cellular phone, data center and/or the extremely popular component of network storage application.For The five-star technology node of 2D NAND designs is 15nm nodes (1y nodes) and most high-density is every 8 states of nude film 128Gb TLC.In order to increase nude film memory density the further 2D NAND below 15nm nodes are scaled to beyond 128Gb Unit and technology have run into great challenge due to having reached technology and physical unit limitation.Deposited to increase NAND nude films Reservoir density reaches the even above level of 1Tb beyond 128Gb, and NAND industries use 3D NAND cell skills in the several years Art is as the replacement solution for surmounting 2D NAND technologies.Currently, stored from 2D the and 3D NAND Flashes of SLC, MLC to TLC Device and system design coexist, but 2D NAND capture more market shares.

Although the nude film density of 3D NAND technologies seems there is being prospect in the recent period, 3D NAND are designed more than 2D The improvement of the Performance And Reliability of NAND corresponding parts is only about 2 times and not notable.When flash technology is moved to for 2D Spacing between the 1xnm nodes of NAND and 2xnm nodes for 3D NAND and neighbouring BL and between neighbouring WL is more and more closer When, harshness of any two physically between BL be long keep AC (BL-BL switching charge/discharges cause) coupling effect and Any two physically (imitate the DC between BL and WL (BL-BL and WL-WL programming thresholds Vt cause) coupling effect by Yupin Should) already lead to that the height with more wrong and less P/E circulations (P/E cycle) is unreliable or nLC that even fail is grasped Make, particularly for more level NAND programming and read operation such as MLC, TLC, not to mention XLC.

In addition, the progress of NAND cell bi-directional scaling is also for example programmed in 2D and 3D NAND quick-flash memories, read Take, programmed check and erasing are examined etc. in all aspects so that HV Vpgm, MHV Vpass during corresponding nLC is operated and LHV Vread grids disturb or stress problem deteriorates.It is used to select block during nLC programming operations it should be noted that above HV is represented (block) high voltage (HV) of single 16V to the 25V for selecting programmed WL in.Above MHV was represented in the nLC programming operation phases Between be used for the high voltage appearance (MHV) of selecting the about 10V of Z in NAND block unselected transmissions WL, when NAND string including with Z=63 during 64 units that two selected transistors are connected.Finally, above LHV is represented during nLC read operations for each In selected NAND block as a 63 unselected WL of Z for transmitting WL 6V low high voltage.Three above grid voltage stress Degree be Vpgm in order>Vpass>Vread, and gate stress or interference time are Tread in order>Tpass>Tpgm. For example, Tpass=64 × Tpgm in 64 unit NAND string arrays, and usually because reading ratio in most NAND applications Programming is more, so Tread>1,000×Tpgm.

In general, the average P/E circulation specifications for SLC NAND are 100K, and MLC NAND are about 10K, TLC NAND is 3K or lower, and is not specifically mentioned in NAND product specifications and reads P/E circulations and perform.But empirically rule, reads P/E circulations specification is about 1000 times of each corresponding nLC P/E circulations specification.In conclusion minimum Vread has minimum HV Stress, therefore minimum data degradation, and highest Vpgm has highest HV programming stress, therefore worst data degradation and P/E NAND.Therefore, Vpgm plays main function in final P/E circulations specification is determined.

In fact, during the NAND product life cycles total HV stress of 2D and 3D NAND Flashes unit be not limited only to HV programmings and read operation described in upper 3 kinds.In addition, routinely, HV 20V (Verase) stress ratio of NAND erasing operations Vpgm stress is much higher, because even Verase is set to, such as Verase=Vpgm=20V, Terase compatible with Vpgm It is more much longer than Tpgm, Terase>>Tpgm.For example, Terase>2ms, and Tpgm is TSLC=250 μ s, TMLC=750 μ S, TTLC ≈ 1 arrives 2ms.

Stated differently, since TLC NAND are gradually popular in 2015 and later NAND markets, therefore nLC programmings The degree of tediously long circulation time and programmed check and erasing stress plays almost equal in final P/E circulation specifications are determined Effect.In addition, designed for more successful TLC, it is also necessary to think better of Vpass and Vread stress.Therefore, in 2D and 3D In NAND designs, not only increase the more effective voltage of P/E circulations but also all HV, MHV and LHV stress of increase P/E/R circulations The key for becoming nLC life cycles is reduced with the time.It should be noted that E represents erasing herein, P represents programming, and R is represented and read.

AC and DC BL-BL and WL-WL coupling effect in view of the above and HV, MHV and LHV stress, although in number Many technologies are proposed in year and using conventional non-hierarchy type 2D and 3D NAND designs and production, but these technologies can not have Reduce the HV stress times and voltage of change in effect ground.In addition, in conventional NAND designs, in every NAND planes every time Alternative performs the only one NAND such as reading, programmed and erased and operates, therefore whole nand memory and system performance Drastically decline.

Therefore, it is intended that read while permission in any part/complete 2D/3D NAND planes, programming and erasing operation Improved 2D/3D hierarchy types NAND array framework, effectively realize nLC read, the HV stress voltages of programming and erasing operation, The reduction of delay, power consumption and wrong bits number.

The content of the invention

The embodiment of the present invention relates generally to memory architecture and operations associated.More precisely, the present invention provides Unit based on part/global bit line (BL) framework in the part of 2D/3D hierarchy type NAND arrays/complete plane it is random big Improved part/complete array/block erasing operation scheme on fraction block.The embodiment of the present invention is multiple selected at random Simultaneously erased operation scheme is partly or completely provided in monoblock, risk and side with the break-through between border WL and selected WL The compromise of the loss of data of boundary's WL units.These schemes can be applied in the design of 2D and 3D hierarchy types nand memory.

In the embodiment summarized below of the present invention, with reference to the attached drawing for the part for forming the present invention, and by means of figure Show and show the specific embodiment that can put into practice the disclosure.In the drawings, described generally throughout some views, identical label Similar component.Other embodiments can be utilized without departing from the scope of the disclosure, and can make structure, logic Change with electricity.

In one embodiment, the present invention provides a kind of hierarchy type array structure, its implement in 2D and 3D NAND arrays with Allow reading, three high latencies of programming and erasing operation and HV stress by multiple selected complete at random and These operations are performed at the same time in partial block and are reduced.

In another embodiment, the present invention provides a kind of be particularly useful in any of 2D and 3D hierarchy type NAND arrays The injection of the method that enforcement division piecemeal is wiped in NAND planes, either GIDL hot holes or the erasing scheme type of FN tunnellings, Or either 2D/3D unit classes of 1- polysilicons trapping charge NAND cell or 2- Polysilicon floating gate NAND cells Type.

In another embodiment, the present invention provides a kind of any NAND being used in any 3D hierarchy types NAND designs and puts down Reading at the same time, the method for programming and erasing operation are performed in face, no matter peripheral circuit is formed at outside or just in 3D Below NAND array.

In a specific embodiment, the present invention provides a kind of 3D NAND arrays with 2 level hierarchical bit-line architectures. The 3D NAND arrays include the one or more planes being formed in the substrate P of isolation.Each plane is included with being drawn by group What the separated K 3D HG groups of separating device were associated is arranged in multiple global positions at the first level on bit line (BL) direction Line (GBL).Every 3D HG group divisions are into J 3D LG group.Every 3D LG groups are multiple at the second level with being arranged in Local bitline (LBL) is associated, and the multiple LBL distinguishes parallel to the multiple GBL and via multiple GBL/LBL on-off circuits It is coupled to the multiple GBL.A pair of of 3D LG groups connect via a line TIE signal control devices.Every 3D LG groups bag Containing H block (block).The H it is in the block each include the multiple 3D associated with the multiple LBL respectively NAND string, it is described string along be orthogonal to wordline (WL) direction in the BL directions in a row and cascade and jointly via a line preliminary filling Electric installation and two PRE signals couple for by odd and even number LBL it is corresponding be coupled to along the WL directions be arranged in the The independent electrical line of force in three levels.Every 3D NAND strings include a series of S 3D NAND cells, and the unit is being orthogonal to State on the stacking direction in BL directions and the WL directions stacked around perpendicular block area (vertical bulk region) and Its source node is made by a pair of string selection device termination, the 3D NAND strings in two ends of the 3D NAND strings respectively It is connected to each or multiple pieces of common source line.The perpendicular block area is isolated from the substrate P of the plane.K, J, H and S It is more than 2 integer and bigger based on memory chip design.

In another specific embodiment of the invention, the present invention, which provides, a kind of has 2 level hierarchical bit-line architectures 3D NAND arrays.The 3D NAND arrays include one or more NAND planes with independent substrate P.Each plane includes The multiple global positions that are arranged in first level associated with J 3D HG group being connected with each other by a line 3D DGBL circuits Line (GBL).Every 3D HG group divisions are into N₂A 3D LG groups.Every 3D LG groups are more at the second level with being arranged in A local bitline (LBL) is associated, and the multiple LBL is parallel to GBL directions and via multiple 3D GBL/LBL on-off circuits point It is not coupled to the multiple GBL.Every 3D LG groups include H block.The H it is in the block each include respectively with it is described Multiple 3D NAND strings that multiple LBL are associated, the string is along being orthogonal to wordline (WL) direction in the GBL directions in a row And cascade and coupled jointly via a line 3D pre-charging devices and extra 3D EPR control devices with two PRE signals for inciting somebody to action Odd and even number LBL is accordingly coupled to the independent electrical line of force being arranged in along the WL directions in third layer level.Every 3D NAND String includes a series of S 3D NAND cells formed with U-shape, and two part strings are being orthogonal to the GBL directions and the WL Stack around perpendicular block area on the stacking direction in direction and linked at the bottom of the string by BG control devices.The 3D NAND string make its source node be connected to by SSL signals control first string selection device and make its drain node be connected to by Second string selection device of GSL signals control and it is coupled to each or multiple pieces of common source line.The perpendicular block area It is isolated from the substrate P of the plane.J、N₂, H and S based on memory chip design be more than 2 integer and bigger.In addition, institute State 3D NAND arrays and include block decoder, it is configured to control one group of voltage signal from voltage generator using latch signal It is delivered to the SSL and GSL of the first and second strings selection device of all WL and every piece respectively via one group of global bus. In addition, the 3D NAND arrays include one group of decoder, it is used to send respectively to the row 3D DGBL devices, multiple 3D The control signal of GBL/LBL on-off circuits, two PRE signals and the epr signal for a line 3D pre-charging devices.In addition, The 3D NAND arrays include drive circuit, its be used for the respectively common source line of each or multiple pieces and The independent electrical line of force per 3D LG groups provides voltage signal.

In still another embodiment, the present invention provides a kind of NAND gusts of 3D with 2 level hierarchical bit-line architectures Row.The 3D NAND arrays include one or more NAND planes in corresponding substrate P.Each plane is included with being drawn by group What the separated K 3D HG groups of separating device were associated is arranged in multiple global positions at the first level on bit line (BL) direction Line (GBL).Every 3D HG group divisions are into J 3D LG group.Every 3D LG groups are multiple at the second level with being arranged in Local bitline (LBL) is associated, and the multiple LBL is parallel to the multiple GBL and via multiple 2D GBL/LBL on-off circuits It is respectively coupled to the multiple GBL.A pair of of 3D LG groups connect via a line 2D TIE signal control devices.Every 3D LG Group includes H block.The H it is in the block each include multiple 3D NAND strings associated with the multiple LBL respectively, It is described string along be orthogonal to wordline (WL) direction in the BL directions in a row and cascade and jointly via a line 2D preliminary filling Densos Put to two PRE signals couple for by odd and even number LBL it is corresponding be coupled to along the WL directions be arranged in third layer The independent electrical line of force in level.Every 3D NAND strings include a series of S 3D NAND cells, and the unit is being orthogonal to the BL Stacked on the stacking direction in direction and the WL directions around perpendicular block area.The 3D NAND strings connect its source node It is connected to the first string selection device controlled by SSL signals and its drain node is connected to the second string choosing controlled by GSL signals Select device and be coupled to each or multiple pieces of common source line.The perpendicular block area is formed directly into the P of the plane On substrate.K, J, H and S based on memory chip design be more than 2 integer and bigger.In addition, the 3D NAND arrays include Block decoder, it is configured to control one group of voltage signal from voltage generator via one group of global bus point using latch signal Supplementary biography is delivered to the SSL and GSL of the first and second strings selection device of all WL and every piece.In addition, described 3D NAND gusts Row include one group of decoder, it is used to send the control to the group division device, every 2D GBL/LBL on-off circuits respectively Signal processed, the TIE signals for every a line TIE signal control devices, two PRE signals for 2D pre-charging devices.In addition, The 3D NAND arrays include drive circuit, its be used for the respectively common source line of each or multiple pieces and The independent electrical line of force per 3D LG groups provides voltage signal.

Brief description of the drawings

The other features and effect of the present invention, will clearly be presented in the embodiment with reference to schema：

Figure 1A shows the 2- in triple p-wells (TPW) in the deep N-well (DNW) in 2D NAND strings and on substrate P The cross-sectional view of Polysilicon floating gate 2D NMOS NAND cells.

Figure 1B shows the cross-sectional view of the 1- polysilicon trapping charge layer 3D NMOS NAND cells in 3D cylinder strings, Block is in center ring and WL grids are formed in external rings.

Fig. 2 is the circuit of preferably 2 level hierarchical LBL/GBL2D/3D NAND chips according to an embodiment of the invention Figure, has at least two independent 2D/3D NAND planes divided by a line 20V NMOS ISO circuits.

Fig. 3 A are the simplification of the J 2D/3D HG group in the 2D/3D NAND planes shown in Fig. 2 with the GBL disconnected Circuit diagram.

Fig. 3 B be it is according to an embodiment of the invention have every LBL be connected to the independent electrical line of force via pre-charging device The simplification figure of LG groups in the 2D/3D hierarchy type NAND arrays of LGps.

Fig. 3 C are the LG Y- according to an embodiment of the invention that GBL is connected to LBL in 2D hierarchy type NAND arrays The simplification figure of Pass circuits.

Fig. 3 D are the LG according to an embodiment of the invention that GBL is connected to LBL in 2D/3D hierarchy type NAND arrays The simplification figure of Y-Pass circuits.

Fig. 3 E are according to an embodiment of the invention GBL is connected to N/4 data in 2D hierarchy type NAND arrays to delay Rush the simplification figure of the LV Y-Pass circuits for being coupled to HV ISO circuits of device.

Fig. 3 F are according to an embodiment of the invention GBL is connected to N/2 data in 3D hierarchy type NAND arrays to delay Rush the simplification figure of the LV Y-Pass circuits for being coupled to HV ISO circuits of device.

Fig. 3 G are two LG groups by a line HV 3D ISO circuits division for 3D hierarchy type NAND arrays of the present invention The simplified electrical circuit diagram of group.

Fig. 4 shows according to an embodiment of the invention one shared in a LG group of 2D hierarchy type NAND arrays The circuit of the neighbouring 2D NAND blocks of two with N number of LBL of common source line CSL.

Fig. 5 A show a part for 3D hierarchy types NAND array according to an embodiment of the invention.

Fig. 5 B show a part for 3D hierarchy type NAND arrays according to another embodiment of the present invention.

Fig. 5 C show a part for the 3D hierarchy type NAND arrays of still another embodiment according to the present invention.

Fig. 5 D show a part for the 3D hierarchy type NAND arrays of another embodiment according to the present invention.

Fig. 5 E show a part for the 3D hierarchy type NAND arrays of another embodiment according to the present invention.

Fig. 6 be it is according to an embodiment of the invention combined with 2D/3D hierarchy type NAND arrays have latch control it is excellent The circuit diagram of block decoder is selected, the input of described one group of global bus of block decoder bridge joint and the grid and string of all wordline select Select the common gate of device.

Fig. 7 A to 7F are the random size portions in the 2D hierarchy type NAND arrays according to an embodiment of the invention for Fig. 2 The circuit diagram of the sets of bias conditions of the various different situations of piecemeal erasing operation.

Fig. 8 shows the random size partial block erasing behaviour of the 2D according to an embodiment of the invention with just bias condition Make.

Fig. 9 A show the complete or part according to an embodiment of the invention under the 3D hierarchy type NAND arrays of Fig. 5 A The preferred set of the bias condition of block erasing operation.

Fig. 9 B show the complete or part according to an embodiment of the invention under the 3D hierarchy type NAND arrays of Fig. 5 B The preferred set of the bias condition of block erasing operation.

Fig. 9 C show the complete or part according to an embodiment of the invention under the 3D hierarchy type NAND arrays of Fig. 5 C The preferred set of the bias condition of block erasing operation.

Fig. 9 D show the complete or part according to an embodiment of the invention under the 3D hierarchy type NAND arrays of Fig. 5 D The preferred set of the bias condition of block erasing operation.

Fig. 9 E show the complete or part according to an embodiment of the invention under the 3D hierarchy type NAND arrays of Fig. 5 E The preferred set of the bias condition of block erasing operation.

Figure 10 is selected in the selected string according to an embodiment of the invention shown for 3D hierarchy type NAND arrays The iteration erasing of 3D units and the figure of erasing check pulse.

Embodiment

Before the present invention is described in detail, it shall be noted that in the following description content, similar element is with identical Number to represent.

In the detailed description below of the embodiment of the present invention, with reference to same inventor submit it is previous pending application or Provisional application and part thereof of attached drawing is formed, and shown that by means of diagram the specific embodiment of the disclosure can be put into practice. In attached drawing, identical label describes generally similar component in some figures.These embodiments are retouched by enough details It is stating so that those skilled in the art can put into practice embodiment.Without departing from the scope of the disclosure can profit With other embodiments, and any structure, logic and electricity can be made and changed.Therefore, it is described in detail below to be not intended to as limit Property or be limited to disclosed precise forms.

In the following description, when referring to N nLC nand memories, it, which means, resides in a physics WL or page The physics nLC NAND cells of 16KB altogether, in order to which the description of 2D and 3D NAND is simple and does not include the sub- ECC word of additional corrections Section.In this application, N WL pages of complete physicals for implying that 16KB nLC units.And then N/2 imply that 8KB (N¹Position), it is Store the 1/2 or 1/2WL sizes of a complete physical page of 8KB routine nLC NAND cells.In addition, N/4 imply that 4KB (N² Position), it is the 1/4 or 1/4WL sizes of a complete physical page of storage 4KB routine nLC NAND cells.

In the present specification, 2D hierarchy types NAND array is used as example to illustrate the creative feature of the disclosure.It is hereafter general The main feature of this 2D hierarchy type NAND array is included, and details will be further seen in Fig. 2,3A and 4 description, part details is Through in the one or more prior U.S. Patent applications being incorporated by reference for all purposes (such as No. 14/970,525 U.S. Patent application) disclosed in：

1) 2D hierarchy types BL structures：A) the 2D NAND arrays include one or two physically single NAND plane, Complete physical TPW and DNW is separated by a line of the first ISO 20V circuits on bit line (BL) or Y-direction；B) it is each NAND planes sentence 4 λ spacing by N included in top M2 levels¹J HG group of GBL long vertical metals line connection；C) every HG It is further divided into N⁶Multiple LG groups, every LG groups are included by having the short gold of N number of LBL of 2 λ spacing in lower part M1 levels Belong to line and be used for a special LGps metal wires company of Vinh and Vss local precharges and discharge operation at minimum M0 levels The H block connect；D) each NAND block includes N number of NAND string, and X1 2D NAND cell in M0 levels optionally with having common source [two WL go here and there close to each top selects the placement of MHV MS (MSe or MSo) transistor and one to two illusory WL of polar curve (CSL) A close bottom string drain selection transistor MHV MG (MGe or MGo) are placed] be connected in series, top dummy row retain for Saved when being closed systematic electricity Vdd and be used for all unfinished nLC odd numbers or even number N¹The N of bit digital programming data¹Odd number or N¹Even number SLC storage operations；X1=8,16,32,64,128 or any other integer numbers；E) in every LBL shapes of M1 levels It is mono- as 1 dynamic caching register (DCR) for 1 data of interim storage, such as 1 DRAM into CLBL capacitors Member so that J page while and pipeline operation can be performed in one or two physically independent NAND planes on LBL directions；f) Every NAND planes include N number of C_LBLThe N of capacitor⁶Page is as the N positions DCR in every HG, or is respectively coupled to N⁶A LG decodings Device, N⁶A LGps lines and N⁶The N of a LG pre-charge circuits⁶A LG, has the N/4 positions (N substantially reduced²Position) data buffer (DB) and N/4 (N²Position) static cache register (SCR), every DB include a N/4 multipliers, one N/4 Sense amplifier (SA) and N/4 programming read buffers (PR/B).

2) GBL and LBL connection modes：a)(GBL//LBL)⊥(CSL//LGps).Optionally, a M2GBL is based on a pair One basis is connected to a M1LBL, i.e. N number of M2GBL is connected to N number of M1LBL.Optionally, a M2GBL is connected to 2/4/8 M1LBL, i.e. imply that N/2 or N/4 or N/8 M2GBL are connected to N number of M1LBL.Optionally, a physics WL has N number of NAND Unit.Optionally, M0CSL and M0LGps lines are arranged perpendicularly to M2GBL and M1LBL.b)(GBL//LBL//LSL)⊥LGps). Optionally, a M2GBL is connected to a M1LBL, i.e. N/2 M2GBL is connected to N/2 shared by N number of NAND string M1LBL.Optionally, a M1LBL is shared by two NAND strings, and a neighbouring LBL is used as a locally specified localized source Polar curve (LSL).In other words, at all without CSL lines in whole array.Optionally, it is arranged perpendicularly in the LGps lines of M0 levels M2GBL, M1LBL and M1LSL line.Optionally, a physics WL has N number of NAND cell.

3) the staggeredly odd number and even number LBL of nLC programmings and programmed check scheme preferably in each single physical WL are mono- Performed in a rotative pattern between member：A) in the case of (GBL//LBL) ⊥ (CSL//LGps), optionally, if a M2GBL Be connected to 1 M1LBL, then with 8TLC fine programs in a single WL using 3 steps, 1-4-8-8TLC, AVtz, ABL, Alt-LBL, Alt-WL, N programmings and N programmed check schemes.Optionally, if a M2GBL is connected to 2/4/8 M1LBL, then 3 steps, 1-4-8-8TLC AVtz, similar ABL, Alt- are used in a single WL with 8TLC fine programs LBL, N/2 programmings and N/2 programmed check schemes.Alt-LBL is implied that performs behaviour at alternate odd and even number LBL units Make.Optionally, programming operation can be performed at the same time for J pages.Optionally, it is being based on source line voltage V without any_SLVt compensation feelings TLC is performed under condition to read.B) in the case of (GBL//LBL//LSL) ⊥ LGps, optionally, if a M2GBL is connected to One M1LBL, then using 2 steps, 1-4-8TLC, AVtz, similar to ABL, Alt-BL, Alt-WL, N/2 in a single WL Programming and N/2 programmed check schemes are without performing 8TLC fine programs.Optionally, it can perform and operate at the same time.Optionally, exist In one single physical WL V is based on N/2_SLVt compensation perform TLC read.

4) the nLC programmings performed in a rotative pattern between 3 physically neighbouring WL and programmed check scheme：A) for 4-Vt MLC Alt-WL are programmed, optionally, using the Alt-WL MLC programmings based on 3WL on conventional non-open WL, and optionally Ground, uses the Alt-WL MLC programmings based on 2WL on open WL.B) program for 7-Vt TLC Alt-WL, opened routinely non- Put using the Alt-WL TLC programmings based on 3WL on WL, or optionally, the Alt-WL TLC based on 2WL are used on open WL Programming.

5) the nLC read schemes in single WL：A) in the case of (GBL//LBL) ⊥ (CSL//LGps), base is not performed In V_SLVt compensation.Optionally, if a M2GBL is connected to a example of a M1LBL, i.e. N number of M2GBL is connected to N number of ML LBL, then 3 N/2 even odd MLC are read is based on V for Q1, Q2 and Q3 without using_SLVt compensation, and 7 N/2 Even odd MLC is read is based on V for P1, P2, P3, P4, P5, P6 and P7 without using_SLVt compensation.Optionally, if one M2GBL is connected to 2/4/8 M1LBL, i.e. N/2 or N/4 or N/8 M2GBL are connected to N number of M1LBL, then 6 N/4 it is strange/ Even MLC is read is based on V for Q1, Q2 and Q3 without using_SLVt compensation, and 14 N/4 even odd MLC read be used for P1, P2, P3, P4, P5, P6 and P7 are based on V without using_SLVt compensation.B) in the case of (GBL//LBL) ⊥ LGps, according to WLn+1TLC page datas use the Vt compensation based on VSL.Optionally, if a M2GBL is connected to a M1LBL, i.e. N/2 A M2GBL is connected to the N/2 M1LBL shared by N number of NAND string, and every M1LBL is shared by two NAND strings.This is to use one A neighbouring situations of the LBL as a locally specified LSL.In addition, 3 N/2 even odd MLC read and are used for Q1, Q2 and Q3, have Have and be based on V_SLVt compensation, and 7 N/2 even odd MLC read and are used for P1, P2, P3, P4, P5, P6 and P7, with being based on V_SL Vt compensation.M0LGps lines are arranged perpendicularly to M2GBL and M1LBL.

6) programmed recording (programming) and the programming of accurate programming state are crossed：A) this is crossed programmed recording and is performed with J page bases plinth.B) mistake Programmed recording is implied that is programmed into P8 by the Vt for crossing programming unit, its is defined to be higher at least than conventional highest nLC programming states 0.5V.For example, if TLC highest programming states are P7, then cross programming unit and arrive P8 by programmed, it has than P7 high At least Vt of 0.5V.C) accurate programming state programming is implied that the true Vt of programming unit excessively according to it in another location NLC data are programmed, the another location can same physics WL it is spare in or difference WL in.Actual value can be stored in one In 1 of one original Vt of a original nLC data or in the n positions SLC forms of good data.For example, each mistake Programming TLC units can be stored in new 3 of new 1 TLC unit or SLC units.D) programming unit is crossed in every nLC WL Sequence be used to be programmed the new sequence of nLC states for crossing programming unit in same or different WL so that executable Accurate Vt compensation is calculated with finding out the original nLC data of programming unit without the ECC for using complexity and taking.E) each choosing The sequence of programming unit and the position excessively determined in nLC WL are by applying Vtp8min=V during P8 crosses programming read operation_WL Obtained to perform extra P8 read operations.Only cross programming unit, it is " 1 " to read numerical data, and remaining of P0 to P7 units Part, it is " 0 " to read data.F) output will sequentially be shifted and by Flash controller outside chip point by crossing programming P8 reading page datas Analysis is to find out the physical location for crossing programming unit in each physics WL, so that Vt compensating operations then can be performed without making Calculated with ECC.

Although with mixing line and at the same time operation 2D and 3D hierarchy type NAND arrays specific embodiment in 2D and 3D Disclosed in NAND manufacturing technologies, but it will be apparent to those skilled in the art that from the present invention other derivatives, modifications and changes and It should be covered by the present invention.The present invention same inventor by having covered some embodiments in prior U.S. Patent application, and Omitted herein in order to describe simple.Hereafter only summarize new inventive concept as set objective.

Explain or define herein some terms used through this specification.

A) ABL programmings represent all bit line programs.In the present invention on the 2 level hierarchical NAND with LBL and GBL Array, it implies that full LBL programmings.

B) programming of similar ABL represents approximate full BL programmings.The even odd of hierarchy type NAND array is selected in first circulation All LBL in numbering row are used to program, and the LBL in idol/odd column is program-inhibited.Then, selected in second circulation even/strange All LBL in row are used to program, but the LBL in even odd row is program-inhibited.In the first and second circulations, programming is performed Examine.In this way, the threshold value Vt coupling effects of BL-BL units can be reduced.

C) AVtz programmings represent programs all 2 at the same timeⁿThe operation of a nLC Vt states, nLC represent different pieces of information storage class Type：N=1 is used for the SLC with 2Vtz, and n=2 is used for the MLC with 4Vtz, and n=3 is used for the TLC with 8Vtz, and n=4 is used In the XLC with 16Vtz, Vte erase status is included.

J pages of mixing line operation at the same time includes subsequent crucial routine NAND operations, and (J implies that generally more numbers herein Mesh, depending on how to divide each plane of 2D/3D NAND arrays via 2 level hierarchical BL frameworks)：

A) J pages of ABL nLC programming：Complete l6KB units in one physics WL of simultaneous selection are programmed for nLC.

B) J pages of N/2 even odd nLC programmed checks：The half page of 8KB units is examined at the same time.

C) J pages of N/2 even odd nLC erasing is examined：Perform all 16KB units.

D) J pages of N/2 even odd nLC is read：The half page of 8KB units is examined at the same time.

E) ABL J page N LBL Vinh or Vdd precharge and discharge operation.

F) the first N/2 V1 precharge of J pages of even odd, followed by the 2nd J pages of even/strange N/2 V2 precharge, to mitigate LBL-LBL AC coupling effects are with the reading that assures success, inspection and programming operation, V1>V2 and preferred V1>3 × V2 and V2=Vdd.

G) N/4 pages of nLC data parallel is loaded and turned according to Vdd/Vss to the Vinh/Vss voltages of every N/4 page datas Change.

J pages of mixing line operation at the same time also includes following reliability relevant operation：

A) J pages of NAND data keep checking and refresh without or need not wipe step.

B) J pages of NAND wear levels inspection, data relocation and programming.

C) the J pages of garbage collection operations under preset strategy.

D) programming was to find programming after J pages on J selected scattered WL is read, by J selected scattered WL On write back J page reading performed before J page datas and carries out J adjacent to WL nLC data inspections to find WL-WL coupling effects.

E) it is used for J pages of nLC ABL of the SSD systems of RAID4, RAID5 or other RAID type at the same time and pipeline programs, J Page data loads and J pages of programming stand-by period has J times and reduce.

F) flexible X-WL is complete or the block of part erasing, and two border WL units are not wiped but labeled to prevent two The data of physically neighbouring nLC WL are damaged in the same block, if using 64NAND unit string schemes, X values are from minimum value 3 change to maximum 64.

Figure 1A shows the 2- in triple p-wells (TPW) in the deep N-well (DNW) in 2D NAND strings and on substrate P The cross-sectional view of Polysilicon floating gate 2D NMOS NAND cells.In the Past 30 Years of 2D NAND productions, 2D NMOS NAND cell structure is unified for a type as seen in figure 1 for all mainstream 2D NAND manufacturers.The 2D NAND cell has 6 terminal nodes, comprising N+ source nodes, N+ drain nodes, 2- polysilicon gates node, TPW nodes, DNW nodes and substrate P node.DNW nodes are formed at the layer above substrate P, and TPW nodes are formed at DNW layers of top Layer.N+ source nodes and N+ drain nodes are respectively formed in TPW layers, have separate channels area.First insulating layer, 23 overlying In channel region, poly-1 layer 22 is supported on the top.Second insulating layer 21 overlies poly-1 layer 22, and grid section is served as in support The polysilicon -2 layer 20 of point.During various NAND (programming, read, wipe or examine) operation, N+ source nodes, N+ drain electrode sections This 6 terminal nodes of point, 2- polysilicon gates node, TPW nodes, DNW nodes and substrate P node are subjected to corresponding bias voltage V_S、V_D、V_G、V_TPW、V_DNWAnd V_psub.This 2D unit represents to use in all 2D hierarchy types NAND arrays of the present invention each One NAND cell of 2D plane NAND strings.

Figure 1B is will to build 3D NAND strings and all 3D NAND cells classes of 3D hierarchy type NAND arrays by the present invention The simplification cross-sectional view of the preferred vertical raceway groove 3D NAND cell structures of type.As shown in the figure, it is the 3D in 3D cylinder strings The cross-sectional view of NMOS NAND cells, it has the block (bluk) being located in center ring and the WL grid being formed on outer shroud Pole.Based on this vertical channel structure, some 3D NAND cells structures can be produced.First, 1- polysilicon trapping charges can be formed SONOS type 3D NMOS NAND cells, its block are directly connected to the substrate P of NAND eyeglasses.The 3D NAND cells of this type make Wiped with FN tunneling schemes (identical with 2D NAND cells) with performing the block wiped for complete and partial block.Second, formed 1- polysilicon trapping charge SONOS type 3D NMOS NAND cells, its block are directly isolated from the substrate P of chip.This type 3D NAND cells are wiped scheme using GIDL and are completely wiped to perform SL sides or BL sides with partial block.3rd, 2- polycrystalline can be formed Silicon floating gate polar form 3D NMOS NAND cells, its block is directly connected to the substrate P of NAND chips, therefore can use FN tunnels Scheme is worn to perform erasing.In addition, forming 2- Polysilicon floating gate type 3D NMOS NAND cells, its block is directly isolated from The substrate P of chip, therefore scheme can be wiped using GIDL and is completely wiped to perform SL sides with partial block.

Each in the 3D NAND cells of four type has 4 terminal nodes, comprising at the inner ring of bottom N+ source nodes, the N+ drain nodes at the inner ring of top, 2 grid of polysilicon or polysilicon gate section at outer shroud Point, and the P+ type block node at center ring, respectively with 4 bias voltage V_S、V_D、V_GAnd V_BIt is associated.This V_BCan be straight The substrate P for being connected to chip in succession is wiped for performing FN tunnellings, or is isolated from substrate P for performing GIDL erasings. Between each internal vertical raceway groove ring and exterior polysilicon ring, charge storage layer is formed.There are two species to form accumulation layer, Such as 2- Polysilicon floating gate 3D NAND NMOS units or 1- polysilicon trapping charge 3D NAND NMOS units.The above two The 3D NAND cells of a species and associated 3D NAND vertical nands string are in the various 3D hierarchy types NAND arrays of the present invention Use.

In the disclosure, the inventive features for illustrating the present invention are used as using some 2D and 3D hierarchy types NAND arrays Example.Hereafter summarize main feature, while details will be further seen in the description from Fig. 2 to Figure 10, a part exists The one or more prior U.S. Patent applications being incorporated to as reference for all purposes are (for example, the 14/970th, No. 525 U.S. State's patent application) disclosed in.

Fig. 2 is the circuit of preferably 2 level hierarchical LBL/GBL 2D/3D NAND chips according to an embodiment of the invention Figure.As shown in the figure, the 2D/3D hierarchy types NAND array is included at least two neighbouring 2D/3D arranged in bit line direction NAND planes (1 10a and plane 210b of plane), are divided by two HV (20V) NMOS ISO circuits (11a and 11b), are had not Same decoder, such as the block decoder (circuit 50) with latch, LG decoders (52a and 52b), LGps decoders (54a And 54b), CSL decoders (53a and 53b) and Y-decoder (34).

Every a 2D/3D NAND planes 10a or 10b are further configured to have multiple 2D/3D HG (HG groups).It is each HG includes the 2D/3D LG (LG groups) of multiple pairings.Every LG further comprises multiple 2D/3D along bit line (BL) direction NAND block, and each piece further comprises N number of 2D/3D NAND strings, has its indivedual but connection N number of parallel low-level office Bit line LBL, N¹Parallel global bit line GBL, N of a top-level²A BLP data cables (being connected to page buffer), and preferably One common source line CSL of 2D/3D hierarchy type NAND arrays and the independent electrical line of force LGp, N²(BLP data cables)≤N¹ (GBL lines)≤N (LBL lines).Every LG includes a page of the N DCR based on LBL, and is further divided into N number of 2D/3D Multiple pieces of NAND string.Shared between each two contiguous block of CSL by each N number of 2D/3D NAND strings in the block.Optionally, LGps power lines are arranged for plane 1 and plane 2 parallel to CSL.The N positions of each selected block of every 2D/3D NAND planes Data can be via as instantaneous N²The data buffer of position temporary cache buffer is accordingly based on N in every circulation²Basis On it is bi-directionally transmitted between two neighbouring 2D/3D NAND planes.

It should be noted that in this 2D/3D NAND array, all CSL be analogous to M0 level LGps lines be arranged in it is M0 layers minimum Metal wire at level.Optionally, CSL is parallel to LGps lines, but they are perpendicular to all LBL and cloth being arranged in M1 levels Put the GBL in the M2 levels of top.In addition, two 2 λ spacing LBL of M1 levels are connected to one by LG Y-Pass1 even odd circuits A 4 λ spacing M2GBL is to save cost.The definition of 2 λ spacing M1 levels LBL implies that the 1 λ M1 levels LBL wide at bottom level Degree and 1 λ M1 level LBL spacing, and 4 λ spacing M2 levels GBL imply that the width of GBL is that W1 and GBL spacing is S1 and W1+S1=4 λ.There are many possible combinations by the W1+S1 of GBL.The two vertical 2D/3D NAND planes pass through two 20V ISO circuits point Separate, and one is attached perpendicularly to via with the 2nd ISO circuits that 20V is protected during any plane under erasing operation Share reduced DB 30.Therefore, depending on operation needs, two planes can be wiped in same time or in different time.Can be Block decoder or DB and the opposite side of static cache register (SCR) are made similar to the more of above plane 1 and plane 2 Plane.Four couples, 8 planes of above plane 1 and plane 2 can be made altogether for the 2D/3D NAND of higher density.

Since plane 2 (10b) and plane 1 (10a) are separated, exist from high, neutralization simulation LV generators (60) the independent HV power lines of two of circuit are by two independent blocks (bulk).In the true erasing operation of the present invention, Scenario described below can occur：

A) only plane 1 is under erasing operation.By the way that Verase (up to 20V) is fed to two blocks of plane 1 (10a) Body, by setting V_ISO1=V_ISO2=0V makes two 2D/3D isolation circuits ISO1 (11a) and ISO2 (11b) be maintained at disconnection shape State.

B) only plane 2 is under erasing operation.By the way that Verase to be fed to two blocks of plane 2 (10b), by setting Surely make that 2D/3D isolation circuits ISO2 (11b) is maintained at off-state and 2D/3D isolation circuits ISO1 (11a) is maintained at connection shape State.In other words, 2D/3D NAND planes 1 are connected to LV data registers or data buffer (DB) 30, and plane 2Verase It is isolated in order to avoid reaching plane 1 and damage LV DB (30) and LV static state cache register (SCR) (32).

C) plane 1 and plane 2 are under erasing operation.By the way that Verase is fed to plane 2 (10b) and plane 1 The block of (10a), 2D/3D isolation circuit ISO 11a and 11b are maintained at off-state.

It should be noted that during partial block disclosed herein is wiped, scenario described below is possible：A) only plane 2 is in part Under block erasing, the nLC data of multiple multiple barrier WL of the unselected WL in plane 2 are transmitted to the selected DCR of plane 1, in plane 2 The ISO circuits of 11a and 11b are in an ON state before upper implementation erasing operation.After the data transfer, ISO circuits 11b disconnect with Isolate the follow-up Verase in plane 2 in order to avoid reaching plane 1, LV DB and SCR for protection.B) only plane 1 is in part Under block erasing, on the contrary, the nLC data of the multiple multiple barrier WL of unselected WL in plane 1 are transmitted to the selected of plane 2 The ISO circuits of DCR, 11a and 11b carried out in plane 2 erasing before in an ON state.After a transfer, ISO circuits are disconnected 11a and 11b is so that the follow-up Verase in plane 1 isolates in order to avoid plane 2 is reached, with the nLC data and LV DB of protection storage With SCR for protection.C) plane 1 and plane 2 are under whole blocks erasing operation, are not required in the DCR of plane 1 and plane 2 Page data is stored, because impacted without border WL units.D) plane 1 and plane 2 are under partial block erasing, this still may be used Complete, but the pre-read of the border WL units of unselected erased partial block and storage can not save.In the case, select The border WL of partial block can not really be wiped by applying 0V.In fact, apply Verase/2 or Verase-5V so that depositing The nLC data being stored in two border WL of unselected partial block will be highly protected.

Peripheral circuit in 2D/3D NAND chips includes various decoders, such as block decoder (50), LG decoders (52), LGps decoders (54), CSL decoders (53) and the reduced LV DB (30) and LV SCR (32) of size.With lock The block decoder (50) of storage is coupled to HV and MHV pump generators (60) via multiple global bus's circuits 55, and is coupled to tool Be useful for selection WL, block and LG pre-decoded address information address register to allow such as Vpgm, Vpass or V_READOr The predetermined electrical bias voltages such as Verase load and are latched into selected WL, block and LG, in every 2D/3D of 10a or 10b J pages of execution nLC ABL, programming ABL programmed checks, ABL readings and ABL erasings inspection, partial block erasing at the same time in NAND planes And erasing checked operation.LV DB (30) include shared by 2 NAND planes N/4 positions, 4KB multipliers (102), N/4, 4KB program registers buffer (PRB) (106) and N/4,4KB sense amplifiers (SA) (104) and N/4 DAC groups (80)。

Each in two 2D/3D ISO circuits 11a and 11b is 20V ISO circuits, it is used in plane 1 and plane 2 Erasing operation during isolate the HV of 2D/3D NAND arrays in order to avoid damage LV DB.N/4,4KB SCR (32) are by interim storage Output and input 4KB data.I/O buffers (90) are byte-by-byte 8 I/O.State machine (70) will be controlled in normal Vdd on chip During the conventional nLC of period is operated at the same time and irregular or abnormal Vdd when when undesirable Vdd loss occurrences is operated SLC is operated.

Peripheral circuit in 2D/3D NAND chips further comprises as HV and MHV the pump generator of central HV pump circuits (60), Vpgm (20V), Verase (20V), Vpass (8 arrive 10V), the V of all NAND operation associated voltages are used for generation_READ (4 arrive 6V) and Vinh (>7V).2D/3D Y-decoders circuit (34) will 32 and 1 byte I/O buffers 90 of 8KB SCR it Between every time decoding 1 byte.2D/3D Y-pass3 circuits (33) are used to byte-by-byte I/O being connected to 4KB PRB or SCR page by page.

One notable feature of this 2D/3D hierarchy type NAND array is reduced to only N/4 of the size of DB and SCR, It is the 1/4 of a complete N WL, but still J pages of ABL nLC programmings and J pages of N/2 odd or evens reading and inspection needed for providing Test.An every N/4 DB include N/4 multipliers (102), N/4 SA (104), N/4 PRB (106) and N/4 DAC groups (80).Each multiplier is used for each the sensed analog signal for amplifying Vinh or Vss from every nLC units.It is each SA is used to each sensed analog signal being amplified to whole number signal.Every PRB is used for storage numeral after zooming Programming and reading data, and DAC groups are used to produce 2 programmed for the nLC of 2D/3D hierarchy type NAND arraysⁿ V_LBLVoltage Or 2 for the Vt compensation based on SLⁿ V_LBLVoltage, LSL and the LBL such as present invention are abreast arranged (as 2D/3D NAND strings One embodiment).

In addition, this preferred 2D/3D hierarchy types NAND array allows each to select complete or randomized part block wiping in the block Remove and random WL programming operations.Hereafter the more of every 2D/3D NAND planar circuits will be further explained in Fig. 3 A to 3G Details.

Fig. 3 A are the letters of the J 2D/3D HG group with the GBL disconnected in the 2D/3D NAND planes shown in Fig. 2 Change circuit diagram.As shown in the figure, it is to preferably include the N disconnected by J-1¹One of J 2D/3D HG (110) of GBL connections A part for general 2D/3D NAND arrays (101).Every 2D/3D HG groups include N⁶/ 2 pairs of 2D/3D LG (120) (such as A pair of of LG1 and LG2, to a pair of of LGN⁶- 1 and LGN⁶), respectively by N⁶The TIE NMOS devices connection of/2 rows.Every 2D/3D LG into One step includes being used to connect N number of LBL and N¹The 2D/3D Y-passl circuits (110) of GBL and by N¹PREo and N¹PREe grids The LG pre-charge circuits (120) of signal control, all N number of source nodes are connected to one between two neighbouring 2D/3D LG altogether With LGps lines.

The function of every 2D/3D LG (120) includes the cell capaciator C for using every LBL as 1 similar DRAM_LBL Cache register (DCR) of the N positions based on DRAM a page.Altogether formed with N in every 2D/3D NAND arrays⁶It is a N DRAM cache registers.Each cache is used to store the N of page 1/2 for N programming datas of nLC¹Position V_LBL Voltage.

Each long GBL metals are divided into J disconnection by the grid-controlled J-1GBL division row circuits (134) with DGBL GBL lines.During each read operation, N/2 or N¹N/2 or N in LBL lines¹Position even odd unit is by corresponding to SA sensings, N/2 Or N¹Even/strange metal wire in position is maintained at fixed voltage to prevent LBL-LBL AC coupling effects.

Every 2D/3D HG (150) also can be formed with being connected to N¹The common HGps lines of one of GBL lines are as every 2D/3D A HGps line in LG (120).Every 2D/3D LG (120) are further divided into H 2D/3D NAND block on LBL directions (127), H=4 in one example.All H 2D/3D blocks in every 2D/3D LG are by the N=16KB LBL (examples in M1 levels Such as LBL¹ ₁To LBL¹ _N, its formation includes such as C_LBL1To C_LBLNDeng N=16KB C_LBLThe N positions of capacitor or 2N¹The one of position DCR A page) and N in M2 levels¹The GBL connections that=8KB is disconnected, for each physics nLC 2D WL, N=2N¹=16KB. LGps and HGps lines are used to allow from locally selected LG or HG rather than from page buffer to corresponding N number of LBL lines and N1GBL Line is into line precharge, to save the power consumption of 2D/3D hierarchy type NAND arrays and multipage while reading and programming operation.

Fig. 3 B be it is according to an embodiment of the invention have every LBL be connected to the independent electrical line of force via pre-charging device The simplification figure of LG groups in the 2D/3D hierarchy type NAND arrays of LGps.This LG group of circuits include H NAND block (127) with An and special N¹Position odd number and N¹Position even number LBL precharge and discharge circuit (125), single supply of electric power by MPRo and The N of MPRe¹Position precharge and electric discharge NMOS MHV devices are connected to a 2D LGps, its common gate is coupled to PREo¹With PREe¹Two to induction signal.In this example, 2N¹Position implies that N or 16KB and H=4.

Fig. 3 C are the LG Y- according to an embodiment of the invention that GBL is connected to LBL in 2D hierarchy type NAND arrays The simplification figure of Pass circuits.In this example, every 2D LG Y-Pass1 circuits include N¹Unit 2/1, and every Unit 1 Including a pair of of odd and even number 2D NMOS devices MLGo and MLGe, so as to form two row Y-pass1N¹LV nmos pass transistors. MLGo devices make its grid be connected to LG¹O and its source electrode are connected to a M1 odd numbers LBL.MLGe devices are connected to its grid LG¹E and its source electrode are connected to another M1 even numbers LBL staggeredly.Per the N of a pair MLGo and MLGe devices¹A common drain node, Such as LBL¹1 and LBL¹2、...、LBL¹N-1 and LBL¹N, is connected to N together respectively¹A M2GBL, such as GBL1 to GBLN¹。 The loose layout spacing of M2GBL is twice of the close spacing of M1LBL, therefore GBL layouts are not related to compared with each close LBL Key.M1LBLo the and M1LBLe lines each matched are connected to a M2GBL line.

Fig. 3 D are the LG according to an embodiment of the invention that GBL is connected to LBL in 2D/3D hierarchy type NAND arrays The simplification figure of Y-Pass circuits.In this example, every 2D/3D LG Y-Pass1 circuits include the N such as MLG NMOS One page of 2D/3D devices, its grid are connected to a LG¹And N number of source node is connected to N number of M1 odd numbers LBL, such as LBL¹1、LBL¹2 arrive LBL¹N, and N number of drain node is connected to N number of M2 levels GBL, GBL1 to GBLN of the invention.Change sentence Talk about, GBL//LBL.The layout spacing of every 3D GBL is identical with every 3D LBL spacing, and there are identical layout designs to advise Then, and MHV it is defined be MHV>7V, it is defined by the BVDS of the MG and MS of string selection NMOS device.

Fig. 3 E are that GBL is connected to N/4 data bufferings in 2D hierarchy types NAND array according to an embodiment of the invention The simplification figure of the LV Y-Pass circuits for being coupled to HV ISO circuits of device.An as shown in the figure, 2D LV Y-Pass2 circuit (12) physically it is placed on the 2D TPW in the 2D DNW being formed on 2D substrate Ps with a 2D HV ISO circuit (11) 2D NAND arrays (15) and N/4 DR (not shown) between.LV Y-Pass2 circuits (12) include being formed on substrate P Two row Y-pass N/4LV 2D nmos pass transistors.Row of N/4 odd number the transistor of NMOS Mo, N/4 grid are connected to One common control signal ODD.Similarly, the row of N/4 even number transistor of NMOS Me, N/4 grid are connected to one altogether With control signal EVEN.N²=1/2N¹To the N altogether of even odd transistor MXo/MXe¹=1/2N common source node is connected to In the common GBLps supply of electric power line that M0 levels are arranged in the X direction, control gate is connected respectively to Xo and Xe.In addition, A pair of of GBL lines are connected to a BLP line by a pair of of HV ISO devices and a pair MXo and MXe LV NMOS devices.It is altogether N number of The N that M1 levels LBL passes through MI¹A ISO HV devices are connected to N¹A M2 levels GBL lines and it is connected further to N²A BLP lines, Such as BLP1 to BLPN².ISO circuits include the N of MI¹A 20V NMOS devices, its common gate are connected to an ISO1.Due to N in this example¹=N/2, therefore save N¹A 20V MI devices.

Fig. 3 F are that GBL is connected to N/2 data bufferings in 3D hierarchy types NAND array according to an embodiment of the invention The simplification figure of the LV Y-Pass circuits for being coupled to HV ISO circuits of device.As shown in the figure, LV Y-pass2 circuits are together with HV ISO Circuit is the peripheral interface circuit between 3D hierarchy types NAND array and LV page buffers together.3D HV ISO circuits herein (11) multiple N HV NMOS device MI are included, its common gate is connected to the ISO1 outside the block area for being formed at NAND array Signal.N number of individual source node of N number of MI devices is parallel-connected to N number of M1 levels GBL metal wires respectively, and (such as GBL1 is arrived GBLN).In addition, N number of drain node of N number of MI devices is divided into N/2 odd numbers group and N/2 even numbers group staggeredly, it is distinguished It is connected to LV Y-pass2 circuits.

LV Y-Pass2 circuits are the interface circuits between HV ISO circuits (11) and PB (not shown).Odd number MI devices N/2 odd drain lines are connected respectively to N/2 source node of LV odd number Mo devices and the N/2 of LV odd number MXo devices Drain node.Similarly, N/2 even drain lines of even number MI devices are connected respectively to N/2 even number of LV even number Me devices N/2 drain node of source node and LV even number MXe devices.N/2 odd number MXo and N/2 even number MXe devices are connected to and WL The common GBLps power lines of formation parallel with array CSL directions.

In addition, the common drain node of N/2 Mo device and N/2 Me device is connected to from LBL1 to BLPN¹N¹=N/ 2 BLP lines, and it is then attached to LV PB.

Fig. 3 G are two LG groups by a line HV 3D ISO circuits division for 3D hierarchy type NAND arrays of the present invention The simplified electrical circuit diagram of group.As shown in the figure, every 3D LG1/LG2 circuits (120) include a water for being connected to LGps1/LGps2 The H 3D NAND block (such as 3D BLOCK1 to 3D BLOCKH) of the ordinary telegram line of force, and by row of N/2 3D even odds MPR The PRE circuits that NMOS device is formed.All N number of drain nodes of H 3D block are connected in parallel by N number of 3D LBL respectively, such as 3D LBL in LG1¹1 arrives LBL¹N, and all N number of drain nodes of N number of HV TIE NMOS devices, N number of grid are connected to as N/2 The TIE of the common gate line of a odd number NMOS MPR devices¹²。

The every LBL line associated with LG1/LG2 forms C_LBLCapacitor, it is used for the 2V with Vdd/Vss_LBLS stores 1 Digital programming data simulates V with 4MLC_LBLS or 8TLC simulations V_LBLS stores analogue data.Each indivedual LGps lines are each A Local C being used as before read operation in every 3D LG_LBLPre-charge line.N/2 odd numbers C in LG1_LBLVoltage pre-charge is Via odd number PRE circuits, but N/2 3D odd number MPR devices its common gate is by PRE¹Signal controls.In contrast, in LG2 N/2 even numbers C_LBLVoltage pre-charge is via even number PRE circuits, but N/2 3D even number MPR devices its common gate is by PRE²Letter Number control.During each read operation, in C_LBLPRE circuits are disconnected after precharge to prevent V_LBLLeak into LGps lines.

Fig. 4 shows two 2D in a LG group of 2D hierarchy types NAND array according to an embodiment of the invention NAND block circuit.As shown in the figure, a pair of physically neighbouring 2D NAND blocks share a horizontal CSL line.Each piece includes this hair The N number of 2D NAND of connection in one of bright multiple 2D LG of each corresponding HG of this preferred hierarchy type 2D NAND array N number of low-level N LBL of string.Top-level N¹GBL metal wires are not shown.Each NAND string further comprises SSL lines, one A SLCWL, 64 WL, two illusory WL (DWL1 and DWL2), GSL and CSL line.WL in 3D NAND arrays Typical maximum number be 48, but more than 100 in 2D NAND arrays.The single SLC WL often gone here and there prepare one through pre- erasing Quick storage is from the SLC data or chip that exterior dram chip transmits when denier detects unexpected system Vdd power failures One page SLC programming datas.SLC WL are optionally interposed between SSL and DWL2, therefore its SLC programmings are not disturbed and are stored in often Advise the normal NAND cell data in WL.

Block structure shown in Fig. 4 has the most short string length associated with minimum 2D NAND strings size.In this example In, every 2D blocks include from string bottom to string top 64 WL (such as WL1 to WL64), two illusory WL, at top A SLCWL between the DWL2 and DWL1 in bottom, and the string selection SSL lines being placed on every DWL2 and top, with And a GSL line of string drain selection line is served as in X-direction or WL directions.The institute of N number of NAND string in one 2D NAND block There is N number of drain node to be connected respectively to N number of LBL (LBL1 to LBLN) in M1 levels in the Y direction or on BL directions, and it is N number of All N number of source nodes of NAND string are connected to the common CSL line arranged in M0 levels on WL directions or X-direction.This Corresponding to the situation of the 2D conventional NAND array associated with (GBL//LBL) ⊥ (CSL//LGps).

In embodiment, nLC programming and read operation preferably the present invention 2D/3D hierarchy type NAND arrays under with class Performed like ABL modes.Different from conventional ABL programmings and even odd BL programmings, so-called similar ABL programmings are a with odd number N/2 NLC is performed in a rotative pattern between unit that LBL is associated and the Liang Ge groups of the unit associated with N/2 even number LBL to change Generation programming and programmed check.In conventional N/2 even/strange programming and programmed check scheme, the programming behaviour of N/2 idol/azygos members Make only to perform after complete iteration programming and programmed check operation is completed for N/2 even odd units.This conventional even odd The defects of programming scheme, is that N/2 odd numbers or N/2 even numbers will undergo the interference of WL gate programs, because odd and even number unit Do not complete to program at the same time.But similar ABL programmings and programmed check operation under the 2D/3D hierarchy type NAND arrays of the present invention The programming on the N/2 positions odd number 2D/3D units and N/2 even number 2D/3D units in every WL can be generally completed at the same time.Into And, it can be achieved that minimum WL gate programs interference and most reliable cell data reliability.

Fig. 5 A show a part for 3D hierarchy types NAND array according to an embodiment of the invention.As shown in the figure, this 3D Formed under the framework for the NAND plane that hierarchy type NAND array Array1 is drawn in fig. 2, comprising being divided into multiple 3D LG Multiple 3D HG groups of group, it is associated with the GBL metal wires of top-level respectively via 3D GBL/LBL switches, described Switch includes by 3 signal LG, LGo and LGe controls and is coupled to LBL in lower part (centre) level via pre-charge circuit 3 3D NMOS devices of metal wire, the pre-charge circuit be configured for use in be associated to independent electrical line of force LGps it is corresponding The LBL of odd and even number numbering.Two 3D LG groups match via the device that a line TIE signals control.Every 3D LG crowds Group further includes H block, has two cross-sectional views shown in Fig. 5 A, top section shows (right with an odd number LBL Should be in odd number string) associated all devices and base section show it is associated with an even number LBL (corresponding to even number string) 3D LG groups H all devices in the block.In cross-sectional view as shown in Figure 5 A, H 3D NAND string of H block Shown by every piece of basis in a 3D NAND string, their drain node is via different string selection SSL control 3D NMOS Transistor is connected to a common intermediate level LBL line, and their source node selects GSL controls NMOS brilliant via different strings Body pipe is connected to a bottom level common source line (CSL).Every 3D NAND strings formed with a series of 3D NAND cells, its Share such as the common vertical block area of vertical stacking on (the chip) depth direction or stacking direction marked in Fig. 5 A.3D NAND cell can be made of 2- Polysilicon floating gates transistor or 1- polysilicon trapping charge transistors.Optionally, it is each NAND cell is configured to from least one of two common gates of a pair of of string selection device hanging down to quick condition GIDL hot holes in straight block area inject and are eliminated via hole-electron and perform the erasing of nLC cell datas, for 2 The SLC cell data n=1 of a threshold value Vt states, for the MLC cell data n=2 with 4 threshold value Vt states, for The TLC cell datas n=3 of 8 threshold value Vt states.

In addition, an end of every LBL is connected to each corresponding top-level GBL, institute via 3D GBL/LBL switches Stating switch is included by 3 3D NMOS devices of 3 signal LG, LGo and LGe control.Independent electrical line of force LGps is also metal Line, it is arranged in bottom level and a pair of of pre-charging device PREo and PREe by being respectively used to odd and even number string are gated.(3D LG1 groups) another end of LBL is connected to a 3D NMOS device, and its grid is connected to TIE signals for even Meet (3D LG2 groups) adjacent LBL.All non-string nmos pass transistors of 3D are preferably formed in the same of 3D string select transistors At level.All above non-string devices associated with 3D GBL/LBL switches, pre-charging device, TIE devices are formed at conduct Near the intermediate level of LBL.LGps lines 3D NAND strings GSL control string selection device below lowest hierarchical level at CSL lines Abreast arrange.

As shown in the figure, whole 3D NAND Arrayl are with (GBL//LBL) ⊥ (CSL//LGps) metal wire arrangements, GBL//LBL implies that top-level GBL lines and intermediate level LBL lines are formed parallel to.Similarly, CSL//LGps implies that bottom layer Level CSL lines and LGps lines are formed parallel to.Finally, GBL and LBL is formed perpendicular to CSL and LGps lines.Optionally, GBL and The number of LBL is formed as identical.

In a specific embodiment, this 3D NAND string includes 3D NAND cells, their block floats and directly isolates In the common substrate P of chip.The 3D NAND cells of this type using GIDL wipe scheme, and to perform, SL sides or BL sides be complete and portion Piecemeal is wiped.The erasing scheme of 1 side LBL or 1 side CSL or 2 side LBL and CSL based on GIDL can be used for wiping multiple selected 3D LG Selectivity in group is complete or part 3D NAND blocks, no matter 2- Polysilicon floating gates unit or 1- polysilicon trapping charges How is the 3D cell types of unit.

Explained below with respect to Fig. 9 A of the disclosure on 1 side under the 3D NAND Arrayl of Fig. 5 A or 2 side bases in GIDL Partial block erasing detailed description.

Embodiment (1)：1 side LBL partial blocks erasing in selected LG1 groups.With reference to figure 5A, in order to H 3D odd number string (on the top section of Fig. 5 A) and H 3D even numbers string (on base section of Fig. 5 A) perform the preferred portion of 1 side LBL GIDL erasings Piecemeal is wiped, V_LBLoAnd V_LBLeIt must be coupled into an iteration Verase voltages and connect same common Vsg voltages and be coupled to selection string All SSL signals (SSL of device¹1 arrives SSL¹H), injected hot holes into and every 3D string phases with producing GIDL effects In associated perpendicular block area.Herein, Vsg voltages are for triggering the GIDL hot holes in the perpendicular block area of quick condition Predetermined optimum voltage.Every a string of another string selection device is in 0V.In other words, bias condition includes a) V_LBLo=V_LBLe= Verase, Verase=15V to 20V.b)V_SSL11=...=V_SSL1H=Vsg.c)V_GSL11=Vss.D) CSL be set to Vdd or Vss.E) in order to perform erasing, for each selected (partial block) WL, in order to wipe the nLC of the page of cells in selected LG1 groups Data, WL voltages are set to 0V.For selecting the unselected WL in LG1 groups, WL biasings remain in floating to prevent corresponding page In nLC data NAND erasing.

Embodiment (2)：1 side CSL partial blocks erasing in selected LG1.On the contrary, in order to perform preferred partial block from CSL sides Wipe to produce GIDL effects for the erasing on the H 3D odd numbers string and even number string of array 1, only V_CSLWith an iteration A common gate V of the Verase voltages coupling together with string selection device_GSLCoupled with Vsg.Other bias conditions include V_LBLo= V_LBLe=Vdd or Vss.In order to perform erasing, for each selected (partial block) WL, in order to wipe the list in selected LG1 groups The nLC data of metapage, WL voltages are set to 0V.For select LG1 groups in unselected WL, WL biasing remain in floating to prevent Only correspond to the NAND erasings of the nLC data in page.

Embodiment (3)：2 side LBL and CSL partial block erasings in selected LG1 groups.This operation will combine above-mentioned 1 side LBL With 1 side CSL erasings so that GIDL effects can be triggered from the both sides in perpendicular block area, so that being wiped than above-mentioned 1 side GIDL Quickly perform erasing operation.Combined bias condition includes：a)V_LBLo1=V_LBLe1=V_CSL=Verase, Verase=15V are arrived 20V.B) string selection device common gate：V_SSL11=...=V_SSL1H=V_GSL11=Vsg.C) for each selected (partial block) WL, in order to wipe the nLC data of the page of cells in selected LG1 groups, WL voltages are set to 0V to wipe corresponding nLC data.It is right Unselected WL in selected LG1 groups, WL biasing remain in the NAND to float to prevent the nLC data in corresponding page and wipe.

Meanwhile for unselected 3D LG2 groups, all gate bias conditions are set as 0V to be disconnected from GBLo and GBLe. For all above example, by as follows by following grid control condition by two corresponding pre-charging devices by LBL couplings Close to independent electrical line of force LGps1 a to Verase and obtain the LBL voltages of up to Verase：V_PREo1>=Verase+Vt, will Verase is fully transmitted to LBLo1 from LGps1.V_PREe1>=Verase+Vt, Verase is fully transmitted to from LGps1 LBLe1.LGo1 and LG1 is set to 0V to prevent V_LBLo1Leak into GBLo.LGe1=LG1 is set to 0V to prevent V_LBLe1Leakage To GBLe.V_TIE12=0V is to prevent V_LBLo1Leak into V_LBLo2And prevent V_LBLe1Leak into V_LBLe2.It is old according to Fig. 9 A of the disclosure State the more detailed bias condition for controlling TIE12, PREo1, PREe1, LGo1, LGe1, LG1 and ISO signal.

Referring again to Fig. 5 A, the multiple 3D NAND strings (210) in same 3D LG (200) are connected to different SSL controls Line processed, but it is connected to identical GSL and CSL lines.Every 3D LG via made of 3D NMOS devices 3D Y-pass circuits connect To each corresponding HG, respective gates are connected to LG1, LG2, LGe and LGo signal.(BL) end of all HG is by a line 3D HV ISO devices (MIe and MIo) are connected to LV page buffers (PB) will not be applied with protecting LV PB in 2D/3D ANND arrays HV erasing voltages Verase is damaged.In this 3D hierarchy types NAND array 1, three kinds of metals altogether are used.Top metal is used for GBL The metal wire of disconnection.Intermetallic metal is used for LBL sectionalized metallic lines, and bottom metal is used to be total to perpendicular to what LBL and GBL lines were formed With CSL and LGps lines.

Fig. 5 B show a part for 3D hierarchy type NAND arrays according to another embodiment of the present invention.As shown in the figure, Formed under the framework that this 3D hierarchy type NAND array Array2 is drawn in fig. 2, multiple 3D HG group divisions into respectively with one The GBL metal wires of a level and multiple 3D LG groups for being associated of LBL metal wires in another level.Two 3D LG are via one Row TIE signals control device and match.Every 3D LG groups further comprise H block, have two horizontal strokes shown in Fig. 5 B Sectional view, top section shows all devices associated with an odd number LBL (corresponding to odd number string) and base section shows H all devices in the block of the 3D LG associated with an even number LBL (corresponding to even number string) are gone out.The institute in such as Fig. 5 A In the cross-sectional view shown, H 3D NAND string of H block is shown by every piece of basis on a string, their drain node via Different string selection SSL control 3D nmos pass transistors are connected to a common intermediate level LBL line, and their source node GSL control nmos pass transistors are selected to be connected to a bottom level common source line (CSL) via different strings.Every 3D NAND For string formed with a series of 3D NAND cells, it is shared as hung down on (the chip) depth direction or stacking direction marked in Fig. 5 B The common vertical block area directly stacked.3D NAND cells can be cut by 2- Polysilicon floating gates transistor or 1- polysilicons electric charge Transistor is stayed to be made.Optionally, each NAND cell is configured to from two common gates of a pair of of string selection device At least one perpendicular block area to quick condition in the injection of GIDL hot holes and eliminate and perform via hole-electron NLC cell datas are wiped, for the SLC cell data n=1 with 2 threshold value Vt states, for 4 threshold value Vt states MLC cell data n=2, for the TLC cell datas n=3 with 8 threshold value Vt states.

Optionally, an end of every LBL is connected to each corresponding GBL via GBL/LBL switches, and the switch includes The 1 3D NMOS device controlled by LG signals.One independent electrical line of force LGps is also metal wire, it is arranged in independent stratum Level and by be respectively used to odd and even number string a pair of of pre-charging device PREo and PREe gate with respectively with odd number LBLo and idol Number LBLe couplings.Another end of LBL is also connected to a 3D NMOS device, its grid be connected to TIE signals and with GBL/LBL switch sharing Coupling points.Whole 3D NAND arrays 2 shape optionally by placement LBL and associated 3D LG groups Into the group includes all 3D NAND strings that stacking direction is downwardly into from a direction.Include GBL/LBL switches, preliminary filling Electric installation, TIE devices, the non-string NMOS crystal of all 3D of GBL and LGps lines and block decoder (being not clearly shown in Fig. 5 B) Pipe is preferably formed from opposite direction by overturning wafer substrates, their corresponding polysilicon gate polar curve and GBL metal wires It is formed at wafer substrates.At the top-level of the 3D NAND arrays 1 of GBL metals placement in fig. 5.But in the array of Fig. 5 B In 2, LBL top-level and GBL be formed at bottom level (or wafer substrates opposite side top).Therefore LBL/GBL The associated devices and its circuit of switch can be implemented as 2D hierarchy types NAND.Independent electrical line of force LGps be generally arranged in Identical CSL level and in parallel.

Furthermore the 3D transistors in 3D NAND strings make its perpendicular block area float and are directly isolated from the common P linings of chip Bottom.The 3D NAND cells of this type are wiped scheme using GIDL and are completely wiped to perform SL sides or BL sides with partial block.It is special one Determine in embodiment, the erasing scheme of 1 side LBL or 1 side CSL or 2 side LBL and CSL based on GIDL can be used for wiping multiple selected 3D Selectivity in LG groups is complete or part 3D NAND blocks, no matter 2- Polysilicon floating gates unit or 1- polysilicons electric charge are cut Stay unit 3D cell types how.

2 times detailed offset strips for being used to perform the partial block erasing of 1 side or 2 side bases in GIDL of 3D NAND arrays of Fig. 5 B Part is generally similar to for those conditions summarized array 1 Suo Shi and in Fig. 9 B of the disclosure with the example of 1 side LBL erasings.

Fig. 5 C show a part for the 3D hierarchy type NAND arrays of still another embodiment according to the present invention.3D hierarchy types It is similarly constructed under the framework for the plane that NAND array 3 is generally drawn in fig. 2, comprising via 3D DGBL circuits stroke Be divided into multiple 3D HG groups of multiple 3D LG groups, the group respectively with the GBL metal wires of the disconnection in top-level with And the LBL metal wires in intermediate level below GBL are associated in the stacking direction.As seen in this cross sectional view, every 3D LG Further comprise the H 3D NAND strings (being belonging respectively to H block) based on BiCS, their H drain node is different via H String selection SSL 3D nmos pass transistors are connected to a common intermediate level LBL line, and H source node is via with one H string selection nmos pass transistor of common GSL controls is connected to a common source line CSL.Each 3D NAND based on BiCS String is formed as U-shaped string, and two part strings are made of a series of 3D NAND cells respectively, and the unit shares common vertical block Area is abreast arranged with stacking direction and at central bottom level by being engaged by the ST transistors of BG signal gatings.Due to U Geometric layout, two string selection device two common gates on GSL and SSL signals be located at same upper level (but still ratio LBL levels are low).CSL is arranged in below LBL but above the polysilicon lines of GSL.3D NAND cells can be by 2- poly floatings Gridistor or 1- polysilicon trapping charge transistors are made.Optionally, each NAND cell is configured to from a pair At least one of two common gates of string selection device are injected to the GIDL hot holes in the perpendicular block area of quick condition And eliminated via hole-electron and perform the erasing of nLC cell datas, for the SLC cell datas n with 2 threshold value Vt states =1, for the MLC cell data n=2 with 4 threshold value Vt states, for the TLC cell datas with 8 threshold value Vt states N=3.

In addition, an end of every LBL is connected to each corresponding top-level via 3D GBL/LBL switches, it is described to open Closing is included by 2 3D NMOS devices of 2 signal LG1 and LG12 control.Another end of LBL is connected to by a pair PREo/e controls pre-charging device and in an independent electrical line of force LGps with the EPR control devices of CSL same level gating. All non-string nmos pass transistors of 3D are preferably formed at the same level of 3D string select transistors.All 3D strings nmos pass transistors Its block is floated and be not directly connected to the common substrate P of chip.Therefore, these 3D NAND cells suffer from GIDL erasings Scheme is completely wiped with performing CSL sides or LBL sides with partial block, no matter 2- Polysilicon floating gate 3D units or 1- polysilicons it is electric Lotus retains 3D units.

Whole 3D NAND arrays 3 similarly with (GBL//LBL) ⊥ (CSL//LGps) metal wire arrangements, GBL// LBL implies that top-level GBL lines and center level LBL lines are formed parallel to.Similarly, CSL//LGps implies that bottom level CSL Line and LGps lines are formed parallel to.Finally, GBL and LBL is formed perpendicular to CSL and LGps lines.

3 times detailed offset strips for being used to perform the partial block erasing of 1 side or 2 side bases in GIDL of 3D NAND arrays of Fig. 5 C Part is generally similar to for those conditions summarized array 2 Suo Shi and in Fig. 9 C of the disclosure with the example of 1 side CSL erasings.

Fig. 5 D show a part for the 3D hierarchy type NAND arrays of another embodiment according to the present invention.3D hierarchy types NAND array 4 is substantially similar to the array 3 shown in Fig. 5 C, and multiple 3D HG group divisions (contain H into multiple 3D LG groups A similar BiCS 3D U string NAND block), the group is respectively with the GBL metal wires in level and in element stack side The LBL metal wires in another level below GBL are associated upwards.For the sake of simplicity, show only with two GBL lines The associated only a pair of 3D LG1 groups of (GBLo1 and GBLe1) and two LBL (LBLo1 and LBLe1) and 3D LG2 groups and Its relevant apparatus BiCS 3D U strings NAND block similar with H.As shown in the cross-sectional view of Fig. 5 D, every 3D LG groups are into one Step includes NAND strings (be belonging respectively to H block) of the H 3D similar to BiCS, their H drain node is via H different string selection SSL 3D nmos pass transistors are connected to a common intermediate level LBL line, and H source node is via with a common GSL H string selection nmos pass transistor of control is connected to CSL lines.Each similar BiCS strings are U-shaped strings, it is formed with curved with U-shape Two bent vertical component strings.Since U-shape is laid out, GSL the and SSL signals on two common gates of two string selection devices Positioned at same upper level (but still lower than LBL level).CSL is arranged in below LBL but above the polysilicon lines of GSL.The U The each section string of shape string includes a series of 3D NAND cells of vertical stacking in the stacking direction, has and is directly coupled to altogether Source line but still the common vertical block area for being isolated from the substrate P of chip.In being placed in by the ST transistors of BG signal gatings Between bottom level gone here and there with engaging described two parts.

The common vertical block area of each similar BiCS string is directly connected to common source line, can be offset to HV rather than Keep floating in array 1, array 2 and array 3, such as Verase, for using FN tunneling schemes to from each selected 3D LG The complete or partial block WL of each piece of selection in group performs erasing operation.3D NAND cells in similar BiCS strings can be by 2- Polysilicon floating gates transistor or 1- polysilicon trapping charge transistors are made.Optionally, each NAND cell is configured Wiped with entering the retention electronics in perpendicular block area in HV states by removing to perform nLC cell datas, for 2 thresholds The SLC cell data n=1 of value Vt states, for the MLC cell data n=2 with 4 threshold value Vt states, for 8 The TLC cell datas n=3 of threshold value Vt states.

In addition, an end of every LBL is connected to each corresponding top-level via 3D GBL/LBL switches, it is described to open Closing is included by 2 3D NMOS devices of 2 signal LG1 and LG12 control.Another end of LBL is connected to by a pair PREo/e controls pre-charging device and in the same level of CSL and an independence of the EPR control device parallel with CSL gating Power line LGps.All non-string nmos pass transistors of 3D are preferably formed at the same level of 3D string select transistors.

Show that the detailed of FN ditch track erasures of the partly or completely monoblock for array 4 biases below with respect to Fig. 9 D of the disclosure Condition.Wiped in order to which the H vertical 3D odd and even number U-shapeds strings of the LG1 to array 4 perform preferable partly or completely monoblock, only CSL is coupled to iteration Verase (being supplied from independent CSL voltage generators (not shown)), and remaining section in selected 3DU shape strings Point must keep floating to operate 3D NAND strings and array.To all strings selection common gate letter of each selected 3D LG groups Number SSL1 ..., SSLH and GSL1 ..., the control of voltage at GSLH and the LBLo1 and LBLe1 associated with this LG group System is unwanted.

Exactly, V_CSL1=Verase is applied to be used for all CSL for selecting block.Therefore, all choosings in LG1 groups The N+ source nodes and substrate P node for determining all selected 3D GSL nmos pass transistors of 3D U-shaped strings are coupled to iteration Verase Voltage (oblique ascension is until about 20V step by step).Therefore, the common block of the selected 3D units in the selected 3D U-shapeds string in LG1 groups Body area be coupled to Verase voltages by allow the erasing of preferred FN tunnellings can it is identical with 2D NAND arrays in a manner of selectively hold OK, iteration Verase voltages can be in the scope from 15V to 20V.For unselected block, all CSL keep floating.It is all LBL keeps floating to avoid gate breakdown.SSL, GSL, LGps, PRE signal all keep floating.For each selected (part Block) WL, in order to wipe the nLC data of the page of cells in selected LG1 groups, WL voltages are set to 0V to wipe corresponding nLC data. For selecting the unselected WL in LG1 groups, WL biasings remain in the NAND to float to prevent the nLC data in corresponding page and wipe Remove.It should be noted that erasing is performed by every LG bases, therefore, it can be achieved that part and complete 3D blocks are wiped while selecting in 3D LG Remove, while other operations of such as nLC programmings, programmed check and reading are performed in other LG.

Fig. 5 E show a part for the 3D hierarchy type NAND arrays of another embodiment according to the present invention.3D hierarchy types NAND array 5 is substantially similar to the array 2 shown in Fig. 5 B, and multiple 3D HG group divisions are described into multiple 3D LG groups Group respectively with the GBL metal wires in level and the LBL in another level on element stack direction below GBL Metal wire is associated.For the sake of simplicity, show only with two GBL (GBLo1 and 3D GBLe1) and two LBLs (LBLo1 and 3D LBLe1) associated a pair of of 3D LG1 groups and 3D LG2 groups and its relevant apparatus and H vertical 3D NAND blocks. As shown in the cross-sectional view of Fig. 5 D, LG1 groups are connected with LG2 groups at bottom level by TIE devices.Every 3D LG crowds Group (LG1 or LG2) further comprises H 3D vertical nands string (being belonging respectively to H block), their H drain node is via H Difference string selection SSL 3DNMOS transistors are connected to a common intermediate level LBL line, and H source node is via with one H string selection nmos pass transistor of a common GSL controls is connected to a CSL line for being also arranged in bottom level.Every 3D NAND string includes a series of 3D NAND cells stacked in the stacking direction in shared perpendicular block area, it is directly coupled to shape Into in the common source line in the substrate P of chip.GSL signal wires be located at bottom level CSL lines nearby and SSL signal wires generally It is positioned near LBL.

The common vertical block area of every 3D NAND strings is directly connected to common substrate P.Optionally, common substrate P association To every 3D NAND planes.The whole chip of 3D hierarchy type NAND arrays can include at least two 3D NAND planes, it has The corresponding substrate P that can be isolated from each other.This permission performs multiple while NAND in a selected plane independently of another plane Operation.The array 4 isolated different from all block areas with string with substrate P, present block area can be biased via common substrate P To HV, such as Verase, for complete to being selected from each piece in each selected 3D LG groups using FN tunneling schemes Or partial block WL performs erasing operation.3D NAND cells in 3D NAND strings can be by 2- Polysilicon floating gates transistor or 1- Polysilicon trapping charge transistor is made.Optionally, each NAND cell is configured to absorb and enters vertically in HV states The retention electronics in block area and perform the erasing of nLC cell datas, for the SLC cell data n=1 with 2 threshold value Vt states, For the MLC cell data n=2 with 4 threshold value Vt states, for the TLC cell datas n=with 8 threshold value Vt states 3。

In addition, an end of every LBL is connected to each corresponding top-level GBL, institute via 3D GBL/LBL switches State the 3D NMOS devices that switch includes being controlled by signal LG1.Another end of LBL is connected to be controlled by a pair of of PREo/e One independent electrical line of force LGps of pre-charging device gating.LGps lines are arranged in the same bottom level of CSL and parallel with CSL. CSL is formed in substrate P and is respectively coupled to the perpendicular block area of 3D NAND strings.

3D hierarchy types array 5 every 3D NAND strings perpendicular block area via every 3D NAND strings CSL nodes It is directly connected under conditions of the common substrate P of chip, therefore array 5 can be by being biased to Verase so as into one by substrate P Verase is coupled to block area and wipes scheme using only FN tunnellings by step.In other words, can use FN tunnellings wipe for The complete or partial block WL of the selected block such as LG1 and LG2 in multiple selected 3D LG groups is wiped, no matter 3D NAND cells It is 2- Polysilicon floating gate 3D units or 1 polysilicon trapping charge 3D units.

Show that the detailed of FN ditch track erasures of the partly or completely monoblock for array 5 biases below with respect to Fig. 9 E of the disclosure Condition.Wiped in order to which the H vertical 3D odd and even number U-shapeds strings of the LG1 to array 5 perform preferable partly or completely monoblock, CSL It is coupled to iteration Verase (being supplied from independent CSL voltage generators (not shown)), and selected 3D from the substrate P of Verase biasings Remaining node in NAND string must keep floating to operate 3D NAND strings and array.Own to each selected 3D LG groups String selection common gate signal SSL1 ..., SSLH and GSL1 ..., GSLH and the LBLo1 associated with this LG group and The control of voltage at LBLe1 is unwanted.

Exactly, for each selected (partial block) WL, in order to wipe the nLC numbers of the page of cells in selected LG1 groups According to WL voltages are set to 0V to wipe corresponding nLC data.For selecting the unselected WL in LG1 groups, WL biasings remain in floating Move to prevent the NAND of the nLC data in corresponding page from wiping.It should be noted that erasing is performed by every LG bases, therefore, it can be achieved that one Part and the erasing of complete 3D blocks while in selected 3D LG in a NAND planes, at the same it is other in another NAND planes Other operations of such as nLC programmings, programmed check and reading are performed in LG.

Fig. 6 is that according to an embodiment of the invention combined with 2D/3D hierarchy type NAND arrays has breech lock control for providing The circuit diagram of the block decoder of the global WL voltages of system.In a specific embodiment, block decoder includes latch circuit and one Partial charge pump circuit is so that SSL, WL and GSL voltage of each randomly selected set of blocks in any NAND key operations Can sequentially and it be respectively locked in its respective gates polysilicon parasitic capacitance, for performing the preferred 2D hierarchy types of the disclosure Required more masks of NAND and 3D hierarchy types NAND array (for example, above array 1 to array 5) operate at the same time.As shown in the figure, block Decoder (50 of Fig. 2) includes input XDn, it is the output of the pre decoder from address register (the 25 of Fig. 2) and can be only It is enabled when the status signal XDMBn of latch circuit is in voltage Vdd.The latch circuit include phase inverter INV4 and INV5.This latch circuit is used to determine that addressed block decoder is selected or not selected for preferred flexible part Or whole blocks erasing and erasing verification operation and it is any follow-up while/pipeline programming, read and checked operation.

In embodiments, all latch of all block decoders by global single-shot Vdd pulse signals CLA reset with Set all XDMn=Vss, and then all XDMBn=Vdd.This global single-shot pulse signal CLA can detect it is each The power-up of NAND chip or chip produce at once after enabling signal.When passing through addressed XDn and selecting block decoder, then XDn =Vdd, the single-shot pulse with ENSm=Vdd with set XDMBn=Vss come record the selection and the selected block of differentiation with not Selected block.Therefore, as XDMBn=Vss, select at least some preferably flexible for performing in all block decoders Complete or partial block erasing operation.

When CLRm signals are set to Vss and ENBm is given single-shot pulse Vdd, then XDPn=Vdd is so that PH clock energy Enough into part VHH pump circuits so that HXDn reaches high voltage VPP=Verase+Vt, so that global bus (SSLp, SLCWLp, DWL2p) gather, multiple overall situation WL line GWL (GWl1 to GWL64), the whole collection of DWL1p and the HV on GSLp Close all WL (examples in the correspondence grid that can may be respectively used in string selection line SSL, SLC WL, illusory WL, 2D/3D NAND string Such as, 64 WL for 2D NAND strings), the grid of another string selection line GSL of another illusory WL and any selected block and nothing Need voltage drop.

When receiving partial block (for example, 64WL Z in the block (=1 to 63) a WL) erasing order, Z will be sequentially received A WL addresses and be forwarded to the accordingly selected block in selected LG regardless of whether 2D or 3D NAND structures how.Those parts HV pump electricity Lu Dangwei will be disabled when being selected by corresponding states signal XDMBn=Vss.Unselected XDPn=HXDn=Vss is so that every piece 1 GSL, 1 SLCWL, 2 DWL, 64 WL and 1 SSL unselected set from corresponding global bus GSLp, SLCWLp, DWL1p, GWL1 to GWL64, DWL1p and SSLp are disconnected, and depending on whether will be each based on partial block erasing order selective erasing WL and specific WL voltages are determined to be in 0V or Verase and other values.

In one embodiment, the block decoder shown in Fig. 6 is functionally equivalent in 2D/3D block decoders and latch circuit 50th, be coupled to it is high, in, the 2D/3D NAND chips shown in the voltage provider 56 of simulation low-voltage generator 60 and Fig. 2 Address register 25 combination, be used alternately for correspondence HV, MHV or the simulation of global conductive polycrystalline silicon bus set to provide LV voltages.It can control these voltages and be delivered to the correspondences of the GSL/DWL/WL/DWL/SLCWL/SSL lines of selected block and entirely gather And its latch, the global conductive polycrystalline silicon set is then discharged for for example being compiled to alternately selected block while execution Other NAND operations such as journey, reading and inspection.For example, on by chip state machine control about 5 μ s ENBm pulses Before starting erasing operation, block decoder provides the non-self-timing voltage charge of Verase voltages to the random big of each selected block Fraction block.In addition, block decoder provides the parasitic electricity of each selected set poly2 of block during the application of Verase=20V Self-timing (Tpgm=100 μ s) voltage lockout on container line.In addition, block decoder automatically provides each selected set for every piece Self-timing (about 2.5 μ s of T electric discharges) electric discharge of the HV retained in poly2 capacitor parasitics lines.

This block decoder is provided for 1 SSL, 1 SLCWL, 2 illusory WL, Z (optionally for partial block Z=1 To 63 and for whole blocks Z=64) WL and 1 GSL lines and V_TPWAnd V_DNWAll selected set voltage latch function, with The completely random selective erasing of multiple randomly selected complete and partial blocks at the same time is allowed to save each whole blocks or partial block Power consumption in erasing operation.Between completely being wiped from partial block is not both to latch the different grid such as selected VWL=0V Pole tension, and unselected one is in floating.In a specific embodiment, if for WL same position it is each random There are identical erasing operation in selected block, then need not enable latch function.We can be used directly all GWL, DWLp, The global bus of SLCWLp, SSLp and GSLp line to drive all selected blocks at the same time.Once for WL, BWL, SSL and GSL, void If all erasing bias voltages of the selected set of WL and TPW and DNW are latched, HV pump circuits can be closed.The latch It is to be performed according to following sequence.

1) discharge, and then make Z WL, 2 illusory WL, 1 SLCWL, 1 SSL and 1 GSL of selected erasing block Each selected set collect jointly from Z GWL, the illusory WL of 2 overall situations, 1 SLCWLp, one of 1 SSLp and 1 GSLp line Signal is closed to disconnect.In other words, the WL for selecting block is initially set to the quick condition with 0V.

2) V is made_TPW=V_DNWVerase is ramped up to from 0V or increases Verase step by step.Therefore,

a)V_TPW=V_DNW=Verase.

b)V_WLS=Verase.

c)V_SSL=V_GSL=Verase.

d)V_DWLS=Verase (V_SLCWL=Verase).

In this step, all selected whole blocks or partial block will be due to V_WL=V_TPWWithout being wiped free of.

3) as follows from each corresponding bus voltage V_GWLSelected part block WL voltage of the setting for erasing：

A) the selected erasing WL of setting：V_WL=0V.

B) unselected WL is set：V_WL=Verase (floating).

C) remaining illusory WL, SSL and GSL are set as floating.

D) above WL, BWL, illusory WL, SSL and GSL are latched at the same time by being disconnected from GWL signals.

1 SSL, 64 WL, 1 SLCWL, 2 DWL and 1 GSL in all difference 2D or 3D NAND operations at the same time The operation voltages of some crucial set of local signal sequentially latched.What every a 2D or 3D inside selected block went here and there Selected WL addresses can be randomly chosen and latch together with each selected unselected signal in the block.It should be noted that will be whole In the voltage latch of a set to the polysilicon parasitic gate capacitor of each selected block is correctly periodically in each set Local grid voltage from 1 SSLp, 64 GWL, 1 SLCWLp, one of overall signal of 2 DWLp and 1 GSLp it is common After set is stablized.Hereafter summarize key operation.

1) nLC while programming operation.The local gate program voltage gathered below is the identical global electricity from corresponding set Pressure latches (common source line is set to Vdd)：

a)V_SSL=Vdd.

b)V_DWL=V_SLCWL=Vpass=~10V.

c)V_WL(selected)=iteration Vpgm.

d)V_WL(unselected)=Vpass=~10V.

e)V_GSL=Vdd.

2) nLC while programmed check and read operation.The local programmed check or reading voltage gathered below are from correspondence The identical global voltage latch of set (common source line CSL is set to Vss)：

a)V_SSL=Vdd.

b)V_DWL=V_SLCWL=Vread=~5V.

c)V_WL(selected)=iteration VRn：

I. read for SLC, a VRn.

II is read for MLC, three VRn.

III is read for TLC, seven VRn.

IV is read for XLC, 15 VRn.

d)V_WL(unselected)=Vread=~5V.

e)V_GSL=Vdd.

3) using the simultaneously erased operations of nLC of GIDL schemes (for 3D NAND from LBL sides).The local wiping gathered below Except voltage is the identical global voltage latch from corresponding set (common source line, which is in, to float)：

a)V_SSL=float on Verase

b)V_DWL=V_SLCWL=float on Verase.

c)V_WL(selected)=0V.

d)V_WL(unselected)=float on Verase.

e)V_GSL=float on Verase.

Wiped for partial block, simultaneously erased multiple selected every piece of Z WL in the block.In general, as Z routine nLC of erasing During WL, while also wipe SLCWL referred to above and the unexpected Vdd power consumptions just guarantor in the form of SLC once occurs to prepare Deposit new nLC programming datas.One SLCWL is used for a NAND block.But there is H block H SLCWL to store the nLC of more multipage Data.With V_SLCWL=0V and V_TPW=V_DWLThe bias condition selective erasing SLCWL of=Verase, it is with a string and same in the block Remaining Z WL, 2 illusory WL and two string selection SSL and GSL lines are biased in quick condition and are stored in protecting in every a string Z nLC WL in nLC data all or in part.For example, if J pages of MLC program operation is completed, then only J pages Remaining MSB programming datas will at the same time be programmed into J SLCWL in J LG.Through this specification and will especially look for below To the more detailed description on random size partial block erasing operation.

In alternative embodiments, the present invention relates to be configured for use in hold similar to above 2D hierarchy type BL NAND arrays J pages of ABL of row or similar ABL, AVtz while and pipeline nLC programming operations 3D hierarchy types BL NAND planes and array.It is similar Ground, an option of whole 3D NAND arrays are to be separated by complete physical on 3D BL or column direction by the first ISO A line of 20V circuits is at least divided into 2 vertical physical 3D planes.Every 3D planes further comprise preferred 2 level of hierarchy type It is vertical not disconnect 2 λ spacing M2 3D GBL, but 2 λ spacing M1 3D LBL nLC of the disconnection with every 3D GBL layout spacing 3D NAND arrays structure is formed with the spacing identical with each close 3D LBL persons.Every 3D NAND arrays are further divided into J bottom level 3D LG (low group group) of every 3D GBL lines on 3D GBL directions, it is respectively coupled to J M0 level metal Line LGps and J common source line CSL.Every 3D LG are further divided into H 3D NAND block.Every 3D blocks further comprise The N number of 3D strings cascaded on 3D WL or line direction, and every a string include X 3D memory cell (and optionally dummy cell), With one top a 3D string select transistor MHV MS and bottom 3D string select transistor MHV MG be connected in series, X=8,16, 24th, 32 or integer.Up to the present the number of the 3D NAND cells in every 3D NAND strings is less than in every 2D NAND strings The number of 2D NAND cells.

Optionally, in this 3D NAND array, all M0 levels CSL and M0 level LGps lines are arranged perpendicularly to own 3D M1 level LBL and 3D M2 levels GBL but parallel with WL, SSL and GSL line.An in addition, 2 λ spacing 3D M1 level LBL lines It is connected to a 2 λ spacing 3D M2 level GBL lines.

Optionally, each 3D M0 levels SL lines are by the CSL for the N number of source node for being connected to a 3D NAND block.Cause 3D M1 level LBL and 3D the M2 level GBL lines that this 3D M0 levels SL will be arranged perpendicularly in 3D NAND arrays.Substituting In 3D NAND arrays, each 3D M0 levels SL lines are to correspond to the arriving for multiple source nodes for being connected to multiple 3D NAND blocks Indivedual lines of 3D M2 level GBL and 3D M1 level LBL lines.Therefore 3D M0 levels SL be arranged perpendicularly to 3D WL, SSL and GSL lines, but it is parallel with 3D M2 level GBL lines and 3D M1 level LBL lines.By using GIDL schemes, NAND gusts of the two 3D The erasing scheme of row is identical.The two 3D NAND planes are during any plane erasing operation via being protected with 20V 2nd ISO circuits are connected to a shared DB (30).Therefore, can be in same time or in different time depending on operation needs Wipe two planes.

In a specific embodiment, this disclosure shows 2D the and 3D ranks that random size erasing operation can be directed to the present invention Laminar NAND array performs.Hereafter summarize some main features of random size erasing operation.

1) it is the whole blocks (such as S=64) with S WL or the partial block with Z WL to wipe big I, and Z becomes from 1 Change to 63.

2) number for wiping block can be one or more than one, such as W block, 1<W≤T and T are for NAND gusts of 2D Total block data in the identical TPW and DNW voltages of row or the whole NAND chip in the identical bulk voltage of 3D NAND arrays Mesh.

3) position for wiping WL is completely random in each selected part block.

4) it can be W all whole blocks or W all partial blocks, or the complete and partial block of W mixing to wipe block.

5) can simultaneously erased all selected blocks, either whole blocks or partial block.

6) triple p-well VTPWs of the grid of complete or part all WL in the block of erasing in 2D hierarchy types NAND are selected At bulk voltage VB in place or 3D hierarchy types NAND 0V is offset to relative to Verase.

7) random size erasing can iteratively be performed, i.e. iteration wipes checked operation.

8) number of selective erasing partial block can be one to J with make it ready for J pages of the WL on many random dispersions, AVtz, ABL or similar ABL while nLC programming operations.

9) for Alt-WL programming schemes, the order of nLC programmings is preferably carried out, but the number for working as erasing border WL exceedes It is unrestricted on a direction along string when 1 such as the same from string bottom to string top or vice versa.

10) physics is wiped using the FN tunneling effects of 2D/3D NAND cells with from the floating in 2D/3D NAND cells Grid or trapping charge layer remove electronics or to injection electronics, or in 3D floating grids or trapping charge layer NAND cell only Injected using hot hole.

11) the average erasing time for being used for partial block and whole blocks is about 1 to arrive 3ms.

12) border WL (BWL) is wiped for partial block together with potential WL-WL punchthrough issues and existed.In the erasing operation phase Between, about 20V is increased up step by step in TPW bases Verase, if BWL while next WL for erasing is in 0V In 20V, then accidentally the risk of erasing or WL-BWL oxide breakdowns exists.Optionally, deposited if worked as between BWL and routine WL In 20V, WL-WL oxide breakdowns will not occur, then make the gate bias of these BWL in the V for TPW_BWL=Verase phases Same HV, to prevent FN tunneling effects from occurring on those BWL.Optionally, pair unit associated with BWL performs and pre-reads extract operation With the nLC data retrieved first, and nLC data are programmed into the friendship isolated with the current plane with independent TPW/DNW substrates Can be with WL for the replacement in plane, or it is saved into the outer Flash controller of chip.Later can be to the current of current plane Partial block erasing operation reloads back nLC data after completing.

Random partial block or the whole blocks erasing of 3D NAND is substantially the same with 2D NAND, and only some bias conditions are not Together.The bias condition of this partial block erasing is that 2D hierarchy types array is performed based on the exemplary 2D blocks shown in Fig. 4, (GBL//LBL) scheme is perpendicular to (CSL//LGps) line.Each erasing WL erasings are relative to V with its grid_TPW=V_DNW= Verase or the Verase being stepped up are connected to 0V and perform.

J pages of nLC can be performed to the random size erasing operation of all situations to program at the same time, can be from J in every HG The partial block or whole blocks of LG is randomly chosen J erasing WL.The position of J J in the block selected WL in J difference LG can It is well-known to reduce for realizing the required highest flexibility of selective erasing and stochastic programming to be identical or different Programming amplification and the stress for even wiping amplification.

Fig. 7 A to 7F are the random size portions in the 2D hierarchy type NAND arrays according to an embodiment of the invention for Fig. 4 The circuit diagram of the sets of bias conditions of the various different situations of piecemeal erasing operation.Random size partial block erasing operation can also Performed with substantially similar mode in other 2D hierarchy types NAND array structures, and corresponding description is not repeated here.

Fig. 7 A are shown to be used for for two 2D NAND blocks only with 1 BWL (side in the WL of selection S=64- (K+1) number Boundary WL) WLK+1 be used in the case of being wiped random partial block erasing operation WL bias conditions set, the value of S pass through with Machine is defined as S=64- (K+1).As S=64, imply that whole blocks are wiped, otherwise referred to as partial block is wiped.Hereafter summarize this feelings The erasing feature and bias condition of condition.

1) the random selected part block erasing size of one of nLC WL is 64- (K+1) a WL.V_WLK+2=...=V_WL64If Determine into 0V and be latched the selected WL for from number K+2 to number 64.2) it is used as an option, 1 SLCWL and 1 DWL2 is also wiped free of, V_SLCWL=0V, V_DWL2=0V.3) the random unselected partial block erasing size of one of nLC WL is K+1 WL.V herein_WL1=...=V_WLKIt is set to Verase and is latched.Border WLK+1 is still set to Verase, but may need pre- Read and then be programmed so that corresponding page data is saved in Flash controller outside substitutive patterns or chip.4) for each iteration Step is wiped, wipes a WL of all selected 64- (K+1), 1 DWL2 and 1 SLCWL, and forbids wiping WL1 to WLK+1 at the same time. 5) for Alt-WL programming schemes, guide is wiped according to partial block, is preferably carried out the order but in one direction of nLC programmings It is unrestricted, such as from WLK+2 to WL64.6)V_TPW=V_DNW=Verase increases step by step.

Due to erasing operation, the SLC data in nLC data and SLCWL and DWL2 in WLK+2 to WL64 will be wiped Remove, to be arrived 1 in the 3ms erasing times with such as Vtemax<- 2V makes its Vt state be changed into Vte to bear state.In BWL (WLK+1) Data may due to V_TPW=V_DNW=Verase compares reduced V_BWLIt is and impacted.In order to preserve the number in BWL units According to, be first carried out read operation and based on same chip by read data be programmed into another plane with independent p-well/N traps WL in, or Flash controller can be saved in outside chip before erasing operation and in current portions block erasing operation and further part Block erasing checked operation reprograms the BWL returned in this plane after completing.

Fig. 7 B show that the WL for being used for another random partial block erasing operation in the case of 2 BWL of lower section explaination is inclined Put the set of condition.Hereafter summarize the erasing feature and bias condition of this situation.

1) the random selected part block erasing size of one of nLC WL is 4 WL, V from WLK to WLK+3_WLK=V_WLK+1= V_WLK+2=V_WLK+3It is set to 0V and latch.

2) option is used as, also with V_SLCWL=0V and V_DWL2=0V wipes 1 SLCWL and 1 DWL2 and latch.

3) the random unselected partial block of two of nLC WL wipe big I for a) comprising BWL WLK-1 slave WL1 to The unselected partial block in bottom of the K-1 WL of WLK-1.V_WL1=...=V_WLK-1It is set to Verase；B) the unselected part in top Block includes all WL, border WLK+4V from WLK+4 to WL64_WLK+4=V_WLK+5=...=V_WL64It is set to Verase and latch.

4) step is wiped for each iteration, wipes four selected WL (WLK to WLK+3), 1 DWL2 and 1 SLCWL, And forbid wiping remaining 60 nLC WL at the same time.

5) for Alt-WL programming schemes, guide is wiped according to partial block, is preferably carried out the order of nLC programmings but one It is unrestricted on a string direction, such as from WLK to WLK+3.

6)V_TPW=V_DNW=Verase is the value being stepped up.

, will be in 1 to the 3ms erasing times with Vtemax due to erasing operation<- 2V is by the nLC data in WLK to WLK+3 And the SLC data in SLCWL are erased to Vte and bear state.

Fig. 7 C show the WL biasings for being used for the erasing of another random partial block in the case of 1 BWL as explained below The set of condition.Hereafter summarize the erasing feature and bias condition of this situation：

1) the random selected part block erasing size of one of the nLC WL=K+1 from WL1 to WLK+1, V_WLK1=...= V_WLK+1It is set to 0V and latch.

2) option is used as, also with V_SLCWL=0V and latch V_DWL1=0V wipes 1 SLCWL and 1 DWL1 and latch.

3) the random unselected partial block erasing size of one of nLC WL.A) it is unselected for the top of WLK+2 to WL64 Partial block, V_WLK+2=...=V_WL64It is set to Verase and latch.

4) K+1 selected WL (WL1 to WLK+1), 1 DWL1 and 1 SLCWL are wiped, and forbid wiping remaining 64- at the same time (K+1) a nLC WL.

5) for Alt-WL programming schemes, guide is wiped according to partial block, is preferably carried out the order of nLC programmings but one It is unrestricted on a string direction, such as from WL1 to WLK+1.

6)V_TPW=V_DNW=Verase, the Verase being stepped up.

, will be with Vtemax due to erasing operation<- 2V is by the nLC data in WL1 to WLK+1 and SLCWL and DWL1 SLC data are erased to Vte and bear state.

Fig. 7 D show the collection for the WL bias conditions for being used for two random partial block erasing operations in the case of 3 BWL Close.Hereafter summarize the erasing feature and bias condition of this situation.

1) the first of 2 WL (WLK and WLK+1) the random selected part block erasing size, V_WLK=V_WLK+1It is set to 0V and lock Deposit.

2) same in the block the second of the erasing size of 64- (K+3) a WL from WLK+4 to WL64 selectes portion at random Piecemeal, V_WLK+ 4=...=V_WL64It is set to 0V and latch.

3) option is used as, also with V_SLCWL=0V and V_DWL2=0V wipes 1 SLCWL and 1 DWL2 and latch.

4) the random unselected partial block erasing size of two of nLC WL, a) the 2 unselected partial blocks in top：WLK+2 and WLK+3 is border WL, V_WLK+2=V_WLK+3It is set to Verase and latch；B) the unselected partial blocks of bottom K-1：WL1 and WLK- 1, V_WL1=...=V_WLK-1It is set to Verase and latch.

5) nLC WL altogether, 1 DWL2 and 1 SLCWL of WLK, WLK+1 and WLK+4 to WL64 are wiped, and is prohibited at the same time Only wipe remaining nLC WL.

6) for Alt-WL programming schemes, guide is wiped according to partial block, is preferably carried out the order of nLC programmings but one It is unrestricted on a direction, such as from WLK to WLK+1 and WLK+4 to WL64.

7)V_TPW=V_DNW=Verase increases step by step.

Fig. 7 E show the WL bias conditions that are used for two random partial block erasing operations in the case of only 2 BWL Set.Hereafter summarize the erasing feature and bias condition of this situation.

1) the first of K-1 WL (WL1 and WLK-1) the random selected part block erasing size, V_WL1=...=V_WLK-1Setting Into 0V and latch.

2) there is the same second random selected part block in the block of the erasing size from WLK+4 to WL64, V_WLK+4=... =V_WL64It is set to 0V and latch.

3) option is used as, also with V_SLCWL=0V (L.=latches), V_DWL1=0V (L.=latches) and V_DWL2=0V (locks Deposit) 1 SLCWL of erasing, 1 DWLl and 1 DWL2.

4) the random unselected partial block erasing size of one of nLC WL, has middle unselected partial block：From WLK to 4 WL, V of WLK+3_WLK=V_WLK+3It is set to Verase and latch.

5) nLC WL altogether, 1 DWL2,1 DWL1 and 1 SLCWL of WL1 to WLK-1 and WLK+4 to WL64 is wiped, And forbid wiping remaining nLC WL at the same time.

6) for Alt-WL programming schemes, guide is wiped according to partial block, is preferably carried out the order of nLC programmings but one It is unrestricted on a direction, such as from WL1 to WLK-1 and WLK+4 to WL64.

7)V_TPW=V_DNW=Verase is Verase progressively.

Fig. 7 F show that being used for two random partial blocks in the case where every partial block 1WL is wiped but has 4 BWL wipes The set of the WL bias conditions of operation.Hereafter summarize the erasing feature and bias condition of this situation.

1) the first of 1 WL (for WLK) the random selected part block erasing size, V_WLK=0V (latch).

2) there is the same second random selected part block in the block of 1WL erasing sizes WLK+3, V_WLK+3=0V (latch).

3) option is used as, also with V_SLCWL=0V (latch) wipes 1 SLCWL.

4) 4 BWL：BWL1=WLK-1, BWL2=WLK+1, BWL3=WLK+2 and BWL4=WLK+4, each setting Into V_BWL=Verase.

5) nLC WL and 1 SLCWL altogether of WLK and WLK+3 is wiped, and forbids wiping remaining nLC WL at the same time.

6) compiled for Alt- programming schemes, this situation due to the single WL minimum erasing sizes wiped without performing Alt-WL Journey.In the case, it can be necessary that WLK+1 and WLK-1nLC, which is examined, to ensure before 1WL erasings and afterwards without nLC data Mistake.

Optionally, the case above of partial block or whole blocks erasing operation needs to set V_SSL=V_GSL=Verase (and lock Deposit) to avoid the oxide breakdown of the MS and MG devices in each NAND string, either 2D or 3D NAND blocks.

Optionally, all above bias conditions of Verase of the invention (latch) imply that unselected WL, SSL, GSL and Verase voltages on DWL are not as art methods from V_TPW=Verase is coupled.In fact, for each unselected The every Verase (latch) for determining WL or SSL and GSL lines is with V_GWLThe each corresponding global buses of=Verase from block decoder GWL is directly set.

Optionally, all above bias conditions of Verase of the invention (floating) are implied that works as art methods Verase voltages are from V when it from GWL by disconnecting initially to float_TPW=Verase is coupled.

Fig. 8 shows the preferred of the just bias condition according to an embodiment of the invention for 2D hierarchy type NAND arrays Random size partial block erasing operation.In general, all programming operations perform the block for aligning erasing first.In other words, The typical sequence of NAND operations is that erasing operation is first carried out, and second performs programming operation, and the 3rd performs erasing at the same time, compiles Journey and read operation.Illustrate for the example for 2D hierarchy type NAND arrays, be used for the 5 of selected and unselected cells by setting The HXD control signals that the following bias condition of a terminal and use are produced by X-decoder (block decoder) are used to control various Application of the voltage signal to the selected WL of selected block, to perform random size partial block erasing operation.These bias conditions with Defined in 3 circulations of T0, T1 and T2 of this partial block erasing operation.Least random block size is a WL.

First, V is set_TPW=Verase, V_DNW=Verase, and Vpsub=0V.At T0 circulations, by bias voltage V_G (V_WL) gate node is put on, by V_D/V_SPut on drain/source node, and by V_HXDPut on the X-decoder on all pieces Control node.For selecting selected WL in the block：Originally V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL= Verase (GWL is the correspondence Overall word line from the X-decoder for being linked to corresponding WL), V_HXD=0V.For selecting in the block 1 A or 2 border WL (unselected WL)：V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL=Verase, V_HXD= 0V.For selecting non-border WL in the block and unselected unselected WL in the block：V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL=Verase, V_HXD=0V.Optionally, the data of border WL before erasing and afterwards must on chip Stored in different TPW/DNW or outside chip, for checking bit-errors caused by possible erasing.Optionally, such as fruit part Erasing block includes WL1 or WL64, then only exists a border WL.Otherwise, there are two border WL.

Circulated in T1, every time to a selected block enforcement division piecemeal erasing operation.For selecting selected WL in the block：V_G= 0V, V_D/V_S=FL (Verase), V_GWL=0V, V_HXD=VPP, VPP=Verase+Vt.For selecting 1 or 2 border in the block WL：V_G=Verase, V_D/V_S=FL (Verase), V_GWL=Verase, V_HXD=VPP, VPP=Verase+Vt.For selecting block In non-border WL (unselected WL)：V_G=Verase, V_D/V_S=FL (Verase), V_GWL=Verase, V_HXD=VPP.It is right In unselected unselected WL in the block：V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL=0V or Verase, and V_HXD=0V.

Circulated in T2, every time to a selected block enforcement division piecemeal erasing operation.For selecting selected WL in the block：V_G= FL (0V), V_D/V_S=FL (Verase), V_GWL=0V, V_HXD=0V.For selecting 1 or 2 border WL in the block：V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL=Verase, V_HXD=0V.It is (unselected for selecting non-border WL in the block WL)：V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL=Verase, V_HXD=0V.For unselected in the block unselected Fixed WL：V_G=FL (Verase), V_D/V_S=FL (Verase), V_GWL=0V or Verase, and V_HXD=0V.

Fig. 9 A show that the 3D hierarchy types NAND array execution being used for Fig. 5 A of the disclosure is complete or partial block erasing is grasped The set of the bias condition of work.3D hierarchy types NAND array is used as the example for being used to illustrate the erasing operation of the present invention.3D stratum All memory cells in formula NAND array are optionally formed or optionally with 3D floating grid lists with 3D vertical nands unit Member is formed.As illustrated in figure 9 a, as an example, bias condition is specified to be used for the 3D NAND cells using GIDL erasing schemes, No matter the 3D NAND cells are 2- Polysilicon floating gates transistor types or 1- polysilicon trapping charge transistor-likes Type, the perpendicular block area of unit isolate different operating while to allow between different 3D LG from the substrate P of chip.

This erasing operation is divided into 3 operational phases, is, for example, preparation stage, charging stage and wiping by preferred sequence order Except the stage, have corresponding bias condition with 3D hierarchy type NAND array combination control signals, such as V_GBL、V_ISO、V_CSL、V_LGo、 V_LGe、V_LBLo、V_LBLe、V_PREo、V_PREe、V_LGps, and common string selection signal V_SSL、V_GSLWith source electrode line signal V_SL.Hereafter summarize The details that bias condition for each stage is set.

1) preparation stage：This is the first step of erasing operation.It will partly drive LBL with selected 3D from LGps lines By V in LG_LSLS increases to Vsg, and Vsg is the optimum voltage for causing GIDL effects.This is the unilateral erasing for 3D strings Example, GIDL holes are produced from the LBL drain sides for erasing, and CSL sides are biased off to prevent the leakage from LBL. Optionally, the unilateral erasing from CSL sides can also be used under same an array 1.Optionally, bilateral GIDL erasings are in same an array 1 It is lower to be applicable in.Similarly, V is prevented always according to the 3D NAND array circuits of the present invention_LSLCharge leakage is to GBL.Therefore, bias condition Comprising：a)V_GBL=float, V_ISO=Vpass~10V；B) for selecting the selected block V in 3D LG_CSL=float and for unselected Determine block V_CSL=0V, and V in unselected 3D LG_CSL=0V；c)V_LG=0V and V_LGo/e=0V；D) for selecting 3D LG, V_LBLo/e Vsg is increased to from 0V, and for unselected 3D LG, V_LBLo/eIt is set to and floats on 0V.

Different from the prior art, there is no divided LBL lines and every BL to be shared by selected and unselected erasing block, is made Obtain and only select whole blocks for all being wiped with Vb1=Verase.In an embodiment of the present invention, LBL is through being separated into Selected LBL and unselected LBL.Therefore, any random selected and unselected piece of BL voltages any value can from it is each Any part LGps lines that 3D LG are associated independently are assigned.Therefore, Verase power consumption significantly decreases.

Bias condition further includes：E) for selecting 3D LG by V_PREo/eIt is set as Vsg+Vt and for unselected 3D LG sets it to 0V；F) for selecting 3D LG by V_LGpsIt is set as Verase and is set it to for unselected 3D LG 0V；G) for selecting 3D LG by the V of the first common gate of the string selection device for selecting block_SSLVsg is increased to, but will be used In unselected piece of V_SSLIt is set to and floats in selected and unselected 3D LG；H) it is used for the second of string selection device for selecting block The V of common gate_GSLIt is Vdd for selected 3D LG, but for unselected piece of V_GSLIt is set in selected and unselected 3D LG Middle floating；I) in this preparation stage for all WL by V_WLIt is set to floating.

Optionally, the preparation stage mainly prepare GBL, LBL, CSL and LGps control signal/voltage to select and not The drain node of the 3D strings of selected person or the source node of 3D strings.

2) charging stage：First, can be by reaching highest Verase voltages from initial Vsg rises in each iterative step (about 20V).LGps lines are selected from those rather than are put on Verase from GBL all selected complete or partial block all Local N number of LBL.Second, all WL are maintained at quick condition to avoid accidental erasing during this Verase ramp-up phase.Mostly A signal/voltage (being included in the voltage at the first and second common gates of string selection device) does not change from pre-charging stage, Except following voltage：A) for selecting 3D LG by V_LBLo/eVerase is increased to from Vsg and for unselected 3D LG by V_LBLo/e It is set to floating；B) for selecting 3D LG by V_PREo/eBe increased to Verase+Vt from Vsg+Vt with allow from corresponding LGps lines to The Verase of selected LBL completely by and for unselected 3D LG by V_PREo/eIt is set to 0V；C) for selecting 3D LG, V_LGps=Verase, and for unselected 3D LG, V_LGps=0V.

3) stage is wiped：In this stage, only WL bias voltages change as follows：A) for the choosing of the selected LG for erasing Those selected WL of block are determined, by V_WLS pulls down to 0V from floating；B) for unselected piece of the unselected 3D LG for erasing Those unselected WL, V_WLS keeps floating on Verase.

Optionally, in order to perform the WL of random selected number, each indivedual blocks in complete or partial block selected at random The latch of decoder be used to loading and latch S WL of each random selected block, 2 illusory WL, 1 SLCWL, 1 SSL and One set of 1 GSL line.Safely load and latch these WL voltages.It should be noted that the collection of the bias voltage in this table is suitable Erasing behaviour is performed for each type in five types of the 3D NAND arrays of the array 1 shown in Fig. 5 A to the disclosure Make.

Fig. 9 B show that the 3D hierarchy types NAND array execution being used for Fig. 5 B of the disclosure is complete or partial block erasing is grasped The set of the bias condition of work.Exactly, being integrated on 3D hierarchy type NAND array 3D arrays 2 for bias condition is applicable in.Make For an example, following bias condition is specified only for the 3D NAND cells using GIDL erasing schemes, no matter 3D NAND cells 2- Polysilicon floating gates transistor types or 1- polysilicon trapping charge transistor types, the perpendicular block area of unit with The substrate P of chip isolates different operating while to allow between different 3D LG.Also, array 2 passes through via upside-down mounting substrate process It is different from array 1 in common source line its GBL formed below and associated peripheral circuits.

The erasing operation of 3D hierarchy type NAND arrays is also included similar to the operation shown in Fig. 9 A in order 3 stages：Preparation stage, charging stage and erasing stage.It is optionally expansible, and additional bias condition is set to produce Verase to CSL lines are wiped for performing the bilateral of each selected 3D NAND strings.In other words, leaked during the erasing stage Pole and source side are used to produce GIDL hot holes, therefore realize faster erasing operation.Following bias condition is only used for 1 side LBL GIDL are wiped.

1) preparation stage：First step be from LGps lines locally driving LBL with selected 3D LG by V_LBLS increases to Vsg.Similarly, V is prevented always according to the 3D NAND array circuits of the present invention_LBLLeak into GBL.Preparation stage bias condition bag Contain：a)V_GBL=Float, V_ISO=Vpass；B) V in selected 3D LG_CSL(selected) be in is floated, and in unselected 3D LG V_CSL(unselected) is set to 0V；C) for selected and unselected 3D LG, V_LG=0V；C) for selecting LG by V_LBLo/eFrom Vss liters Height arrives Vsg, and for unselected LG by V_LBLo/eIt is set to and floats on 0V.LBL lines are separated with selected person and unselected person.Therefore, Any random selected any value with unselected piece of BL voltages can be from any part V_LGpsIndependently assign.Therefore, Verase Power consumption significantly decreases.

Preparation stage bias condition further includes：E) for selecting LG by V_PREo/eIt is increased to Vsg+Vt or for unselected Determine LG and hold it in 0V；F) for selecting LG by V_LGpsIt is set to Verase and is set into 0V for unselected LG；g) For selecting LG by the V of the first common gate of the string selection device for selecting block_SSLVsg is increased to, but for unselected piece V_SSLKeep floating in selected and unselected LG；H) be used to select the string selection device of block and unselected piece second is common The V of grid_GSLIt is set to floating；I) in the preparation stage for all WL by V_WLIt is set to floating.

Optionally, the preparation stage mainly prepare GBL, LBL, CSL and LGps control signal and voltage to selecting and The drain node of the 3D strings of unselected person or the source node of 3D strings.

2) charging stage：In this step, first each iterative step by Verase voltages from initial Vsg raise until Highest Verase about 20V.LGps lines are selected from those, and Verase is put on into all selected complete or partial block all offices The N number of LBL in portion (and being also optionally applied to CSL).Second, during this Verase ramp-up phase all WL be maintained at floating with Avoid accidentally wiping.Big multiple signal/voltages do not change from the preparation stage, except following voltage：A) for selecting LG by V_LBLo/e Verase is increased to from Vsg and is maintained at floating for unselected LG；B) for selecting LG by V_PREo/eIt is increased to from Vsg+Vt Verase+Vt with allow Verase from LGps lines to selected LBL completely by and for unselected LG, V_PREo/e=0V；c) V is kept for selected LG_LGps=Verase, and keep VLGps=0V for unselected LG.

3) stage is wiped：In this stage, WL voltages are only changed after the charging stage as follows again：A) for for wiping Selected LG selected block those selected WL, by V_WLS pulls down to 0V from floating；B) for the unselected LG for erasing not Those unselected WL, V of selected block_WLS keeps floating on Verase.

Fig. 9 C show that the 3D hierarchy types NAND array execution being used for Fig. 5 C of the disclosure is complete or partial block erasing is grasped The set of the bias condition of work.Exactly, being integrated on 3D hierarchy type NAND array 3D arrays 3 for bias condition is applicable in.Make For an example, following bias condition is specified only for the 3D NAND cells using GIDL erasing schemes, no matter 3D NAND cells 2- Polysilicon floating gates transistor types or 1- polysilicon trapping charge transistor types, the perpendicular block area of unit with The substrate P of chip isolates different operating while to allow between different 3D LG.But array 3 passes through with the U-shaped string based on BiCS Replace simple vertical string and be different from array 1, the GBL and associated peripheral circuits of the array 3 are still arranged in top as array 1 Portion's level.

The erasing operation of 3D hierarchy type NAND arrays is also included similar to the operation shown in Fig. 9 A in order 3 stages：Preparation stage, charging stage and erasing stage, but it is to be wiped from 1 side GIDL caused by the LBL sides of 3D NAND strings Remove.It is optionally expansible, and additional bias condition is set to produce Verase to LBL for performing each selected 3D The bilateral erasing of NAND string.In other words, drain electrode and source side are used to produce GIDL hot holes during the erasing stage, therefore Realize faster erasing operation.Following bias condition is only used for 1 side CSL GIDL erasings.Array 3 is using U-shape based on BiCS 3D NAND strings, bottom junction transistor by BG signal gatings.

1) preparation stage：First step is that the CSL lines of the selected block in selected 3D LG are driven by local driver with from 0V Increase to Vsg voltages (for causing GIDL effects to be optimal in the block area of 3D NAND strings.Similarly, always according to this hair Bright 3D NAND array circuits prevent LBL from leaking into GBL.Preparation stage bias condition includes：a)V_GBL=float, V_EPR=0V, V_BG=float；B) by V in selected 3D LG_CSL(selected) is increased to Vsg from 0v, and by V in unselected 3D LG_CSLIt is (unselected It is fixed) it is set to 0V；C) for selected and unselected 3D LG, V_LG=0V；D) for selected and unselected 3D LG by V_LBLo/eSetting Into floating；E) for selected and unselected 3D LG, V_PREo/e=0V, LGps line are set to 0V；F) for selected and unselected 3D LG, the V of the first common gate of the string selection device for selecting block_SSLIt is to float；G) for selected block selection device will be gone here and there The second common gate V_GSLVsg is increased to from 0V, and then keeps floating for unselected piece；H) in the preparation stage for All WL are by V_WLIt is set to floating.

2) charging stage：In this step, first in each iterative step by V_CSLVoltage is raised until highest from Vsg Verase about 20V.Second, all WL are maintained at floating to avoid accidental erasing during this Verase ramp-up phase.It is big multiple Signal/voltage does not change from the preparation stage.

3) stage is wiped：In this stage, WL voltages are only changed after the charging stage as follows again：A) for for wiping Selected LG selected block those selected WL, by V_WLS pulls down to 0V from floating；B) for the unselected LG for erasing not Those unselected WL, V of selected block_WLS keeps floating on Verase.

Fig. 9 D show that the 3D hierarchy types NAND array execution being used for Fig. 5 D of the disclosure is complete or partial block erasing is grasped The set of the bias condition of work.Exactly, being integrated on 3D hierarchy type NAND array 3D arrays 4 for bias condition is applicable in.Make For an example, following bias condition is specified for the 3D NAND cells using FN tunnellings erasing scheme, no matter the 3D NAND Unit is 2- Polysilicon floating gates transistor types or 1- polysilicon trapping charge transistor types.But array 4 is by carrying It is different from array 3 for the 3D NAND strings of similar BiCS, its perpendicular block area is directly connected to common source line but still and chip Substrate P isolate different operating while to allow between different 3D LG.

The erasing operation of 3D hierarchy type NAND arrays is also included similar to the operation shown in Fig. 9 C in order 3 stages：Preparation stage, charging stage and erasing stage, but employ FN tunnellings erasing scheme.Array 4 is using U-shape The 3D NAND strings of similar BiCS, bottom junction transistor by BG signal gatings, and additional circuit is used to CSL being connected to The perpendicular block area shared by every 3D NAND strings.

1) preparation stage：First step is that the CSL lines of the selected block in selected 3D LG are driven by local driver with from 0V Increase to predetermined Verl voltages (for causing FN tunneling effects to be optimal in perpendicular block area).Similarly, always according to this The 3D NAND array circuits of invention prevent LBL from leaking into GBL.Preparation stage bias condition includes：a)V_GBL=float, V_EPR= 0V, V_BG=float；B) by V in selected 3D LG_CSL(selected) is increased to Verl from 0v, and by V in unselected 3D LG_CSL (unselected) is set to 0V；C) for selected and unselected 3D LG, V_LG=0V；D) will for selected and unselected 3D LG V_LBLo/eIt is set to floating；E) for selected and unselected 3D LG, V_PREo/e=0V, LGps line are set to 0V；F) for selected and Unselected 3D LG, the V of the first common gate of the string selection device for selecting block_SSLIt is to float；G) will for selected block The V of second common gate of string selection device_GSLIt is set to 0V, and then keeps floating for unselected piece；H) in the preparation stage For all WL by V_WLIt is set to 0V.

2) charging stage：In this step, first in each iterative step by V_CSLVoltage is raised until highest from Ver1 Verase about 20V.Second, select and be maintained at 0V for the WL of erasing, and unselected WL is increased to floating from 0V.It is big a number of other Signal/voltage not from the preparation stage change, but for select block by for go here and there selection device the second common gate V_GSLFrom 0V It is increased to floating.

3) stage is wiped：In this stage, all bias conditions for all grids control remain unchanged, for via FN tunneling schemes select WL to those and perform the erasing of complete or partial block.

Fig. 9 E show that the 3D hierarchy types NAND array execution being used for Fig. 5 E of the disclosure is complete or partial block erasing is grasped The set of the bias condition of work.Exactly, being integrated on 3D hierarchy type NAND array 3D arrays 5 for bias condition is applicable in.Make For an example, following bias condition is specified for the 3D NAND cells using FN tunnellings erasing scheme, no matter the 3D NAND Unit is 2- Polysilicon floating gates transistor types or 1- polysilicon trapping charge transistor types.But array 5 is by carrying It is different from array 4 for straight vertical 3D NAND strings, its perpendicular block area is directly connected to be formed to be made by single NAND planes Common source line in common substrate P.Array 5 is formed with least two NAND planes with independent substrate P to allow Different operating while between Different Plane.

The erasing operation of 3D hierarchy type NAND arrays is also included similar to the operation shown in Fig. 9 C in order 3 stages：Preparation stage, charging stage and erasing stage, but FN tunnellings erasing scheme is employed with from the choosing of selected 3D LG The fixed selected plane in the block containing the selected WL for being useful for erasing connects substrate P by iteratively being biased rise The charged electrical for entering perpendicular block area in floating grid or charge trap is removed to Verase.

1) preparation stage：First step is to drive the selected plane containing selected block in selected 3D LG by local driver Substrate P to increase to predetermined Ver1 voltages from 0V (for causing FN tunneling effects to be optimal in perpendicular block area).It is right In unselected plane, substrate P bias voltage is maintained at 0V.Similarly, prevented always according to the 3D NAND array circuits of the present invention LBL leaks into GBL.Preparation stage bias condition includes：a)V_GSL=float, V_TIE=float；b)V_CSLIt is (selected) in float with It is used to select 3D LG and unselected 3D LG together with substrate P biasing；C) for selected and unselected 3D LG, V_LG=float； D) for selected and unselected 3D LG by V_LBLo/eIt is set to floating；E) for selected and unselected 3D LG, V_PREo/e=float, LGps lines are set to floating；F) for selected and unselected 3D LG, the first common gate of the string selection device for selecting block V_SSLFloat；G) for selecting block by the V of the second common gate of string selection device_GSLIt is set to 0V, and for unselected piece Then keep floating；H) for selecting all WL in 3D LG (selected block or unselected piece) by V in the preparation stage_WLIt is set to 0V and it is set to floating for all WL in unselected 3D LG.

2) charging stage：In this step, substrate P voltage is raised until highest from Ver1 in each iterative step first Verase about 20V, it also couples other grid voltages.Second, selection is maintained at 0V for the WL wiped, and in selected 3D LG Unselected WL be increased to floating from 0V.Big multiple other signals/voltages do not change from the preparation stage, but will be used for selected block In the V of the second common gate of string selection device_GSLFloating is increased to from 0V.

3) stage is wiped：In this stage, all bias conditions for all grids control remain unchanged, for via FN tunneling schemes select WL to those and perform the erasing of complete or partial block.

Figure 10 is selected in the selected string according to an embodiment of the invention shown for 3D hierarchy type NAND arrays The iteration erasing of 3D units and the figure of erasing check pulse.As shown in the figure, in selected string for 3D hierarchy type NAND arrays Multiple iterative operations of the erasing of selected 3D units are respectively followed by the respective operations that the erasing of identical 3D units is examined, by with Erasing and erasing staggeredly examines the figure of voltage pulse to describe.Exist only for the situation of the 3D hierarchy type NAND arrays of Fig. 9 A V_LBLGo up or in the case of the 3D hierarchy type NAND arrays of Fig. 9 B in V_LBLAnd V_CSLOn, in each iterative step EV0 to EV7 With the equal increments of Vers-step make erasing pulse Vers be sequentially increased to from Vers0 Vers1, Vers2 ..., Vers7. Each iteration for raising Vers pulses wipes step and is related to single increment amplitude Vers-step.And examine behaviour on erasing Work is related to two erasings and examines voltage | Vtemax | and Vinh, | Vtemax | it is due to V_CSL=| Vtemax | setting it is absolute Voltage.

For those unselected 3D strings and unit, Vsg=floats or 0V and V_CSL=Verase or 0V is to forbid GIDL to imitate It should occur.Optionally, the V during checked operation is wiped_LBL=Vinh implies that the Vts of some 3D NAND cells is remained above Vtemax, therefore will be pre-charged V without conductive unit electric current_LBL=Vinh pulls down to V_CSL=Vtemax.Therefore, both the above feelings The iteration 3D erasing operations of any of condition must continue to.

Optionally, the V during checked operation is wiped_LBL=| Vtemax | imply that the Vts of some 3D NAND cells is less than Vtemax (negative value) and wipe, because this element conductive current will make precharge V_LBL=Vinh pulls down to V_CSL=Vtemax.Therefore, The iteration 3D erasing operations of any of both the above situation must stop to avoid erasing is crossed.

Optionally, every C of preferred 3D hierarchy types NAND array herein_LBLWith each corresponding C_GBLBetween perform electric charge share Afterwards, Vinh and | Vtemax | between voltage difference Vinh- | Vtemax | more than 4V, it is in the present invention with or without multiplying In the sensing function of the SA of the analog voltage amplification of musical instruments used in a Buddhist or Taoist mass.

Although illustrated above, other modification, alternative solution and changes to may be present according to specific embodiment.Ying Li Solution, as described above, is only presently preferred embodiments of the present invention, when cannot limit the scope implemented of the present invention with this, i.e., all The simple equivalent changes and modifications made according to claims of the present invention and description, all still belongs to the scope of the present invention.

Claims (59)

1. a kind of 3D NAND arrays with 2 level hierarchical bit-line architectures, it is characterised in that the 3D NAND arrays include：

The one or more planes being formed in the substrate P of isolation, each plane include K separated with by group division device The multiple global bit lines (GBL) being arranged on bit line (BL) direction at the first level that 3D HG groups are associated, every 3D HG groups are divided into J 3D LG group, every 3D LG groups and the multiple local bitlines (LBL) being arranged at the second level Associated, the multiple LBL is respectively coupled to described more parallel to the multiple GBL and via multiple GBL/LBL on-off circuits A GBL, a pair of of 3D LG groups connect via a line TIE signal control devices, and every 3D LG groups include H block, the H It is a it is in the block each include the multiple 3D NAND string associated with the multiple LBL respectively, the string is along being orthogonal to Wordline (WL) direction in the BL directions cascades and is coupled jointly via a line pre-charging device with two PRE signals in a row For odd and even number LBL is accordingly coupled to the independent electrical line of force being arranged in along the WL directions in third layer level, often One 3D NAND strings include a series of S 3D NAND cells, and the unit is being orthogonal to the BL directions and the WL directions Stack around perpendicular block area on stacking direction and gone here and there respectively in two ends of the 3D NAND strings by a pair and select dress Termination is put, the 3D NAND strings make its source node be connected to each or multiple pieces of common source line, the perpendicular block Area isolates with the substrate P of the plane, and K, J, H and S are based on integer and the bigger that memory chip design is more than 2.

2. 3D NAND arrays according to claim 1, it is characterised in that the 3D NAND arrays include：

Block decoder, it is configured to control one group of voltage signal global total via one group from voltage generator using latch signal Line is delivered to two common gates of two rows of the multiple string selection device of all WL and every piece respectively；

One group of decoder, it is used to send the control signal to the group division device, GBL/LBL on-off circuits respectively, uses TIE signals in TIE signal control devices, two PRE signals for pre-charging device；

Drive circuit, it is used for the respectively common source line of each or multiple pieces and the institute per 3D LG groups State the independent electrical line of force and voltage signal is provided.

3. 3D NAND arrays according to claim 2, it is characterised in that the block decoder includes latch cicuit, described It is any complete or partial block for what is wiped for selecting with decoding address information that latch cicuit is coupled to address register WL, and guide the voltage generator to provide one group of bias voltage to select the WL of block.

4. 3D NAND arrays according to claim 1, it is characterised in that the 3D NAND cells include 2- floating polysilicons Moving grid gated transistors or 1- polysilicon trapping charge transistors, the transistor are configured to from described pair of string selection device Described two common gates in it is at least one enter in quick condition the perpendicular block area GIDL hot holes note Enter and perform the erasing of nLC cell datas via hole-electron elimination, for the SLC cell datas with 2 threshold value Vt states N=1, for the MLC cell data n=2 with 4 threshold value Vt states, for the TLC unit numbers with 8 threshold value Vt states According to n=3.

5. 3D NAND arrays according to claim 1, it is characterised in that the 3D NAND strings are along the stacking side To single vertical string, have near second level associated with the LBL at top the first string selection device and There is the second string selection device, first He near the third layer level associated with the common source line in bottom Each in second string selection device is the 3D 1- polycrystalline with the source electrode line and drain line being arranged in vertically stacked orientation Silicon nmos pass transistor.

6. 3D NAND arrays according to claim 1, it is characterised in that the common source line is along the WL side To generally at the same third layer level below second level parallel to the independent electrical line of force but perpendicular to institute State the metal wire of GBL and LBL arrangements.

7. 3D NAND arrays according to claim 1, it is characterised in that the GBL is on the stacking direction described It is arranged at first level above the substrate P, higher than the LBL being arranged in second level, the multiple GBL/ Every a line of LBL on-off circuits, every a line TIE signal control devices per a pair of 3D LG groups and every 3D LG groups is pre- Charging unit is arranged near second level of the LBL.

8. 3D NAND arrays according to claim 7, it is characterised in that every GBL/LBL on-off circuits include 3D LG 1- polysilicon nmos pass transistors are controlled, it is strange in every 3D LG groups with being connected respectively to that the transistor is coupled in the GBL Between a pair of of 3D LGo controls of number numbering LBL and even-numbered LBL and LGe control 1- polysilicon nmos pass transistors.

9. 3D NAND arrays according to claim 7, it is characterised in that every TIE signal control devices include a pair of 3D 1- polysilicon nmos pass transistors, the transistor jointly by the TIE signal gatings and are connected respectively to a pair of of 3D LG groups Two LBL.

10. 3D NAND arrays according to claim 7, it is characterised in that each pre-charging device includes a pair of 3D PREo is controlled and PREe control 1- polysilicon nmos pass transistors, and the independent electrical line of force is connected respectively to each by the transistor The odd-numbered LBL and even-numbered LBL of 3D LG groups, the independent electrical line of force is below the 3D NAND strings described Three hierarchical arrangements are in higher depth.

11. 3D NAND arrays according to claim 1, it is characterised in that the GBL is on the stacking direction in institute State and be arranged at the first level above the substrate P, it is described less than the common source line being arranged at the third layer level Multiple GBL/LBL on-off circuits, every a line TIE signal control devices per a pair of 3D LG groups and every 3D LG groups Each line precharge device is arranged in the third layer of the common source line during upside-down mounting substrate from the dorsal part of chip Level lower section.

12. 3D NAND arrays according to claim 11, it is characterised in that every GBL/LBL on-off circuits include 2D LG controls 1- polysilicon nmos pass transistors, and the transistor is coupled between the GBL in every 3D LG groups and corresponding LBL.

13. 3D NAND arrays according to claim 11, it is characterised in that every TIE signal control devices are included by institute The 2D 1- polysilicon nmos pass transistors of TIE signal gatings are stated, source node and drain node are connected respectively to a pair of of 3D LG groups Two LBL of group.

14. 3D NAND arrays according to claim 11, it is characterised in that each pre-charging device includes a pair of 2D PREo is controlled and PREe control 1- polysilicon nmos pass transistors, and the independent electrical line of force is connected respectively to each by the transistor The odd-numbered LBL and even-numbered LBL, the independent electrical line of force of 3D LG groups are arranged in from the dorsal part of the chip At level near the GBL.

15. 3D NAND arrays according to claim 3, it is characterised in that random positioned at selected one or more in the block Partial block WL is configured to be selected for performing erasing operation, and the selected block belongs to H in any selected 3D LG groups One in the block, the total number for one or more of partial block WL of erasing is selected from the 1 integer Z for arriving S-1.

16. 3D NAND arrays according to claim 15, it is characterised in that one or more of portions for erasing Piecemeal WL includes one or more unselected border WL, and the border WL is subjected to pre-reading extract operation to obtain corresponding page data and warp By programming operation with the replacement that is written to the page data in the current not selected another pair 3D LG groups for being used to wipe The page data is saved in Flash controller outside chip by a pair of of LBL.

17. 3D NAND arrays according to claim 15, it is characterised in that to selecting in the selected block in 3D LG groups One or more of partial block WL the erasing operation include have steps of 1 side GIDL erasing scheme：

Make group division device in the selected 3D LG groups, GBL/LBL on-off circuits, TIE signal control devices and pre- All gate-floatings of charging unit；

It is increased at the multiple LBL of the selected 3D LG groups in the preparation stage from 0V from the corresponding independent electrical The Vsg voltages of power supply line supply, the Vsg voltages are for causing GIDL hot in the perpendicular block area of quick condition The predetermined optimum voltage in hole；

Setting is used for the multiple string selection associated with each selected block in the preparation stage and subsequent charge stage The voltage signal of described two common gates of described two rows of device；

Verase voltages are further ramped up to from the Vsg voltages in the charging stage at the multiple LBL, at the same time will At least one the Vsg voltages are maintained in described two common gates of described pair of string selection device；And

Corresponding one group of bias voltage is provided to all WL to each selected block in the erasing stage from the block decoder, at the same time The multiple LBL of correspondence is maintained at the Verase voltages, described group of bias voltage include from quick condition voltage to for The 0V of each in one or more of partial block WL of erasing pulls down and is latched into the institute in the quick condition There are the Verase voltages of remaining unselected WL.

18. 3D NAND arrays according to claim 17, it is characterised in that in the described more of each selected 3D LG groups A LBL, which was in the preparation stage, to be increased to Vsg voltages from 0V and includes：

The Verase that will be up to about 20V puts on the independent electrical line of force associated with the selected 3D LG groups, while 0V is kept at the independent electrical line of force associated with unselected 3D LG groups；

By for the line precharge device that is connected to the independent electrical line of force associated with the selected 3D LG groups Grid voltage is increased to the Vsg voltages from 0V and adds transistor threshold voltage Vt, simultaneously for unselected 3D LG groups phase Other grid voltages of associated other line precharge devices keep 0V；

The common source line of each selected block in the selected 3D LG groups is set to float, while in unselected piece of institute State holding 0V at common source line.

19. 3D NAND arrays according to claim 17, it is characterised in that in the preparation stage setting be used for The voltage signal of two common gates of the described two rows for the string selection device that each selected block is associated includes：

Vsg voltages and global total at described group are produced by the voltage generator one in described group of global bus 0V is produced at another in line；

The latch signal of the block decoder is set in high voltage, to be in the institute of the Vsg voltages by being connected to One in Shu Zu global buses and described the of the string selection device in the LBL being coupled at second level The Vsg voltages are increased to from 0V at first common gate of a line, and make the string selection dress for being coupled to the common source line Second common gate of second row put floats；

The common gate of the string selection device associated with unselected piece is set to float.

20. 3D NAND arrays according to claim 19, it is characterised in that in the charging stage setting be used for The voltage signal of two common gates of the described two rows for the string selection device that each selected block is associated includes：

The Vsg voltages are kept at first common gate but are floated at second common gate, and are further led to Spend the erasing stage；

The common gate of the string selection device associated with unselected piece is set to float.

21. 3D NAND arrays according to claim 17, it is characterised in that by corresponding one group of bias voltage from described piece All WL that decoder is provided to each selected block include：

The latch signal is switched to the high voltage that threshold level is added equal to the Verase for each controlling transistor, Described group of global bus is connected to each selected of the common gate comprising string selection device based on next every selected block All WL of the block and optional illusory WL for being completely in quick condition；

The latch signal is switched to 0V being latched into 0V for all described of erasing again in the erasing stage Selected part block WL and by the Verase voltage latch to remaining all unselected WL and the illusory WL in quick condition；With And

The latch signal is maintained at 0V for all unselected pieces.

22. 3D NAND arrays according to claim 17, it is characterised in that it further comprises：

In the preparation stage Vsg voltages are increased to from 0V at the common source line for the selected block；

From 0V liters at second common gate of second row for the string selection device for being coupled to the common source line Height arrives the Vsg voltages；

In the charging stage Verase electricity is further risen to from the Vsg voltages at the common source line Pressure, for being in quick condition from LBL sides and common source line side starting both sides GIDL effects to inject hot holes into In the perpendicular block area.

23. 3D NAND arrays according to claim 3, it is characterised in that one of part planar including the plane or One or more of multiple 3D HG groups all 3D NAND strings in the block, at least one 3D HG groups include random number L A 3D LG groups, L are selected from 1 until J-1 3D LG group, the part planar are configured in the following manner to the choosing All selected parts/whole blocks the WL determined in 3D NAND strings performs erasing operation：Connect and be isolated from other unselected 3D LG All corresponding LBL that all selected 3D LG groups of group are associated, will set close to the string selection device of corresponding LBL At described selected 3D LG groups while the string selection device floating for being set to high voltage and making to be coupled to corresponding common source line 0V is latched at all pieces of all WL in group, the LBL of the connection is ramped up to Verase from 0V for for every 3D NAND string originates 1 side GIDL effects to inject hot holes into the corresponding perpendicular block area in quick condition from LBL sides.

24. 3D NAND arrays according to claim 23, it is characterised in that for described in the part planar at the same time Erasing operation further comprises：

The connection all common source lines associated with all 3D NAND strings in the selected L 3D LG groups；

It will be set as high voltage close to the string selection device of corresponding common source line and making to be coupled to described in corresponding LBL 0V is latched at all pieces of all WL while selection device of going here and there floats in the selected L 3D LG groups；

Verase is ramped up to for originating another 1 side GIDL effects from 0V via the drive circuit for the common source line It should be in injecting hot holes into the corresponding perpendicular block area of quick condition.

25. a kind of 3D NAND arrays with 2 level hierarchical bit-line architectures, it includes：

One or more NAND planes with independent substrate P, each plane are included with being connected with each other by a line 3D DGBL circuits The multiple global bit lines (GBL) being arranged at the first level that are associated of J 3D HG group, every 3D HG groups are divided Into N₂A 3D LG groups, every 3D LG groups are associated with the multiple local bitlines (LBL) being arranged at the second level, described Multiple LBL are respectively coupled to the multiple GBL, every 3D parallel to GBL directions and via multiple 3D GBL/LBL on-off circuits LG groups include H block, the H it is in the block each include multiple 3D NAND associated with the multiple LBL respectively String, it is described string along be orthogonal to wordline (WL) direction in the GBL directions in a row and cascade and jointly via a line 3D preliminary fillings Electric installation and extra 3D EPR control devices and two PRE signals are coupled for being coupled to edge by odd and even number LBL is corresponding The independent electrical line of force that the WL directions are arranged in third layer level, every 3D NAND strings include being formed with U-shape a series of S 3D NAND cell, two part strings are on the stacking direction in the GBL directions and the WL directions is orthogonal in vertical blocks Stack around body area and linked at the bottom of the string by BG control devices, the 3D NAND strings connect its source node To the first string selection device controlled by SSL signals and its drain node is set to be connected to the second string selection controlled by GSL signals Device and be coupled to each or multiple pieces of common source line, the substrate P of the perpendicular block area and the plane every From J, N₂, H and S based on memory chip design be more than 2 integer and bigger.

26. 3D NAND arrays according to claim 25, it is characterised in that further comprise：

Block decoder, it is configured to control one group of voltage signal global total via one group from voltage generator using latch signal Line is delivered to the SSL and GSL of the first and second strings selection device of all WL and every piece respectively；

One group of decoder, it is used to send the control to the row 3D DGBL devices, multiple 3DGBL/LBL on-off circuits respectively Signal, two PRE signals and the epr signal for a line 3D pre-charging devices；

Drive circuit, it is used for the respectively common source line of each or multiple pieces and the institute per 3D LG groups State the independent electrical line of force and voltage signal is provided.

27. 3D NAND arrays according to claim 26, it is characterised in that the block decoder includes latch cicuit, institute State latch cicuit and be coupled to address register with decoding address information for any complete or partial block of the selection for erasing WL, and guide the voltage generator to provide one group of bias voltage for the WL of selected block.

28. 3D NAND arrays according to claim 25, it is characterised in that the 3D NAND cells include 2- polysilicons Floating grid transistor or 1- polysilicon trapping charge transistors, the transistor are configured to from described pair of string selection dress At least one GIDL hot holes for entering the perpendicular block area in quick condition in the described two common gates put Inject and perform the erasing of nLC cell datas via hole-electron elimination, for the SLC unit numbers with 2 threshold value Vt states According to n=1, for the MLC cell data n=2 with 4 threshold value Vt states, for the TLC units with 8 threshold value Vt states Data n=3.

29. 3D NAND arrays according to claim 25, it is characterised in that the common source line is along the WL Direction generally at the same third layer level below second level parallel to the independent electrical line of force but perpendicular to The metal wire of GBL and the LBL arrangement.

30. 3D NAND arrays according to claim 25, it is characterised in that the GBL is on the stacking direction in institute State and be arranged at the first level above the substrate P, higher than the LBL being arranged in second level, per a line 3D DGBL devices, the multiple 3D GBL/LBL on-off circuits and every a line 3D pre-charging devices of every 3D LG groups arrangement Near second level of the LBL.

31. 3D NAND arrays according to claim 25, it is characterised in that every 3D DGBL devices include shared common A pair of of 3D nmos pass transistors of grid, the common gate are controlled by the DGBL signals for connecting two adjacent GBL respectively.

32. 3D NAND arrays according to claim 25, it is characterised in that every 3D GBL/LBL on-off circuits include 3D LG12 control nmos pass transistor, and the drain node of the 3D LG12 controls nmos pass transistor is coupled to the GBL and source electrode Node is commonly coupled to the source node of 3D LG1 control nmos pass transistors and LG2 control nmos pass transistors, the 3D LG1 controls Nmos pass transistor and LG2 processed control nmos pass transistor make its drain node be connected to the LBL of 3D LG groups and adjacent respectively The LBL of 3D LG groups.

33. 3D NAND arrays according to claim 25, it is characterised in that the 3D pre-charging devices include a pair of 3D PREo is controlled and PREe control nmos pass transistors, the pair of transistor control nmos pass transistor by the independence by 3D EPR Power line is respectively coupled to the odd-numbered LBL and even-numbered LBL of every 3D LG groups.

34. 3D NAND arrays according to claim 25, it is characterised in that random positioned at one in the block or more selected A partial block WL is configured to be selected for performing erasing operation, and the selected block belongs to the H in any selected 3D LG groups A one in the block, the total number for one or more of partial block WL of erasing is selected from the 1 integer Z for arriving S-1.

35. 3D NAND arrays according to claim 34, it is characterised in that one or more of portions for erasing Piecemeal WL includes one or more unselected border WL, and the border WL is subjected to pre-reading extract operation to obtain corresponding page data and connect Is programming operation so that the page data to be written to the replacement in the current not selected another pair 3D LG groups for being used to wipe A pair of of LBL or the page data is saved in Flash controller outside chip.

36. 3D NAND arrays according to claim 34, it is characterised in that to selecting in the selected block in 3D LG groups One or more of partial block WL the erasing operation include have steps of 1 side GIDL erasing scheme：

Epr signal is set as 0V for controlling the 3D EPR control devices；

Make all grid of 3D GBL/LBL on-off circuits in the selected 3D LG groups, DGBL circuits and 3D pre-charging devices Float pole；

It is increased in the preparation stage at the common source line of each selected block of each selected 3D LG groups from 0V Vsg voltages, the Vsg voltages are for causing the predetermined of GIDL hot holes in the perpendicular block area in quick condition Optimum voltage；

Setting is used for associated with each selected block the multiple described the in the preparation stage and subsequent charge stage One and it is described second string selection device SSL and GSL voltage signal；

In the Vsg voltages of the GSL signals for the multiple second string selection device for being left coupled to the common source line While in the charging stage at the common source line further from the Vsg voltage ramps to Verase voltages； And

Corresponding one group of bias voltage is provided to all WL to each selected block in the erasing stage from the block decoder, at the same time The multiple LBL of correspondence is maintained at the Verase voltages, described group of bias voltage in the erasing stage is included from floating type State voltage is to the 0V of each drop-downs in one or more of partial block WL for erasing and is latched into described The Verase voltages of remaining all unselected WL of quick condition.

37. 3D NAND arrays according to claim 36, it is characterised in that setting is used for every in the preparation stage The multiple described the first of one selected block and the voltage signal of the SSL and GSL of the second string selection device include：

Vsg voltages and global total at described group are produced by the voltage generator one in described group of global bus 0V is produced at another in line；

The latch signal of the block decoder is set in high voltage, to be in the institute of the Vsg voltages by being connected to One in Shu Zu global buses and for the described of the second string selection device for being coupled to the common source line GSL signals are increased to the Vsg voltages from 0V, and the first string selection device for being coupled to the LBL is floated；

The common gate of the other string selection devices associated with unselected piece is set to float.

38. the 3D NAND arrays according to claim 37, it is characterised in that setting is used for every in the charging stage The multiple described the first of one selected block and the voltage signal of the SSL and GSL of the second string selection device include：

Keep being used for the Vsg voltages of the GSL of the described second string selection device but make the first string selection device The SSL floats, and further passes through the erasing stage；

The common gate of the other string selection devices associated with unselected piece is set to float.

39. 3D NAND arrays according to claim 36, it is characterised in that by corresponding one group of bias voltage from described piece All WL that decoder is provided to each selected block include：

The latch signal is switched to the high voltage that threshold level is added equal to the Verase for each controlling transistor, Described group of global bus is connected to comprising described in the described first and second string selection devices based on next every selected block All WL of each selected block of the SSL and GSL and optional illusory WL for being completely in quick condition；

The latch signal is switched to 0V being latched into 0V for all described of erasing again in the erasing stage Selected part block WL and by the Verase voltage latch to remaining all unselected WL and the illusory WL in quick condition；With And

The latch signal is maintained at 0V for all unselected pieces.

40. 3D NAND arrays according to claim 27, it is characterised in that part planar includes one of the plane Or one or more of multiple 3D HG groups all 3D NAND strings in the block, at least one 3D HG groups include random number L 3D LG group of mesh, L are selected from 1 until J-1 3D LG group, and the part planar is configured in the following manner to choosing All selected parts/whole blocks the WL determined in 3D NAND strings performs erasing operation：Connect and be isolated from other unselected 3D LG All corresponding LBL that all selected 3D LG groups of group are associated, will set close to the string selection device of corresponding LBL At described selected 3D LG groups while the string selection device floating for being set to high voltage and making to be coupled to corresponding common source line 0V is latched at all pieces of all WL in group, the LBL of the connection is ramped up to Verase from 0V for for every 3D NAND string originates 1 side GIDL effects to inject hot holes into the corresponding perpendicular block area in quick condition from LBL sides.

41. 3D NAND arrays according to claim 27, it is characterised in that further comprise：

One DHG circuit, it is used to make the transistor channel of every 3D DGBL circuits to be grounded；

The first VSP control circuits to the 3D GBL/LBL on-off circuits per 3D LG groups；

The 2nd VSP control circuits to the 3D pre-charging devices per 3D LG groups；

Every 3D NAND strings are configured to have the correspondence perpendicular block area for being connected to the common source line.

42. 3D NAND arrays according to claim 41, it is characterised in that every 3D in every 3D NAND strings NAND cell includes being configured to the 2- poly floatings that one or more partial block WL are performed with nLC cell data erasing operations Gridistor or 1- polysilicon trapping charge transistors, it is right for the SLC cell datas n=1 with 2 threshold value Vt states In the MLC cell data n=2 with 4 threshold value Vt states, for the TLC cell datas n=3 with 8 threshold value Vt states.

43. 3D NAND arrays according to claim 42, it is characterised in that to one or more of partial block WL's The erasing operation includes the selected FN tunneling schemes in the block in selected 3D LG groups having steps of：

Make the VSP signal grounds and epr signal is set as 0V for controlling the EPR control devices；

Make owning for the 3D GBL/LBL on-off circuits in the selected 3D LG groups, 3D DGBL circuits and 3D pre-charging devices Gate-floating；

It is increased in the preparation stage from 0V at the common source line of each selected block of each selected 3D LG groups pre- Determine Ver1 voltages；

Setting is used for the SSL and GSL of the described first and second string selection devices in the preparation stage and subsequent charge stage Voltage signal；

In the charging stage be connected at the common source line in the perpendicular block area from the Ver1 voltages into One step ramps up to the Verase voltages for being up to about 20V to realize that FN tunnellings wipe scheme, while for the described second string selection At the GSL of device floating is increased to from 0V；And

Corresponding one group of bias voltage is provided to all WL to each selected block, described group of biased electrical briquetting from the block decoder Include in the preparation stage for all WL 0V, the charging stage into the erasing stage be used for it is one or more of The 0V of each in partial block WL, and the charging stage into the erasing stage for all unselected WL from The voltage of the elevated quick conditions of 0V.

44. 3D NAND arrays according to claim 43, it is characterised in that setting is used for every in the preparation stage The voltage signal of the SSL and GSL of the first and second strings selection device of one selected block include：

It is being coupled to the multiple first string selection device of the LBL associated with the selected 3D LG groups Float at SSL；

0V is set at the GSL of the second row string selection device for being coupled to the common source line；

Other common gates of the string selection device associated with unselected piece are made to float.

45. 3D NAND arrays according to claim 44, it is characterised in that setting is used for every in the charging stage The voltage signal of the SSL and GSL of the first and second strings selection device of one selected block include：

The SSL of described first string selection device is maintained at quick condition, and further passes through the erasing stage；

Quick condition is increased to from 0V at the GSL of the described second string selection device, and further passes through the erasing rank Section；

Other common gates of the string selection device associated with unselected piece are made to float.

46. 3D NAND arrays according to claim 43, it is characterised in that by corresponding one group of bias voltage from described piece All WL that decoder is provided to each selected block include：

The latch signal is switched to the high voltage that threshold level is added equal to the Verase for each controlling transistor, Described group of global bus is connected to each selected of SSL and GSL comprising string selection device based on next every selected block All WL of block and optionally illusory WL；

The latch signal is switched to 0V being latched into 0V for all described of erasing again in the erasing stage Selected part block WL and by the Verase voltage latch to remaining all unselected WL and the illusory WL in quick condition；With And

The latch signal is maintained at 0V for all unselected pieces.

47. 3D NAND arrays according to claim 41, it is characterised in that part planar includes one of the plane Or one or more of multiple 3D HG groups all 3D NAND strings in the block, at least one 3D HG groups include random number L 3D LG group of mesh, L are selected from 1 until J-1 3D LG group, the part planar are configured in the following manner to portion Point/the 3D NAND strings of whole blocks in all selected parts/whole blocks WL perform erasing operation：Connection is coupled to corresponding vertical All corresponding common source lines of the same drive circuit in block area, dress is selected in the string for being used in corresponding 3D NAND strings 0V is latched at all pieces of all WL while the SSL and GSL put floats in the selected 3D LG groups, via The same drive circuit makes the common source line of the connection ramp up to Verase from 0V for via FN tunneling effects Electronics is removed to the corresponding perpendicular block area from 3D NAND cells.

48. a kind of 3D NAND arrays with 2 level hierarchical bit-line architectures, it includes：

One or more NAND planes in corresponding substrate P, each plane include with by the separated K 3D of group division device The multiple global bit lines (GBL) being arranged on bit line (BL) direction at the first level that HG groups are associated, every 3D HG crowds Group is divided into J 3D LG group, and every 3D LG groups are related to the multiple local bitlines (LBL) being arranged at the second level Connection, the multiple LBL is respectively coupled to the multiple parallel to the multiple GBL and via multiple 2D GBL/LBL on-off circuits GBL, a pair of of 3D LG groups connect via a line 2D TIE signal control devices, and every 3D LG groups include H block, described H it is in the block each include multiple 3D NAND strings associated with the multiple LBL respectively, the string is along being orthogonal to State wordline (WL) direction in BL directions in a row and cascade and coupled jointly via a line 2D pre-charging devices with two PRE signals For odd and even number LBL is accordingly coupled to the independent electrical line of force being arranged in along the WL directions in third layer level, often One 3D NAND strings include a series of S 3D NAND cells, and the unit is being orthogonal to the BL directions and the WL directions Stacked on stacking direction around perpendicular block area, the 3D NAND strings make its source node be connected to what is controlled by SSL signals First string selection device and make its drain node be connected to the second string controlled by GSL signals selection device and to be coupled to each Or multiple pieces of common source line, the perpendicular block area are formed directly into the substrate P of the plane, K, J, H and S base In memory chip design be more than 2 integer and bigger；

Block decoder, it is configured to control one group of voltage signal global total via one group from voltage generator using latch signal Line is delivered to the SSL and GSL of the first and second strings selection device of all WL and every piece respectively；

One group of decoder, it is used to send the control to the group division device, every 2D GBL/LBL on-off circuits respectively Signal, the TIE signals for every a line TIE signal control devices, two PRE signals for 2D pre-charging devices；

Drive circuit, it is used for the respectively common source line of each or multiple pieces and the institute per 3D LG groups State the independent electrical line of force and voltage signal is provided.

49. 3D NAND arrays according to claim 48, it is characterised in that the block decoder includes latch cicuit, institute State latch cicuit and be coupled to address register with decoding address information for any complete or partial block of the selection for erasing WL, and guide the voltage generator to provide one group of bias voltage for the WL of selected block.

50. 3D NAND arrays according to claim 48, it is characterised in that the 3D NAND cells include 2- polysilicons Floating grid transistor or 1- polysilicon trapping charge transistors, the transistor are configured to arrive retention Electron absorption The erasing of nLC cell datas is performed in the perpendicular block area in the Verase voltages and via FN tunneling effects, for SLC cell data n=1 with 2 threshold value Vt states are right for the MLC cell data n=2 with 4 threshold value Vt states In the TLC cell datas n=3 with 8 threshold value Vt states.

51. 3D NAND arrays according to claim 48, it is characterised in that the common source line is along the WL Direction generally at the same third layer level below second level parallel to the independent electrical line of force but perpendicular to The metal wire of GBL and the LBL arrangement.

52. 3D NAND arrays according to claim 48, it is characterised in that the GBL is on the stacking direction in institute State and be arranged at the first level above the substrate P, higher than the LBL being arranged in second level, corresponding 2D GBL/ LBL on-off circuits, every the 2D TIE signal control devices of a pair of 3D LG groups and the 2D preliminary filling Densos of every 3D LG groups Put and be arranged near the third layer level for the independent electrical line of force；

The 2D LG controls NMOS that the 2D GBL/LBL on-off circuits include being coupled between the GBL and the corresponding LBL is brilliant Body pipe；

The 2D TIE signal control devices include the TIE signals of control 2D nmos pass transistors, the 2D nmos pass transistors tool There are drain electrode and the source node of two LBL for being connected respectively to every a pair of 3D LG groups；

The 2D pre-charging devices include a pair of 2D PREo controls and PREe control nmos pass transistors, and the pair of transistor will The independent electrical line of force is connected respectively to the odd number LBL and even number LBL of every 3D LG groups.

53. 3D NAND arrays according to claim 48, it is characterised in that random positioned at one in the block or more selected A partial block WL is configured to be selected for performing erasing operation, and the selected block belongs to the H in any selected 3D LG groups A one in the block, the total number for one or more of partial block WL of erasing is selected from the 1 integer Z for arriving S-1.

54. 3D NAND arrays according to claim 53, it is characterised in that one or more of portions for erasing Piecemeal WL includes one or more unselected border WL, and the border WL is subjected to pre-reading extract operation to obtain corresponding page data and connect Be programming operation with by the page data be written to it is current it is not selected be used to wiping it is associated with substituting substrate P another The page data is saved in Flash controller outside chip by a pair of of LBL of the replacement in another pair 3D LG groups in plane.

55. 3D NAND arrays according to claim 53, it is characterised in that to selecting in the selected block in 3D LG groups The erasing operation of one or more of partial block WL include the FN tunneling schemes that have steps of：

Make group division device, 2D GBL/LBL on-off circuits, the 2D TIE signal control devices in the selected 3D LG groups And all gate-floatings of 2D pre-charging devices；

One or more of erasing is selected in each selected block containing each selected 3D LG groups in the preparation stage At the substrate P of the plane of a partial block WL predetermined Ver1 voltages are increased to from 0V；

Setting is used for the SSL and GSL of the described first and second string selection devices in the preparation stage and subsequent charge stage Voltage signal；

Further ramped up to from the Ver1 voltages at the substrate P and the perpendicular block area in the charging stage The Verase voltages of 20V are up to about to realize that FN tunnellings wipe scheme, while are raised from 0V so as to be coupled to the common source The GSL of the second string selection device of line floats；And

Corresponding one group of bias voltage is provided to all WL to each selected block, described group of biased electrical briquetting from the block decoder Include in the preparation stage for all WL 0V, the charging stage into the erasing stage be used for it is one or more of The 0V of each in partial block WL, and the charging stage into the erasing stage for all unselected WL from The voltage of the elevated quick conditions of 0V.

56. 3D NAND arrays according to claim 54, it is characterised in that setting is used for every in the preparation stage The voltage signal of the SSL and GSL of the first and second strings selection device of one selected block include：

Make to be coupled to described in multiple first string selection devices of the LBL associated with the selected 3D LG groups SSL floats；

0V is set at the GSL of multiple second string selection devices for being coupled to the common source line；

Other common gates of the string selection device associated with unselected piece are made to float.

57. 3D NAND arrays according to claim 55, it is characterised in that setting is used for every in the charging stage The voltage signal of the SSL and GSL of the first and second strings selection device of one selected block include：

The SSL of described first string selection device is maintained at quick condition, and further passes through the erasing stage；

Quick condition is increased to from 0V at the GSL of the described second string selection device, and further passes through the erasing rank Section；

Other common gates of the string selection device associated with unselected piece are made to float.

58. 3D NAND arrays according to claim 54, it is characterised in that by corresponding one group of bias voltage from described piece All WL that decoder is provided to each selected block include：

The latch signal is switched to the high voltage that threshold level is added equal to the Verase for each controlling transistor, With based on per next selected block by described group of global bus be connected to the SSL comprising the described first and second string selection devices and All WL of each selected block of GSL and optionally illusory WL；

The latch signal is switched to 0V being latched into 0V for all described of erasing again in the erasing stage Selected part block WL and by the Verase voltage latch to remaining all unselected WL and the illusory WL in quick condition；With And

The latch signal is maintained at 0V for all unselected pieces.

59. 3D NAND arrays according to claim 48, it is characterised in that part planar includes one of the plane Or one or more of multiple 3D HG groups all 3D NAND strings in the block, at least one 3D HG groups include random number L 3D LG group of mesh, L are selected from 1 until J-1 3D LG group, the part planar are configured in the following manner to portion Point/the 3D NAND strings of whole blocks in all selected parts/whole blocks WL perform erasing operation：It is being used in corresponding 3D NAND All part/whole blocks while the SSL and GSL of the string selection device of string float in the selected 3D LG groups Selected WL at latch 0V, via make the substrate P from 0V ramp up to Verase for via FN tunneling effects from 3D NAND Unit removes electronics to the corresponding perpendicular block area.