CN107919325A - 鳍式场效应晶体管的制造方法 - Google Patents
鳍式场效应晶体管的制造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 230000005669 field effect Effects 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 238000000926 separation method Methods 0.000 claims abstract description 24
- 150000002500 ions Chemical class 0.000 claims description 136
- 230000008569 process Effects 0.000 claims description 37
- 238000000137 annealing Methods 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 30
- 239000007789 gas Substances 0.000 claims description 26
- 230000003647 oxidation Effects 0.000 claims description 23
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 229910021529 ammonia Inorganic materials 0.000 claims description 8
- 239000001307 helium Substances 0.000 claims description 8
- 229910052734 helium Inorganic materials 0.000 claims description 8
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 8
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 18
- 230000009286 beneficial effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003085 diluting agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004821 distillation Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
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- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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Abstract
一种鳍式场效应晶体管的制造方法,包括:提供基底;刻蚀所述基底,形成衬底以及位于衬底上的鳍部;在所述鳍部之间的衬底上形成隔离膜;去除部分厚度的所述隔离膜,形成初始隔离层,所述初始隔离层顶部表面低于所述鳍部顶部表面;对所述初始隔离层进行离子掺杂;去除部分厚度的所述初始隔离层,形成隔离层。本发明的有益效果在于,离子掺杂工艺中减少了鳍部的损伤,且减少了凸出鳍部造成阴影效应的发生,从而提高了鳍式场效应晶体管的电学性能和稳定性。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种鳍式场效应晶体管的制造方法。
背景技术
在半导体制造中,随着超大规模集成电路的发展趋势,集成电路特征尺寸持续减小。为了适应特征尺寸的减小,MOSFET器件的沟道长度也相应不断缩短。然而,随着器件沟道长度的缩短,器件源极与漏极间的距离也随之缩短,因此栅极对沟道的控制能力随之变差,栅极电压夹断(pinch off)沟道的难度也越来越大,使得亚阈值漏电(subthresholdleakage)现象,即所谓的短沟道效应(SCE:short-channel effects)更容易发生。
因此,为了更好的适应特征尺寸的减小,半导体工艺逐渐开始从平面MOSFET晶体管向具有更高功效的三维立体式的晶体管过渡,如鳍式场效应管(FinFET)。FinFET中,栅至少可以从两侧对超薄体(鳍部)进行控制,与平面MOSFET器件比栅对沟道的控制能力更强,从而能够很好的抑制短沟道效应。
然而,现有技术形成的鳍式场效应晶体管的电学性能和稳定性能仍有待提高。
发明内容
本发明解决的问题是提供一种鳍式场效应晶体管的制造方法,提高晶体管的电学性能和稳定性。
为解决上述问题,本发明提供一种鳍式场效应晶体管的制造方法,包括:提供基底;刻蚀所述基底,形成衬底以及位于衬底上的鳍部;在所述鳍部之间的衬底上形成隔离膜;去除部分厚度的所述隔离膜,形成初始隔离层,所述初始隔离层顶部表面低于所述鳍部顶部表面;对所述初始隔离层进行离子掺杂;去除部分厚度的所述初始隔离层,形成隔离层。
可选的,对所述初始隔离层进行离子掺杂的步骤包括:沿垂直于衬底表面方向对所述初始隔离层进行离子掺杂。
可选的,对所述初始隔离层进行离子掺杂的步骤中,所述掺杂离子为调整鳍式场效应晶体管阈值电压的离子。
可选的,所述晶体管为N型晶体管,所述掺杂离子为B离子;或者,所述晶体管为P型晶体管,所述掺杂离子为P离子或As离子。
可选的,刻蚀所述基底,形成衬底以及位于衬底上的鳍部的步骤包括:在所述基底上形成硬掩膜层;以所述硬掩膜层为掩膜对所述基底进行刻蚀,形成衬底以及位于衬底上的鳍部;所述制造方法在对所述初始隔离层进行离子掺杂的步骤之后,形成隔离层的步骤之前还包括:去除所述硬掩膜层。
可选的,所述硬掩膜层的材料为氮化硅。
可选的,所述制造方法还包括:在离子掺杂之后,去除硬掩膜层之前,进行退火工艺处理。
可选的,所述进行退火工艺处理的步骤包括:采用尖峰退火、快速退火或炉管退火的方式进行退火工艺处理。
可选的,所述进行退火工艺处理的步骤包括:所述退火工艺为尖峰退火,所述退火工艺的温度为950-1100℃,退火时间为0-30s。
可选的,所述对初始隔离层进行离子掺杂的步骤包括:采用离子注入的方式对初始隔离层进行离子掺杂。
可选的,所述离子注入的离子源为BF2,离子注入的能量范围为2-35keV,剂量范围为1.0E13-5.0E14atm/cm2;或者,所述离子注入的离子源为B,离子注入的能量范围为1-15keV,剂量范围为1.0E13-5.0E14atm/cm2。
可选的,所述离子注入的离子源为P,离子注入的能量范围为2-25keV,剂量范围为1.0E13-5.0E14atm/cm2;或者,所述离子注入的离子源为As,离子注入的能量范围为5-40keV,剂量范围为1.0E13-5.0E14atm/cm2。
可选的,去除部分厚度的隔离膜,形成初始隔离层的步骤中,所述初始隔离层顶部表面比鳍部顶部表面低
可选的,去除部分厚度的初始隔离层,形成隔离层的步骤中,所述隔离层顶部表面比鳍部顶部表面低
可选的,所述去除部分厚度的隔离膜形成初始隔离层的步骤,或者,所述去除部分厚度的初始隔离层形成隔离层的步骤包括:采用SiCoNi刻蚀工艺进行去除步骤。
可选的,所述去除部分厚度的隔离膜,形成初始隔离层的步骤中,SiCoNi刻蚀工艺的工艺参数包括:氦气的气体流量为600sccm至2000sccm,三氟化氮的气体流量为20sccm至200sccm,氨气的气体流量为100sccm至500sccm,腔室压强为0.01Torr至50Torr,工艺时间为20s至300s。
可选的,所述去除部分厚度的初始隔离层,形成隔离层的步骤中,SiCoNi刻蚀工艺的工艺参数包括:氦气的气体流量为600sccm至2000sccm,三氟化氮的气体流量为20sccm至200sccm,氨气的气体流量为100sccm至500sccm,腔室压强为0.01Torr至50Torr,工艺时间为20s至500s。
可选的,所述基底包括用于形成N型晶体管的第一区域,以及用于形成P型晶体管的第二区域;对所述初始隔离层进行离子掺杂的步骤包括:对第一区域的初始隔离层进行B离子掺杂;在对第一区域的隔离层进行B离子掺杂之后,对第二区域的初始隔离层进行P、As离子掺杂。
可选的,所述制造方法还包括:在形成位于衬底上的鳍部之后,形成隔离膜之前,在所述鳍部的侧面和鳍部之间的衬底上形成线性氧化层。
可选的,所述线性氧化层的厚度为
与现有技术相比,本发明的技术方案具有以下优点:
本发明提供的鳍式场效应晶体管的制造方法,采用对初始隔离层进行离子掺杂,通过掺杂离子横向(与衬底表面平行的方向)扩散到鳍部的方式掺杂鳍部,一方面由于对初始隔离层进行掺杂,而不直接对鳍部进行离子掺杂,因此降低了离子掺杂工艺的难度。另一方面,不直接对鳍部进行离子掺杂可以减少鳍部在离子掺杂工艺中受到的损伤,从而提高了鳍式场效应晶体管的电学性能和稳定性。
可选方案中,采用沿垂直于衬底表面方向的离子掺杂工艺对初始隔离层进行离子掺杂,也可以避免因凸出鳍部造成阴影效应(shadow effect)的发生,防止无法对鳍部位置进行有效离子掺杂的现象发生,从而可以有效准确地对鳍部进行掺杂,提高晶体管的电学性能。
可选方案中,在基底上先形成硬掩膜层,以所述硬掩膜层为掩膜对所述基底进行刻蚀,形成衬底以及位于衬底上的鳍部。硬掩膜层在对初始隔离层进行离子掺杂工艺之后被去除,可以在进行离子掺杂步骤中保护鳍部的顶部,从而防止鳍部受到损伤,进而提高鳍式场效应晶体管的电学性能和稳定性。
附图说明
图1是一种鳍式场效应晶体管制造方法中离子注入步骤的结构示意图;
图2至9是本发明鳍式场效应晶体管制造方法一实施例中各个步骤的示意图。
具体实施方式
由背景技术可知,现有技术形成的鳍式场效应晶体管的电学性能和稳定性仍有待提高。
结合现有技术的制造方法,对鳍式场效应晶体管电学性能不符合要求、稳定性不好的原因进行分析。
为了提高鳍式场效应晶体管的性能,现有技术会对鳍部进行离子注入以对阈值电压进行调整。然而由于鳍部凸出衬底表面,在对鳍部进行离子注入时,凸出的鳍部容易导致注入离子阴影效应(shadow effect)的发生。
为了减少所述阴影效应,采用图1所示的鳍式场效应晶体管制造方法。所述制造方法包括:在基底(未示出)上形成衬底10以及位于衬底10上的鳍部11,在鳍部11之间的衬底10上形成隔离膜12,所述隔离膜12与所述鳍部11的表面齐平。沿垂直于衬底10表面方向对鳍部11进行离子注入,以进行阈值电压调整。
图1所述方案采用垂直于衬底10表面方向对鳍部11进行离子注入,可以避免阴影效应的发生,但是由于需要直接对鳍部11进行离子注入,离子注入工艺中采用的高能量掺杂离子容易对鳍部11表面造成注入损伤,导致鳍部11的形貌不良且产生晶格损伤,降低了晶体管的质量和性能,此外,所述鳍部11损伤难以通过后续工艺进行恢复,降低了晶体管的电学性能和稳定性。
为解决上述技术问题,本发明提供鳍式场效应晶体管的制造方法,包括:提供基底;刻蚀所述基底,形成衬底以及位于衬底上的鳍部;在所述鳍部之间的衬底上形成隔离膜;去除部分厚度的所述隔离膜,形成初始隔离层,所述初始隔离层顶部表面低于所述鳍部顶部表面;对所述初始隔离层进行离子掺杂;去除部分厚度的所述初始隔离层,形成隔离层。
本发明提供的鳍式场效应晶体管的制造方法,通过对初始隔离层进行离子掺杂,使掺杂离子通过横向扩散的方式进入鳍部内,减少了凸出的鳍部造成阴影效应的发生,从而可以有效准确地对鳍部进行掺杂,提高了晶体管的电学性能和稳定性。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图2至图9是本发明鳍式场效应晶体管制造方法一实施例中各个步骤的示意图。本实施例以互补的金属-氧化物-半导体(CMOS)晶体管为例。但需要说明的是,本发明的制造方法还可以用于其它半导体器件。
参考图2,提供基底(未标示)。
所述基底用于为后续形成器件提供工艺平台。所述基底的材料为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟;所述基底还可以为绝缘体上的硅衬底、绝缘体上的锗衬底或绝缘体上的锗化硅衬底。本实施例中,所述基底为硅基底。
在本实施例中,在所述提供基底的步骤中,所述基底包括用于形成N型晶体管的第一区域Ⅰ、以及用于形成P型晶体管的第二区域Ⅱ,且所述第一区域Ⅰ和第二区域II为相邻区域。
在其他实施例中,所述基底也可以仅用于形成N型器件,或者仅用于形成P型器件。在其他实施例中,所述第一区域Ⅰ和第二区域II也可以相隔。
继续参考图2,刻蚀所述基底,形成衬底100以及位于衬底100上的鳍部140。
具体地,所述刻蚀基底,形成衬底100以及位于衬底100上的鳍部140的步骤包括:在所述基底上形成硬掩膜层110;以所述硬掩膜层110为掩膜对所述基底进行刻蚀,形成衬底100以及位于衬底100上的鳍部140。
硬掩膜层110在刻蚀基底形成鳍部140的过程中起掩膜作用。此外,所述硬掩膜层110还可以在后续离子掺杂过程中起到保护鳍部140的作用,或者,在平坦化工艺中能够起到保护所述鳍部140的作用。
在本实施例中,所述硬掩膜层110的材料为氮化硅。
形成所述硬掩膜层110的工艺步骤包括:在所述基底上形成初始硬掩膜(未示出);在所述初始硬掩膜表面形成图形化的光刻胶层(未示出);以所述图形化的光刻胶层为掩膜刻蚀所述初始硬掩膜,在基底表面形成硬掩膜层110;去除所述图形化的光刻胶层。在其他实施例中,所述硬掩膜层的形成工艺还能够包括:自对准双重图形化(SADP,Self-alignedDouble Patterned)工艺、自对准三重图形化(Self-aligned Triple Patterned)工艺、或自对准四重图形化(Self-aligned Double Double Patterned)工艺。所述双重图形化工艺包括LELE(Litho-Etch-Litho-Etch)工艺或LLE(Litho-Litho-Etch)工艺。
本实施例中,所述鳍部140包括:形成于第一区域Ⅰ衬底100上的第一鳍部120和形成于第二区域II衬底100上的第二鳍部130。
需要说明的是,本实施例中,所述制造方法还包括:在形成位于衬底上的鳍部140之后,形成隔离膜之前,在所述鳍部140的侧面和鳍部140之间的衬底上形成线性氧化层(Liner oxide)150。
由于鳍部140为通过刻蚀基底形成,所述鳍部140通常具有凸出的棱角且表面具有缺陷。本实施例对鳍部140进行氧化处理形成线性氧化层150,在氧化处理过程中,由于鳍部140凸出的棱角部分的比表面积更大,更容易被氧化,后续去除所述线性氧化层150之后,不仅鳍部140表面的缺陷层被去除,且凸出棱角部分也被去除,使鳍部140的表面光滑,晶格质量得到改善,避免鳍部140尖端放电问题。并且,形成的线性氧化层150还有利于提高后续形成的隔离层与鳍部140之间的界面性能。
本实施例中,由于所述鳍部140的材料为硅,相应形成的线性氧化层150的材料为氧化硅。
需要说明的是,若线性氧化层150的厚度过薄,也就是说鳍部140凸出的棱角部分和鳍部140的表面缺陷没有完全形成线性氧化层150,后续去除线性氧化层150的步骤中,难以将鳍部140表面的缺陷层和凸出棱角部分一并去除,从而不能起到光滑鳍部140的表面、改善晶格质量的作用,进而难以改善鳍部140尖端放电的问题。由于线性氧化层150是通过对鳍部140进行氧化处理形成,若线性氧化层150的厚度过厚,则会过度消耗鳍部140,从而降低晶体管的性能。因此,本实施例中,形成的线性氧化层150的厚度为
参考图3,在所述鳍部140之间的衬底100上形成隔离膜160。
所述隔离膜160为后续形成隔离层提供工艺基础;所述隔离膜160的材料为绝缘材料,例如为氧化硅、氮化硅或氮氧化硅。本实施例中,所述隔离膜160的材料为氧化硅。
为了提高形成隔离膜160工艺的填孔(gap-filling)能力,采用流动性化学气相沉积(FCVD,Flowable CVD)或高纵宽比化学气相沉积工艺(HARP CVD),形成所述隔离膜160。
具体地,形成所述隔离膜160的工艺步骤包括:在所述线性氧化层150表面形成隔离膜160,所述隔离膜160顶部高于硬掩膜层110顶部;平坦化工艺去除高于硬掩膜层110顶部的隔离膜160。
需要说明的是,在所述平坦化工艺过程中,位于鳍部140顶部的硬掩膜层110可以起到保护鳍部140顶部的作用。
参考图4,去除部分厚度的所述隔离膜160(参考图3),形成初始隔离层170,所述初始隔离层170顶部表面低于所述鳍部140顶部表面。
本实施例中,去除部分厚度的所述隔离膜160(参考图3),形成初始隔离层170的目的是使初始隔离层170的顶部与鳍部140掺杂位置相对应,这样在对初始隔离层170进行离子注入后,离子可以扩散至鳍部140的掺杂位置处。
本实施例中,初始隔离层170的材料为氧化硅。本实施例中,采用SiCoNi刻蚀工艺进行去除步骤。具体地,所述SiCoNi刻蚀工艺的步骤包括:以氦气作为稀释气体,三氟化氮和氨气作为反应气体以生成刻蚀气体;通过刻蚀气体去除部分厚度的所述隔离膜160,形成副产物;进行退火工艺,将所述副产物升华分解为气态产物;通过抽气方式去除所述气态产物。
需要说明的是,本实施例中,所述线性氧化层150的材料也为氧化硅。在去除部分厚度的隔离膜160过程中,还刻蚀去除部分厚度的线性氧化层150,使得剩余线性氧化层150顶部与初始隔离层170顶部齐平。
为了保证所述初始隔离层170至少暴露出所述硬掩膜层110,且后续离子掺杂工艺中,掺杂离子能掺入到所需要的鳍部140位置,以达到调控晶体管性能的目的,本实施例中,形成初始隔离层170的步骤中,所述初始隔离层170顶部表面比鳍部140顶部表面低
具体地,为了达到上述去除量的要求,保证所述初始隔离层170至少暴露出所述硬掩膜层110和部分鳍部140,同时为了后续形成满足厚度要求的隔离层,所述刻蚀工艺参数需控制在合理范围内。本实施例中,所述SiCoNi刻蚀工艺的工艺参数包括:氦气的气体流量为600sccm至2000sccm,三氟化氮的气体流量为20sccm至200sccm,氨气的气体流量为100sccm至500sccm,腔室压强为0.01Torr至50Torr,工艺时间为20S至300S。在其他实施例中,还可以采用干法刻蚀工艺、湿法刻蚀工艺、或干法刻蚀和湿法刻蚀相结合的工艺,刻蚀去除部分厚度的隔离膜。
参考图5至图6,对所述初始隔离层170进行离子掺杂。
对初始隔离层170进行离子掺杂,通过掺杂离子横向扩散到鳍部140的方式掺杂鳍部140,可以有效保护鳍部140在进行离子掺杂步骤中免遭损伤,避免了因鳍部140损伤造成晶体管性能衰减现象的发生,提高了晶体管的稳定性。
本实施例中,采用沿垂直于衬底100表面方向对初始隔离层170进行离子注入,以实现对初始隔离层170的掺杂,从而可以避免因凸出的鳍部140造成离子注入阴影效应的发生,防止无法对鳍部140进行有效离子掺杂的现象发生,从而可以有效准确地对鳍部140进行掺杂,提高晶体管的电学性能。在其他实施例中,还可以通过与衬底表面法线夹角较小(小于5°)的方向对初始隔离层进行掺杂,也能够减小离子注入阴影效应问题。
需要说明的是,在进行离子注入的过程中,位于鳍部140顶部的硬掩膜层110可以起到保护鳍部140顶部的作用,进一步减少离子注入对鳍部140的损伤。
本实施例中,所述掺杂离子为调整鳍式场效应晶体管阈值电压的离子。向所述初始隔离层170中注入的掺杂离子与所形成的晶体管的类型相反。具体地说,当晶体管为N型晶体管时,所述掺杂离子为P型离子,例如:掺杂离子为B离子;当晶体管为P型晶体管时,所述掺杂离子为N型离子,例如所述掺杂离子为P离子或As离子。
具体地,参考图5,沿垂直于衬底100表面方向第一区域Ⅰ衬底100上的初始隔离层170进行离子注入,所述离子注入的离子源为BF2,离子注入的能量范围为2-35keV,剂量范围为1.0E13-5.0E14atm/cm2;或者,所述离子注入的离子源为B,离子注入的能量范围为1-15keV,剂量范围为1.0E13-5.0E14atm/cm2。
需要说明的是,在对第一区域Ⅰ进行离子注入之前,形成遮挡第二区域Ⅱ并露出第一区域Ⅰ的第一阻挡层(图未示),以所述第一阻挡层为掩膜对第一区域Ⅰ的初始隔离层170进行离子注入。
参考图6,沿垂直于衬底100表面方向第二区域Ⅱ衬底100上的初始隔离层170进行离子注入,所述离子注入的离子源为P,离子注入的能量范围为2-25keV,剂量范围为1.0E13-5.0E14atm/cm2;或者,所述离子注入的离子源为As,离子注入的能量范围为5-40keV,剂量范围为1.0E13-5.0E14atm/cm2。
需要说明的是,在对第二区域Ⅱ进行离子注入之前,形成遮挡第一区域Ⅰ并露出第二区域Ⅱ的第二阻挡层(图未示),以所述第二阻挡层为掩膜对第二区域Ⅱ的初始隔离层170进行离子注入。
需要说明的是,本实施例在离子掺杂之后,去除硬掩膜层110之前,还进行退火工艺处理。
经所述退火工艺处理后,掺杂离子弛豫至晶格位,从而实现激活,更加容易和有效地扩散到鳍部140。通过退火工艺可以使离子实现横向(沿平行于衬底100表面的方向)扩散和纵向(沿垂直于衬底100表面的方向)扩散,进而实现调整晶体管阈值电压的目的、优化了晶体管的性能。
所述退火工艺可以是炉管退火、快速退火或尖峰退火。本实施例中,进行退火工艺处理的步骤包括:采用尖峰退火的方式进行退火工艺处理。具体的工艺参数为:所述退火工艺的温度为950-1100℃,退火时间为0-30s。
需要说明的是,在其他实施例中,可以不设置退火工艺处理。因为在初始隔离层中注入离子后,即使不进行退火初始隔离层中的离子会扩散至相邻鳍部中。
参考图8,去除所述硬掩膜层110(参考图7)。
本实施例中,所述硬掩膜层110的材料为氮化硅。去除掩膜层110的工艺为湿法刻蚀工艺,且刻蚀液包括磷酸。其中,所述磷酸用于去除氮化硅材料的掩膜层110,同时,由于鳍部140暴露出的侧壁140表面具有线性氧化层150,所述鳍部140不容易受到磷酸溶液刻蚀的损害,能够保证所述鳍部140结构和形貌的完整性和尺寸的精确性,从而可以使形成的晶体管具有较高的稳定性。
参考图9,去除部分厚度的所述初始隔离层170(参考图8),形成隔离层180。
通过此次去除工艺,可以使最终形成的隔离层180达到预设厚度,获得实现鳍部140之间有效隔离的隔离层180。
本实施例中,采用SiCoNi刻蚀工艺进行去除步骤。所述SiCoNi刻蚀工艺的步骤包括:以氦气作为稀释气体,三氟化氮和氨气作为反应气体以生成刻蚀气体;通过刻蚀气体去除部分厚度的所述初始隔离层170(参考8),形成副产物;进行退火工艺,将所述副产物升华分解为气态产物;通过抽气方式去除所述气态产物。
具体地,所述SiCoNi刻蚀工艺的工艺参数包括:氦气的气体流量为600sccm至2000sccm,三氟化氮的气体流量为20sccm至200sccm,氨气的气体流量为100sccm至500sccm,腔室压强为0.01Torr至50Torr,工艺时间为20S至500S。
在其他实施例中,还可以采用干法刻蚀工艺、湿法刻蚀工艺、或干法刻蚀和湿法刻蚀相结合的工艺,刻蚀去除部分厚度的初始隔离层隔离膜。
所述鳍式场效应晶体管的制造方法还包括:形成横跨鳍部140侧壁和顶部的栅极结构,以及在栅极结构两侧的鳍部中形成源漏掺杂区。所述步骤不再赘述。
本实施例形成的鳍式场效应晶体管,由于鳍部140未在离子掺杂过程中受到过多损伤,且对初始隔离层170进行离子掺杂,减少了凸出鳍部140造成阴影效应的发生,因此,本实施例形成的鳍式场效应晶体管电学性能优良,稳定性高。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (20)
1.一种鳍式场效应晶体管的制造方法,其特征在于,包括:
提供基底;
刻蚀所述基底,形成衬底以及位于衬底上的鳍部;
在所述鳍部之间的衬底上形成隔离膜;
去除部分厚度的所述隔离膜,形成初始隔离层,所述初始隔离层顶部表面低于所述鳍部顶部表面;
对所述初始隔离层进行离子掺杂;
去除部分厚度的所述初始隔离层,形成隔离层。
2.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,对所述初始隔离层进行离子掺杂的步骤包括:沿垂直于衬底表面方向对所述初始隔离层进行离子掺杂。
3.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,对所述初始隔离层进行离子掺杂的步骤中,所述掺杂离子为调整鳍式场效应晶体管阈值电压的离子。
4.如权利要求3所述的鳍式场效应晶体管的制造方法,其特征在于,所述晶体管为N型晶体管,所述掺杂离子为B离子;
或者,所述晶体管为P型晶体管,所述掺杂离子为P离子或As离子。
5.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,刻蚀所述基底,形成衬底以及位于衬底上的鳍部的步骤包括:在所述基底上形成硬掩膜层;以所述硬掩膜层为掩膜对所述基底进行刻蚀,形成衬底以及位于衬底上的鳍部;
所述制造方法在对所述初始隔离层进行离子掺杂的步骤之后,形成隔离层的步骤之前还包括:去除所述硬掩膜层。
6.如权利要求5所述的鳍式场效应晶体管的制造方法,其特征在于,所述硬掩膜层的材料为氮化硅。
7.如权利要求5所述的鳍式场效应晶体管的制造方法,其特征在于,所述制造方法还包括:在离子掺杂之后,去除硬掩膜层之前,进行退火工艺处理。
8.如权利要求7所述的鳍式场效应晶体管的制造方法,其特征在于,所述进行退火工艺处理的步骤包括:采用尖峰退火、快速退火或炉管退火的方式进行退火工艺处理。
9.如权利要求7所述的鳍式场效应晶体管的制造方法,其特征在于,所述进行退火工艺处理的步骤包括:所述退火工艺为尖峰退火,所述退火工艺的温度为950-1100℃,退火时间为0-30s。
10.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,所述对初始隔离层进行离子掺杂的步骤包括:采用离子注入的方式对初始隔离层进行离子掺杂。
11.如权利要求10所述的鳍式场效应晶体管的制造方法,其特征在于,所述离子注入的离子源为BF2,离子注入的能量范围为2-35keV,剂量范围为1.0E13-5.0E14atm/cm2;
或者,所述离子注入的离子源为B,离子注入的能量范围为1-15keV,剂量范围为1.0E13-5.0E14atm/cm2。
12.如权利要求10所述的鳍式场效应晶体管的制造方法,其特征在于,所述离子注入的离子源为P,离子注入的能量范围为2-25keV,剂量范围为1.0E13-5.0E14atm/cm2;
或者,所述离子注入的离子源为As,离子注入的能量范围为5-40keV,剂量范围为1.0E13-5.0E14atm/cm2。
13.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,去除部分厚度的隔离膜,形成初始隔离层的步骤中,所述初始隔离层顶部表面比鳍部顶部表面低
14.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,去除部分厚度的初始隔离层,形成隔离层的步骤中,所述隔离层顶部表面比鳍部顶部表面低
15.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,所述去除部分厚度的隔离膜形成初始隔离层的步骤,或者,所述去除部分厚度的初始隔离层形成隔离层的步骤包括:采用SiCoNi刻蚀工艺进行去除步骤。
16.如权利要求15所述的鳍式场效应晶体管的制造方法,其特征在于,所述去除部分厚度的隔离膜,形成初始隔离层的步骤中,SiCoNi刻蚀工艺的工艺参数包括:氦气的气体流量为600sccm至2000sccm,三氟化氮的气体流量为20sccm至200sccm,氨气的气体流量为100sccm至500sccm,腔室压强为0.01Torr至50Torr,工艺时间为20s至300s。
17.如权利要求15所述的鳍式场效应晶体管的制造方法,其特征在于,所述去除部分厚度的初始隔离层,形成隔离层的步骤中,SiCoNi刻蚀工艺的工艺参数包括:氦气的气体流量为600sccm至2000sccm,三氟化氮的气体流量为20sccm至200sccm,氨气的气体流量为100sccm至500sccm,腔室压强为0.01Torr至50Torr,工艺时间为20s至500s。
18.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,所述基底包括用于形成N型晶体管的第一区域,以及用于形成P型晶体管的第二区域;
对所述初始隔离层进行离子掺杂的步骤包括:对第一区域的初始隔离层进行B离子掺杂;在对第一区域的隔离层进行B离子掺杂之后,对第二区域的初始隔离层进行P、As离子掺杂。
19.如权利要求1所述的鳍式场效应晶体管的制造方法,其特征在于,所述制造方法还包括:在形成位于衬底上的鳍部之后,形成隔离膜之前,在所述鳍部的侧面和鳍部之间的衬底上形成线性氧化层。
20.如权利要求19所述的鳍式场效应晶体管的制造方法,其特征在于,所述线性氧化层的厚度为
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CN105845573A (zh) * | 2015-01-14 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | 一种FinFET器件及其制造方法、电子装置 |
Cited By (2)
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CN110649025A (zh) * | 2018-06-26 | 2020-01-03 | 华邦电子股份有限公司 | 存储器装置的形成方法 |
CN110649025B (zh) * | 2018-06-26 | 2023-08-08 | 华邦电子股份有限公司 | 存储器装置的形成方法 |
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