CN107887388A - Transistor arrangement, memory cell, memory array and preparation method thereof - Google Patents
Transistor arrangement, memory cell, memory array and preparation method thereof Download PDFInfo
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- CN107887388A CN107887388A CN201711205230.1A CN201711205230A CN107887388A CN 107887388 A CN107887388 A CN 107887388A CN 201711205230 A CN201711205230 A CN 201711205230A CN 107887388 A CN107887388 A CN 107887388A
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- conductive layer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 42
- 238000002955 isolation Methods 0.000 claims abstract description 159
- 238000005530 etching Methods 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 392
- 239000000463 material Substances 0.000 claims description 41
- 239000011241 protective layer Substances 0.000 claims description 39
- 239000007789 gas Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 25
- 238000000926 separation method Methods 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 19
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000000460 chlorine Substances 0.000 claims description 12
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 9
- 229910052801 chlorine Inorganic materials 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 6
- 229910003828 SiH3 Inorganic materials 0.000 claims description 6
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical compound [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 125000002147 dimethylamino group Chemical group [H]C([H])([H])N(*)C([H])([H])[H] 0.000 claims description 6
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 125000001339 silanediyl group Chemical group [H][Si]([H])(*)* 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 241001012508 Carpiodes cyprinus Species 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000035484 reaction time Effects 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 238000004347 surface barrier Methods 0.000 claims 1
- 230000000052 comparative effect Effects 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- -1 silicon Alkane Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of preparation method of transistor arrangement, is included in Semiconductor substrate and forms a plurality of grid conducting layers, and forms isolation structure and bolt conductive layer in the side wall of grid conducting layer and upper surface；The first etching is carried out to bolt conductive layer, the apical side height of bolt conductive layer is less than or equal to the apical side height of isolation structure；Bolt conduction definition layer is formed in the exposed sidewall of isolation structure and upper surface, and the second etching is carried out to bolt conductive layer, to form isolation channel；Sacrifice layer is formed in the second side of bolt conductive layer；In formation bolt conductive isolation layer in isolation channel；Thickness amendment is carried out to structure described in previous step, to expose bolt conductive layer；3rd etching is carried out to bolt conductive layer and sacrifice layer, to form depression；Metal pedestal layer is filled in depression, to form the source drain of transistor arrangement.Solved by the present invention because gap in polysilicon being present, cause metal pedestal layer uneven, make intersheathes resistance value higher, the problem of influenceing electric conductivity.
Description
Technical field
The invention belongs to semiconductor devices production field, more particularly to a kind of transistor arrangement, memory cell, memory
Array and preparation method thereof.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made up of the memory cell of many repetitions.Each memory cell mainly by a transistor and by
The capacitor of transistor manipulation is formed, wherein, transistor forms conductive channel by bolt conductive layer and the capacitor, with control
Make the capacitor.
It is well known that the electrical conduction ability of bolt conductive layer is to determine the key parameter of the memory cell performance, and metal
Bed course is then the key for determining the bolt conductive layer electrical conduction ability；And existing bolt conductive layer is in preparation process, its dielectric
Layer material typically uses polycrystalline silicon material, and by being performed etching to the polysilicon, depression is formed, to form follow-up gold
Belong to bed course；But due to having excessive gap when polysilicon generates in structure, cause the side wall out-of-flatness of silicon nitride formed afterwards, enter
And cause the metal pedestal layer that is subsequently formed uneven, and the resistance value for ultimately resulting in metal pedestal layer is higher.
In consideration of it, it is necessary to design a kind of new transistor arrangement, memory cell, memory array and preparation method thereof use
To solve above-mentioned technical problem.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of transistor arrangement, storage are single
Member, memory array and preparation method thereof, for solving in the prior art because gap be present in polysilicon, cause what is be subsequently formed
Metal pedestal layer is uneven, and then causes metal pedestal layer resistance value higher, the problem of influenceing electric conductivity.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of transistor arrangement, described
Preparation method includes：
Step 1) sets a plurality of grid conducting layers on a semiconductor substrate, and in the sidewall surfaces of the grid conducting layer
And upper surface forms isolation structure, and bolt conductive layer, and the adjacent Gate Electrode Conductive are more formed between the adjacent isolation structure
The bolt conductive layer between layer is connected with each other on the fleet plough groove isolation structure of the Semiconductor substrate, wherein, the bolt is led
The thickness of electric layer is more than the height of the isolation structure；
Step 2) carries out first to the bolt conductive layer and etched, and the apical side height of the bolt conductive layer is less than after the first etching
Equal to the apical side height of the isolation structure, the isolation structure isolates the first side of the bolt conductive layer；
Step 3) forms bolt conduction definition layer in the exposed sidewall surface of the isolation structure and upper surface, and to described
The bolt conductive layer on fleet plough groove isolation structure carries out the second etching, to form isolation channel, wherein, the isolation channel isolates institute
State the second side of bolt conductive layer；
Step 4) forms a sacrifice layer in the second side of the bolt conductive layer；
Step 5) in forming a bolt conductive isolation layer in the isolation channel, wherein, it is conductive that the sacrifice layer isolates the bolt
Separation layer and the bolt conductive layer, so that the bolt conductive isolation layer is not directly contacted with second side of the bolt conductive layer
Face；
Step 6) carries out thickness amendment to structure step 5) described, to expose the bolt conductive layer；
Step 7) carries out the 3rd etching to the bolt conductive layer and the sacrifice layer so that the bolt is conductive after the 3rd etching
The apical side height of layer is less than the apical side height of the isolation structure after thickness amendment, and conductive less than the bolt after thickness amendment
The apical side height of separation layer, to form depression；And
Step 8) fills metal pedestal layer in the depression, to form the source drain of the transistor arrangement.
Preferably, the isolation structure in step 1) includes sequentially forming the first protective layer, separation layer and the second protection
Layer；After step 2), the apical side height of the bolt conductive layer is described the still greater than on the grid conducting layer after the first etching
The apical side height of one protective layer；After step 7), the apical side height of the bolt conductive layer is still greater than the grid after the 3rd etching
The height of conductive layer.
Preferably, sacrifice layer described in step 4) is more formed at sidewall surfaces and the upper surface of the bolt conduction definition layer.
Preferably, when the second side of the bolt conductive layer has side relative to the first side compared with out-of-flatness
Edge gap, the middle sacrifice layer formed of step 4) are filled in the edge slot, can sacrifice prominent structure to be formed；Step 7)
In, while remove the prominent structure.
Preferably, the sacrifice layer is formed using atomic layer deposition process in step 4)；The thickness of the sacrifice layer is between 4nm
~6nm；The material of the sacrifice layer includes silica (SiO2)。
Preferably, forming the reacting gas of the sacrifice layer includes SiH3N(C3H7)2、SiH[N(CH3)2]3, hexachloroethanc silicon
Alkane (Si2Cl6)、SiH2(NHtBu)2Or H2Si[N(C2H5)2]2With nitrogen (N2) and oxygen (O2) mixed gas；Wherein, SiH3N
(C3H7)2、SiH[N(CH3)2]3、Si2Cl6、SiH2(NHtBu)2Or H2Si[N(C2H5)2]2Gas flow for 0.2slm~
1slm, the gas flow of the nitrogen are 3slm~30slm, and the gas flow of the oxygen is 3slm~10slm, described in formation
During sacrifice layer, reaction temperature is 20 DEG C~80 DEG C, and reaction pressure be normal pressure~1500mtorr, the reaction time for 3min~
60min。
Preferably, the bolt conductive layer and the sacrifice layer are etched using dry etch process in step 7)；Etch period
For 5sec~15sec；Remove the thickness of the bolt conductive layer includes hydrogen bromide between 10nm~40nm, the reacting gas
And chlorine (Cl (HBr)2) mixed gas, the hydrogen bromide (HBr) and chlorine (Cl2) total gas couette of mixed gas is
10sccm~50sccm；Wherein, the gas flow of the hydrogen bromide (HBr) is 5sccm~30sccm, the chlorine (Cl2)
Gas flow is 5sccm~30sccm.
Preferably, the thickness of the bolt conductive layer formed in step 1) is between 120nm~170nm；In step 2)
Except the thickness of the bolt conductive layer is between 30nm~60nm.
Preferably, first protective layer, the separation layer, second protection are formed using chemical vapor deposition method
Layer, the bolt conductive layer, the bolt conduction definition layer and the bolt conductive isolation layer, the metal is formed using sputtering technology
Bed course；Wherein, first protective layer, second protective layer, the bolt conduction definition layer and the bolt conductive isolation layer
Material includes silicon nitride (SiN)；The insolated layer materials include silica (SiO2)；The material of the bolt conductive layer includes more
Crystal silicon；The material of the metal pedestal layer includes tungsten (W) or aluminium (Al).
Preferably, before the preparation method is also included in step 1), the step of active area is formed in the Semiconductor substrate
Suddenly, the step of and in the active area forming the fleet plough groove isolation structure and notched gates.
Preferably, the forming method of the fleet plough groove isolation structure includes：
Step 11a) there is the first etching barrier layer of the first etching window in active area upper surface formation one, its
In, the position of first etching window is corresponding with the position longitudinal direction of the fleet plough groove isolation structure；
Step 12a) active area is performed etching by first etching window, to form the first groove；And
Step 13a) in first groove packed layer is formed, to form the fleet plough groove isolation structure；
The forming method of the notched gates includes：
Step 11b) there is the second etching barrier layer of the second etching window in active area upper surface formation one, its
In, the position of second etching window is corresponding with the position longitudinal direction of the notched gates；
Step 12b) active area is performed etching by second etching window, to form the second groove；
Step 13b) in one barrier layer of inner wall surface formation of second groove；And
Step 14b) in being sequentially filled conductive layer and insulating barrier in second groove.
Present invention also offers a kind of transistor arrangement, including：
A plurality of grid conducting layers, set on a semiconductor substrate；
Isolation structure, it is formed at sidewall surfaces and the upper surface of the grid conducting layer；
Bolt conductive layer, set on the semiconductor substrate, and be formed between the adjacent isolation structure, the isolation
Structure isolates the first side of the bolt conductive layer, and the bolt conductive layer is on the fleet plough groove isolation structure of the Semiconductor substrate
Isolation channel is formed, the isolation channel isolates the second side of the bolt conductive layer；
Sacrifice layer, it is formed at the second side of the bolt conductive layer；
Bolt conductive isolation layer, be formed in the isolation channel, wherein, the sacrifice layer isolate the bolt conductive isolation layer and
The bolt conductive layer, so that the bolt conductive isolation layer is not directly contacted with the second side of the bolt conductive layer；Wherein, institute
The apical side height for stating bolt conductive layer is less than the apical side height of the isolation structure after thickness amendment, and less than described in thickness amendment
The apical side height of bolt conductive isolation layer, to form depression；And
Metal pedestal layer, filling are formed in the depression.
Preferably, the isolation structure includes sequentially forming the first protective layer, separation layer and the second protective layer, and described the
One protective layer and the separation layer are sequentially formed in the grid conducting layer sidewall surfaces and upper surface；Second protective layer,
It is formed at the separation layer sidewall surfaces.
Preferably, the material of the sacrifice layer includes silica (SiO2), the thickness of the sacrifice layer is between 4nm~6nm.
Preferably, the material of first protective layer, second protective layer and the bolt conductive isolation layer includes nitrogen
SiClx (SiN)；The insolated layer materials include silica (SiO2)；The material of the bolt conductive layer includes polysilicon；The gold
The material of category bed course includes tungsten (W) or aluminium (Al).
Preferably, the transistor arrangement also includes the active area being formed in the Semiconductor substrate, and is formed at institute
State the fleet plough groove isolation structure and the notched gates in active area；Wherein,
The fleet plough groove isolation structure includes：The first groove for being formed in the active area and it is formed at described
Packed layer in one groove；
The notched gates include：The second groove for being formed in the active area, it is formed at the second groove inner wall table
The barrier layer in face and it is sequentially filled in conductive layer and insulating barrier in second groove.
Present invention also offers a kind of preparation method of memory cell, the preparation method of the memory cell includes：
Step S1：Transistor arrangement prepared by one preparation method as described above is provided；And
Step S2：Capacitance structure is formed above the metal pedestal layer of the transistor arrangement, to form memory cell.
Present invention also offers a kind of memory cell, the memory cell includes：
Transistor arrangement as described above；And
The capacitance structure being formed above the metal pedestal layer of the transistor arrangement.
Present invention also offers a kind of memory array, the memory array includes a plurality of storages as described above
Unit.
As described above, the transistor arrangement of the present invention, memory cell, memory array and preparation method thereof, have following
Beneficial effect：The present invention forms a sacrifice layer by the sidewall surfaces in bolt conductive layer so that the sacrifice layer fills the bolt
The edge slot of conductive layer edge directly removes the prominent structure by etching technics to form prominent structure,
So that the metal pedestal layer surfacing being subsequently formed, and then the resistance value of metal pedestal layer is reduced, improve the metal pedestal layer
Conductive capability.
Brief description of the drawings
Fig. 1 is shown as the flow chart of transistor arrangement preparation method described in the embodiment of the present invention one.
Fig. 2 a are shown as the structural representation of substrate when the embodiment of the present invention one prepares the transistor arrangement.
Fig. 2 b are shown as being formed isolation structure and bolt conductive layer when the embodiment of the present invention one prepares the transistor arrangement
Structural representation.
Fig. 2 c are shown as etching the structural representation of bolt conductive layer when the embodiment of the present invention one prepares the transistor arrangement.
The structure that Fig. 2 d are shown as being formed bolt conduction definition layer when the embodiment of the present invention one prepares the transistor arrangement is shown
It is intended to.
Fig. 2 e are shown as being formed the structural representation of isolation channel when the embodiment of the present invention one prepares the transistor arrangement.
Fig. 2 f are shown as being formed the structural representation of sacrifice layer when the embodiment of the present invention one prepares the transistor arrangement.
The structure that Fig. 2 g are shown as being formed bolt conductive isolation layer when the embodiment of the present invention one prepares the transistor arrangement is shown
It is intended to.
Fig. 2 h are shown as the structure of exposure bolt conductive layer after etching when the embodiment of the present invention one prepares the transistor arrangement
Schematic diagram.
Fig. 2 i are shown as being formed the structural representation of depression when the embodiment of the present invention one prepares the transistor arrangement.
Fig. 2 j are shown as being formed the structural representation of metal pedestal layer when the embodiment of the present invention one prepares the transistor arrangement.
Fig. 3 a are shown as when comparative example of the present invention prepares the transistor arrangement in formation isolation in Semiconductor substrate
The structural representation of structure and bolt conductive layer.
Fig. 3 b are shown as etching the structural representation of bolt conductive layer when comparative example of the present invention prepares the transistor arrangement
Figure.
Fig. 3 c are shown as being formed the structure of bolt conduction definition layer when comparative example of the present invention prepares the transistor arrangement
Schematic diagram.
Fig. 3 d are shown as being formed the structural representation of isolation channel when comparative example of the present invention prepares the transistor arrangement.
Fig. 3 e are shown as being formed the structure of bolt conductive isolation layer when comparative example of the present invention prepares the transistor arrangement
Schematic diagram.
Fig. 3 f are shown as the knot of exposure bolt conductive layer after etching when comparative example of the present invention prepares the transistor arrangement
Structure schematic diagram.
Fig. 3 g are shown as being formed the structural representation of depression when comparative example of the present invention prepares the transistor arrangement.
Fig. 3 h are shown as being formed the structural representation of metal pedestal layer when comparative example of the present invention prepares the transistor arrangement
Figure.
Fig. 4 is shown as the flow chart that the embodiment of the present invention two prepares the memory cell.
Fig. 5 is shown as the structural representation of memory cell described in the embodiment of the present invention two.
Component label instructions
10 memory cell
100th, 200 transistor arrangement
101st, 201 Semiconductor substrate
102 active areas
103 fleet plough groove isolation structures
104 first grooves
105 packed layers
106 notched gates
107 second grooves
108 barrier layers
109 conductive layers
110 insulating barriers
111st, 211 grid conducting layer
112nd, 212 isolation structure
113rd, 213 first protective layer
114th, 214 separation layer
115th, 215 second protective layer
116th, 216 bolt conductive layer
117th, 217 edge slot
118th, 218 bolt conduction definition layer
119th, 219 isolation channel
120 sacrifice layers
121st, 221 structure is protruded
122nd, 222 bolt conductive isolation layer
123rd, 223 depression
124th, 224 metal pedestal layer
300 capacitance structures
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Fig. 5.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in figure 1, the present embodiment provides a kind of preparation method of transistor arrangement, the preparation method includes：
Step 1) sets a plurality of grid conducting layers 111 in Semiconductor substrate 101, and in the grid conducting layer 111
Sidewall surfaces and upper surface formed isolation structure 112, more form bolt conductive layer 116 between the adjacent isolation structure 112,
And the bolt conductive layer 116 between the adjacent grid conducting layer 111 is connected with each other in the shallow ridges of the Semiconductor substrate 101
On recess isolating structure 103, wherein, the thickness of the bolt conductive layer 116 is more than the height of the isolation structure 112；
Step 2) carries out first to the bolt conductive layer 116 and etched, and the top surface of the bolt conductive layer 116 is high after the first etching
Degree is less than or equal to the apical side height of the isolation structure 112, and the isolation structure 112 isolates the first of the bolt conductive layer 116
Side；
Step 3) forms bolt conduction definition layer 118 in the exposed sidewall surface of the isolation structure 112 and upper surface, and right
The bolt conductive layer 116 on the fleet plough groove isolation structure 103 carries out the second etching, to form isolation channel 119, wherein, institute
State the second side that isolation channel 119 isolates the bolt conductive layer 116；
Step 4) forms a sacrifice layer 120 in the second side of the bolt conductive layer 116；
Step 5) forms a bolt conductive isolation layer 122 in the isolation channel 119, wherein, the sacrifice layer 120 isolates institute
Bolt conductive isolation layer 122 and the bolt conductive layer 116 are stated, is led so that the bolt conductive isolation layer 122 is not directly contacted with the bolt
The second side of electric layer 116；
Step 6) carries out thickness amendment to structure step 5) described, to expose the bolt conductive layer 116；
Step 7) carries out the 3rd etching to the bolt conductive layer 116 and the sacrifice layer 120 so that described after the 3rd etching
The apical side height of bolt conductive layer 116 is less than the apical side height of the isolation structure 112 after thickness amendment, and is less than thickness amendment
The apical side height of the bolt conductive isolation layer 122 afterwards, to form depression 123；And
Step 8) fills metal pedestal layer 124 in the depression 123, to form the source drain of the transistor arrangement.
Fig. 2 a to Fig. 2 j are referred to below the preparation method of transistor arrangement described in the present embodiment is described in detail.
As shown in Figure 2 a and 2 b, a plurality of grid conducting layers 111 are set in Semiconductor substrate 101, and in the grid
The sidewall surfaces of pole conductive layer 111 and upper surface form isolation structure 112, are more formed between the adjacent isolation structure 112
Bolt conductive layer 116, and the bolt conductive layer 116 between the adjacent grid conducting layer 111 is connected with each other in the semiconductor
On the fleet plough groove isolation structure 103 of substrate 101, wherein, the thickness of the bolt conductive layer 116 is more than the isolation structure 112
Highly.
As an example, as shown in Figure 2 a, before the preparation method is also included in step 1), in the Semiconductor substrate 101
The step of middle formation active area 102, and the fleet plough groove isolation structure 103 and notched gates 106 are formed in the active area 102
The step of.
Specifically, the forming method of the fleet plough groove isolation structure 103 includes：
Step 11a) there is the first etching barrier layer of the first etching window in the upper surface of active area 102 formation one,
Wherein, the position of first etching window is corresponding with the position longitudinal direction of the fleet plough groove isolation structure 103；
Step 12a) active area 102 is performed etching by first etching window, to form the first groove
104；And
Step 13a) packed layer 105 is formed in first groove 104, to form the fleet plough groove isolation structure 103；
Specifically, the forming method of the notched gates 106 includes：
Step 11b) there is the second etching barrier layer of the second etching window in the upper surface of active area 102 formation one,
Wherein, the position of second etching window is corresponding with the position longitudinal direction of the notched gates 106；
Step 12b) active area 102 is performed etching by second etching window, to form the second groove
107；
Step 13b) in one barrier layer 108 of inner wall surface formation of second groove 107；And
Step 14b) in being sequentially filled conductive layer 109 and insulating barrier 110 in second groove 107.
As an example, as shown in Figure 2 b, the grid conducting layer 111 is formed using chemical vapor deposition method, wherein, grid
The material of pole conductive layer 111 includes but is not limited to tungsten W, titanium nitride TiN or titanium Ti.
As an example, as shown in Figure 2 b, the isolation structure 112 include successively the first protective layer 113, separation layer 114 and
Second protective layer 115；Wherein, first protective layer 113, first protective layer are formed using chemical vapor deposition method
113 material includes but is not limited to silicon nitride SiN；The separation layer 114, the isolation are formed using chemical vapor deposition method
The material of layer 114 includes but is not limited to silicon oxide sio2；Second protective layer 115 is formed using gas-phase deposition, it is described
The material of second protective layer 115 includes but is not limited to silicon nitride SiN.
As an example, as shown in Figure 2 b, the bolt conductive layer 116 is formed using chemical vapor deposition method, the bolt is led
The thickness of electric layer 116 includes polysilicon (poly) between 120nm~170nm, the material of the bolt conductive layer 115.
As an example, as shown in Figure 2 b, the second side of the bolt conductive layer 116 relative to the first side compared with
Out-of-flatness and there is edge slot 117.
It should be noted that in vertical direction, the one side of the bolt conductive layer contacted with the isolation structure is
First side, the another side relative with the first side are second side.
As shown in Figure 2 c, carry out first to the bolt conductive layer 116 to etch, the bolt conductive layer 116 after the first etching
Apical side height is less than or equal to the apical side height of the isolation structure 112, and the isolation structure 112 isolates the bolt conductive layer 116
First side.
As an example, as shown in Figure 2 c, the apical side height of the bolt conductive layer 116 is still greater than in the grid after the first etching
The apical side height of first protective layer 113 on pole conductive layer 111.
Specifically, the first etching is carried out to the bolt conductive layer 116 using dry etch process, wherein, remove the bolt
The thickness of conductive layer 116 is between 30nm~60nm.
As shown in Figure 2 d, bolt conduction definition layer is formed in the exposed sidewall surface of the isolation structure 112 and upper surface
118。
As an example, the bolt conduction definition layer 118 is formed using chemical vapor deposition method, wherein, the bolt is conductive
The material of definition layer 118 includes but is not limited to silicon nitride SiN.
As shown in Figure 2 e, the second etching is carried out to the bolt conductive layer 116 on the fleet plough groove isolation structure 103, with
Isolation channel 119 is formed, wherein, the isolation channel 119 isolates the second side of the bolt conductive layer 116.
As an example, the isolation channel 119 is formed using dry etch process, so as to expose the bolt conductive layer 116
Whole edge slots 117 of second side.
As shown in figure 2f, a sacrifice layer 120 is formed in the second side of the bolt conductive layer 116.
As an example, the sacrifice layer 120 is filled in the edge slot 117, prominent structure 121 can be sacrificed to be formed.
It should be noted that the material of the material of the sacrifice layer and the bolt conductive layer has same or like etching
Than in order to described in subsequent etching during bolt conductive layer, while etching and removing the protrusion structure that the sacrifice layer is formed, avoid it
Influence the resistance value of metal pedestal layer.
As an example, the sacrifice layer 120 is formed using atomic layer deposition process, wherein, formed using atomic layer deposition process
During the sacrifice layer 120, reaction temperature is 20 DEG C~80 DEG C, and reaction pressure is normal pressure~1500mtorr, reaction time 3min
~60min；Reacting gas includes SiH3N(C3H7)2、SiH[N(CH3)2]3、Si2Cl6、SiH2(NHtBu)2Or H2Si[N
(C2H5)2]2With nitrogen N2And oxygen O2Mixed gas；Wherein, SiH3N(C3H7)2、SiH[N(CH3)2]3、Si2Cl6、SiH2
(NHtBu)2Or H2Si[N(C2H5)2]2Gas flow be 0.2slm~1slm, the gas flow of the nitrogen for 3slm~
30slm, the gas flow of the oxygen is 3slm~10slm.
As an example, the thickness of the sacrifice layer 120 is between 4nm~6nm；The material of the sacrifice layer 120 is included but not
It is limited to silicon oxide sio2。
As an example, as shown in figure 2f, the sacrifice layer be more formed at the bolt conduction definition layer 118 sidewall surfaces and
Upper surface.
As shown in Figure 2 g, in one bolt conductive isolation layer 122 of formation in the isolation channel 119, wherein, the sacrifice layer 120
Isolate the bolt conductive isolation layer 122 and the bolt conductive layer 116, so that the bolt conductive isolation layer 122 is not directly contacted with institute
State the second side of bolt conductive layer 116.
As an example, the bolt conductive isolation layer 122 is formed using chemical vapor deposition method, wherein, the bolt is conductive
The material of separation layer 122 includes but is not limited to silicon nitride SiN.
As shown in fig. 2h, thickness amendment is carried out to structure described in previous step, to expose the bolt conductive layer 116.
As an example, thickness amendment is carried out to said structure using dry etch process.
As shown in fig. 2i, the 3rd etching is carried out to the bolt conductive layer 116 and the sacrifice layer 120 so that the 3rd etching
The apical side height of the bolt conductive layer 116 is less than the apical side height of the isolation structure 112 after thickness amendment afterwards, and less than thickness
The apical side height of the bolt conductive isolation layer 122 after degree amendment, to form depression 123.
As an example, the prominent structure 121 is removed by the described 3rd etching simultaneously.
As an example, the apical side height of the bolt conductive layer 116 is still greater than the grid conducting layer 111 after the 3rd etching
Highly.
As an example, the bolt conductive layer 116 and the sacrifice layer 120 are etched using dry etch process；Etch period
For 5sec~15sec；Remove the thickness of the bolt conductive layer 116 includes hydrogen bromide between 10nm~40nm, the reacting gas
And chlorine (Cl (HBr)2) mixed gas, the hydrogen bromide (HBr) and chlorine (Cl2) total gas couette of mixed gas is
10sccm~50sccm；Wherein, the gas flow of the hydrogen bromide (HBr) is 5sccm~30sccm, the chlorine (Cl2)
Gas flow is 5sccm~30sccm.
As shown in figure 2j, metal pedestal layer 124 is filled in the depression 123, to form the source electrode of the transistor arrangement
Drain electrode.
As an example, the metal pedestal layer 124 is formed using sputtering technology, wherein, the material bag of the metal pedestal layer 124
Include tungsten (W) or aluminium (Al).
As shown in figure 2j, the transistor arrangement 100 includes the transistor arrangement prepared by above-mentioned preparation method：
A plurality of grid conducting layers 111, are arranged in Semiconductor substrate 101；
Isolation structure 112, it is formed at sidewall surfaces and the upper surface of the grid conducting layer 111；
Bolt conductive layer 116, be arranged in the Semiconductor substrate 101, and be formed at the adjacent isolation structure 112 it
Between, the isolation structure 112 isolates the first side of the bolt conductive layer 116, and the bolt conductive layer 116 serves as a contrast in the semiconductor
Isolation channel 119 is formed on the fleet plough groove isolation structure 103 at bottom 101, the isolation channel 119 isolates the of the bolt conductive layer 116
Two side faces；
Sacrifice layer 120, it is formed at the second side of the bolt conductive layer 116；
Bolt conductive isolation layer 122, it is formed in the isolation channel 119, wherein, the sacrifice layer 120 is isolated the bolt and led
Electricity isolated layer 122 and the bolt conductive layer 116, so that the bolt conductive isolation layer 122 is not directly contacted with the bolt conductive layer 116
The second side；Wherein, the apical side height of the bolt conductive layer 116 is less than the isolation structure 112 after thickness amendment
Apical side height, and less than the apical side height of the bolt conductive isolation layer 122 after thickness amendment, to form depression 123；And
Metal pedestal layer 124, filling are formed in the depression 123.
As an example, as shown in figure 2j, the transistor arrangement 100 also includes being formed in the Semiconductor substrate 101
Active area 102, and the fleet plough groove isolation structure 103 and notched gates 106 being formed in the active area 102；Wherein,
The fleet plough groove isolation structure 103 includes：The first groove 104 being formed in the active area 102 and formation
Packed layer 105 in first groove 104；
The notched gates 106 include：The second groove 107 for being formed in the active area 102, to be formed at described second recessed
The barrier layer 108 of the inner wall surface of groove 107 and it is sequentially filled in conductive layer 109 and insulating barrier in second groove 107
110。
As an example, as shown in figure 2j, the isolation structure 112 include successively the first protective layer 113, separation layer 114 and
Second protective layer 115, first protective layer 113 and the separation layer 114 are sequentially formed in the side wall of grid conducting layer 111
Surface and upper surface；Second protective layer 115 is formed at the sidewall surfaces of separation layer 114.
As an example, the material of the sacrifice layer 120 includes silica (SiO2), the thickness of the sacrifice layer 120 between
4nm~6nm.
As an example, first protective layer 113, second protective layer 115 and the bolt conductive isolation layer 122
Material includes silicon nitride (SiN)；The material of separation layer 114 includes silica (SiO2)；The material of the bolt conductive layer 116
Including polysilicon；The material of the metal pedestal layer 124 includes tungsten (W) or aluminium (Al).
Comparative example
The present embodiment provides a comparative example related to above-described embodiment one, refers to Fig. 3 a to Fig. 3 h below to this
The preparation method of transistor arrangement 200 illustrates described in embodiment.
As shown in Figure 3 a, a plurality of grid conducting layers 211 are set in Semiconductor substrate 201, and in the Gate Electrode Conductive
The sidewall surfaces of layer 211 and upper surface form isolation structure 212, and bolt conduction is more formed between the adjacent isolation structure 212
Layer 216, and the bolt conductive layer 216 between the adjacent grid conducting layer 211 is connected with each other；The bolt conductive layer 216
Thickness is more than the height of the isolation structure 212, and the isolation structure 212 includes the first protective layer 213, separation layer 214 and the
Two protective layers 215；Wherein, the second side of the bolt conductive layer 216 has relative to the first side compared with out-of-flatness
There is edge slot 217.
As shown in Figure 3 b, carry out first to the bolt conductive layer 216 to etch, the bolt conductive layer 216 after the first etching
Apical side height is less than or equal to the apical side height of the isolation structure 212, and the isolation structure 212 isolates the bolt conductive layer 216
First side.
As shown in Figure 3 c, bolt conduction definition layer is formed in the exposed sidewall surface of the isolation structure 212 and upper surface
218。
As shown in Figure 3 d, the second etching is carried out to the bolt conduction definition layer 218 and bolt conductive layer 216, to form isolation
Groove 219, wherein, the isolation channel 219 isolates the second side of the bolt conductive layer 216.
As shown in Figure 3 e, one is formed in the second side of the bolt conductive layer 216 and the surface of bolt conduction definition layer 218
Bolt conductive isolation layer 222, the bolt conductive isolation layer 222 are filled in the edge slot 217, to form prominent structure 221.
As illustrated in figure 3f, thickness amendment is carried out to structure described in previous step, to expose the bolt conductive layer 216.
As shown in figure 3g, the 3rd etching is carried out to the bolt conductive layer 216 so that the bolt conductive layer after the 3rd etching
216 apical side height is less than the apical side height of the isolation structure 212 after thickness amendment, and less than the bolt after thickness amendment
The apical side height of conductive isolation layer 222, to form depression 223.
As illustrated in figure 3h, metal pedestal layer 224 is filled in the depression 223, to form the source electrode of the transistor arrangement
Drain electrode.
It should be noted that because the material of the bolt conductive layer is polysilicon, the material of the bolt conductive isolation layer is
Silicon nitride, therefore when removing the polysilicon by etching, it can not remove because silicon nitride fills formed protrusion structure so that after
The continuous metal pedestal layer out-of-flatness formed, causes the resistance value of metal pedestal layer higher, and then influences the electric conductivity of the metal pedestal layer
Energy.And embodiment one in the bolt conductive layer sidewall surfaces due to forming silicon monoxide sacrifice layer so that the filling of prominent structure
Material is silica, when removing the polysilicon by etching, can directly go silicon to protrude structure, so that subsequently
The metal pedestal layer of formation is smooth, reduces metal pedestal layer resistance value, and then improve the electric conductivity of metal pedestal layer.
Embodiment two
As shown in figure 4, the present embodiment provides a kind of preparation method of memory cell, the preparation method of the memory cell 10
Including：
Step S1：The transistor arrangement 100 prepared just like preparation method described in embodiment one is provided；
Step S2：Capacitance structure 300 is formed above the metal pedestal layer 124 of the transistor arrangement 100, to form storage
Unit 10.
The memory cell prepared by above-mentioned preparation method is as shown in figure 5, the memory cell 10 includes：
One transistor arrangement 100；And
It is formed at the capacitance structure 300 of the top of the metal pedestal layer 124 of the transistor arrangement 100.
Embodiment three
The present embodiment provides a kind of memory array, and the memory array includes a plurality of depositing as described in embodiment two
Storage unit.
In summary, transistor arrangement of the invention, memory cell, memory array and preparation method thereof, have following
Beneficial effect：The present invention forms a sacrifice layer by the sidewall surfaces in bolt conductive layer so that the sacrifice layer fills the bolt
The edge slot of conductive layer edge directly removes the prominent structure by etching technics to form prominent structure,
So that the metal pedestal layer surfacing being subsequently formed, and then the resistance value of metal pedestal layer is reduced, improve the metal pedestal layer
Conductive capability.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (19)
1. a kind of preparation method of transistor arrangement, it is characterised in that the preparation method includes：
Step 1) sets a plurality of grid conducting layers on a semiconductor substrate, and in the grid conducting layer sidewall surfaces and on
Surface forms isolation structure, more forms bolt conductive layer between the adjacent isolation structure, and the adjacent grid conducting layer it
Between the bolt conductive layer be connected with each other on the fleet plough groove isolation structure of the Semiconductor substrate, wherein, the bolt conductive layer
Thickness be more than the isolation structure height；
Step 2) carries out first to the bolt conductive layer and etched, and the apical side height of the bolt conductive layer is less than or equal to after the first etching
The apical side height of the isolation structure, the isolation structure isolate the first side of the bolt conductive layer；
Step 3) forms bolt conduction definition layer in the exposed sidewall surface of the isolation structure and upper surface, and in the shallow ridges
The bolt conductive layer on recess isolating structure carries out the second etching, to form isolation channel, wherein, the isolation channel isolates the bolt
The second side of conductive layer；
Step 4) forms a sacrifice layer in the second side of the bolt conductive layer；
Step 5) in forming a bolt conductive isolation layer in the isolation channel, wherein, the sacrifice layer isolates the conductive isolation of the bolt
Layer and the bolt conductive layer, so that the bolt conductive isolation layer is not directly contacted with the second side of the bolt conductive layer；
Step 6) carries out thickness amendment to structure step 5) described, to expose the bolt conductive layer；
Step 7) carries out the 3rd etching to the bolt conductive layer and the sacrifice layer so that the bolt conductive layer after the 3rd etching
Apical side height is less than the apical side height of the isolation structure after thickness amendment, and less than the conductive isolation of the bolt after thickness amendment
The apical side height of layer, to form depression；And
Step 8) fills metal pedestal layer in the depression, to form the source drain of the transistor arrangement.
2. the preparation method of transistor arrangement according to claim 1, it is characterised in that the isolation junction in step 1)
Structure includes the first protective layer, separation layer and the second protective layer successively；After step 2), the bolt conductive layer after the first etching
Apical side height of the apical side height still greater than the first protective layer described on the grid conducting layer；After step 7), the 3rd etching
Height of the apical side height of the bolt conductive layer still greater than the grid conducting layer afterwards.
3. the preparation method of transistor arrangement according to claim 1, it is characterised in that sacrifice layer described in step 4) is more
It is formed at sidewall surfaces and the upper surface of the bolt conduction definition layer.
4. the preparation method of transistor arrangement according to claim 1, it is characterised in that when described in the bolt conductive layer
Second side has edge slot relative to the first side compared with out-of-flatness, the sacrifice layer filling formed in step 4)
In the edge slot, prominent structure can be sacrificed to be formed；In step 7), while remove the prominent structure.
5. the preparation method of transistor arrangement according to claim 1, it is characterised in that atomic deposition is used in step 4)
Technique forms the sacrifice layer；The thickness of the sacrifice layer is between 4nm~6nm；The material of the sacrifice layer includes silica
(SiO2)。
6. the preparation method of transistor arrangement according to claim 5, it is characterised in that form the reaction of the sacrifice layer
Gas includes SiH3N(C3H7)2、SiH[N(CH3)2]3, disilicone hexachloride (Si2Cl6)、SiH2(NHtBu)2Or H2Si[N
(C2H5)2]2With nitrogen (N2) and oxygen (O2) mixed gas；Wherein, SiH3N(C3H7)2、SiH[N(CH3)2]3、Si2Cl6、
SiH2(NHtBu)2Or H2Si[N(C2H5)2]2Gas flow be 0.2slm~1slm, the gas flow of the nitrogen is 3slm
~30slm, the gas flow of the oxygen is 3slm~10slm, and when forming the sacrifice layer, reaction temperature is 20 DEG C~80
DEG C, reaction pressure is normal pressure~1500mtorr, and the reaction time is 3min~60min.
7. the preparation method of transistor arrangement according to claim 1, it is characterised in that dry etching is used in step 7)
Technique etches the bolt conductive layer and the sacrifice layer；Etch period is 5sec~15sec；Remove the thickness of the bolt conductive layer
Between 10nm~40nm, the reacting gas includes hydrogen bromide (HBr) and chlorine (Cl2) mixed gas, the hydrogen bromide
And chlorine (Cl (HBr)2) total gas couette of mixed gas is 10sccm~50sccm；Wherein, the gas of the hydrogen bromide (HBr)
Body flow is 5sccm~30sccm, the chlorine (Cl2) gas flow be 5sccm~30sccm.
8. the preparation method of transistor arrangement according to claim 1, it is characterised in that what is formed in step 1) is described
The thickness of bolt conductive layer is between 120nm~170nm；The thickness of the bolt conductive layer is removed in step 2) between 30nm~60nm.
9. the preparation method of transistor arrangement according to claim 2, it is characterised in that using chemical vapor deposition method
Formed first protective layer, the separation layer, second protective layer, the bolt conductive layer, the bolt conduction definition layer and
The bolt conductive isolation layer, the metal pedestal layer is formed using sputtering technology；Wherein, first protective layer, described second protect
The material of sheath, the bolt conduction definition layer and the bolt conductive isolation layer includes silicon nitride (SiN)；The separation layer material
Material includes silica (SiO2)；The material of the bolt conductive layer includes polysilicon；The material of the metal pedestal layer include tungsten (W) or
Aluminium (Al).
10. the preparation method of transistor arrangement according to any one of claim 1 to 9, it is characterised in that the preparation
Before method is also included in step 1), in the Semiconductor substrate the step of formation active area, and formed in the active area
The step of fleet plough groove isolation structure and notched gates.
11. the preparation method of transistor arrangement according to claim 10, it is characterised in that the fleet plough groove isolation structure
Forming method include：
Step 11a) there is the first etching barrier layer of the first etching window in active area upper surface formation one, wherein, institute
The position for stating the first etching window is corresponding with the position longitudinal direction of the fleet plough groove isolation structure；
Step 12a) active area is performed etching by first etching window, to form the first groove；And
Step 13a) in first groove packed layer is formed, to form the fleet plough groove isolation structure；
The forming method of the notched gates includes：
Step 11b) there is the second etching barrier layer of the second etching window in active area upper surface formation one, wherein, institute
The position for stating the second etching window is corresponding with the position longitudinal direction of the notched gates；
Step 12b) active area is performed etching by second etching window, to form the second groove；
Step 13b) in one barrier layer of inner wall surface formation of second groove；And
Step 14b) in being sequentially filled conductive layer and insulating barrier in second groove.
A kind of 12. transistor arrangement, it is characterised in that including：
A plurality of grid conducting layers, set on a semiconductor substrate；
Isolation structure, it is formed at sidewall surfaces and the upper surface of the grid conducting layer；
Bolt conductive layer, set on the semiconductor substrate, and be formed between the adjacent isolation structure, the isolation structure
Isolate the first side of the bolt conductive layer, the bolt conductive layer is formed on the fleet plough groove isolation structure of the Semiconductor substrate
Isolation channel, the isolation channel isolate the second side of the bolt conductive layer；
Sacrifice layer, it is formed at the second side of the bolt conductive layer；
Bolt conductive isolation layer, it is formed in the isolation channel, wherein, the sacrifice layer isolates the bolt conductive isolation layer and described
Bolt conductive layer, so that the bolt conductive isolation layer is not directly contacted with the second side of the bolt conductive layer；Wherein, the bolt
The apical side height of conductive layer is less than the apical side height of the isolation structure after thickness amendment, and is led less than bolt described in thickness amendment
The apical side height of electricity isolated layer, to form depression；And
Metal pedestal layer, filling are formed in the depression.
13. transistor arrangement according to claim 12, it is characterised in that the isolation structure includes sequentially forming first
Protective layer, separation layer and the second protective layer, first protective layer and the separation layer are sequentially formed in the grid conducting layer
Sidewall surfaces and upper surface；Second protective layer, it is formed at the separation layer sidewall surfaces.
14. transistor arrangement according to claim 12, it is characterised in that the material of the sacrifice layer includes silica
(SiO2), the thickness of the sacrifice layer is between 4nm~6nm.
15. transistor arrangement according to claim 13, it is characterised in that first protective layer, second protection
Layer and the material of the bolt conductive isolation layer include silicon nitride (SiN)；The insolated layer materials include silica (SiO2)；
The material of the bolt conductive layer includes polysilicon；The material of the metal pedestal layer includes tungsten (W) or aluminium (Al).
16. transistor arrangement according to claim 12, it is characterised in that the transistor arrangement also includes being formed at institute
The active area in Semiconductor substrate is stated, and the fleet plough groove isolation structure and the notched gates being formed in the active area；Wherein,
The fleet plough groove isolation structure includes：The first groove for being formed in the active area and to be formed at described first recessed
Packed layer in groove；
The notched gates include：The second groove for being formed in the active area, it is formed at the second groove inner wall surface
Barrier layer and it is sequentially filled in conductive layer and insulating barrier in second groove.
17. a kind of preparation method of memory cell, it is characterised in that the preparation method of the memory cell includes：
Step S1：Transistor arrangement prepared by one preparation method as claimed in claim 1 is provided；And
Step S2：Capacitance structure is formed above the metal pedestal layer of the transistor arrangement, to form memory cell.
18. a kind of memory cell, it is characterised in that the memory cell includes：
Transistor arrangement as claimed in claim 12；And
The capacitance structure being formed above the metal pedestal layer of the transistor arrangement.
19. a kind of memory array, it is characterised in that the memory array is deposited as claimed in claim 18 including a plurality of
Storage unit.
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