CN107887383B - GaN-based monolithic power inverter and manufacturing method thereof - Google Patents
GaN-based monolithic power inverter and manufacturing method thereof Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a GaN-based monolithic power inverter and a manufacturing method thereof, wherein the power inverter comprises: a heterojunction epitaxial substrate; a passivation layer formed on the heterojunction epitaxial substrate, with a plurality of hollow regions between the passivation layers; enhancement mode power triode structure forms in a plurality of hollow regions, includes: the first source electrode and the first drain electrode are in ohmic contact with the thin barrier layer, and the first grid electrode is insulated from the thin barrier layer through a first grid dielectric layer positioned below the first grid electrode; and a depletion mode power transistor structure formed in the remaining hollow region, including: the second source electrode and the second drain electrode are in ohmic contact with the thin barrier layer, and the second grid electrode is insulated from the passivation layer through a second grid dielectric layer positioned below the second grid electrode or directly contacts the passivation layer. The power converter is simple in preparation process, diversified in structure and capable of improving the yield of devices.
Description
Technical Field
The disclosure belongs to the technical field of semiconductor devices, and relates to a GaN-based monolithic power inverter and a manufacturing method thereof.
Background
A power Inverter (power Inverter) formed by cascading enhancement (normal OFF) and depletion (normal ON) power triodes is a basic unit of an Inverter circuit and is applied to various DC/AC conversion modules. However, the difficulty in simultaneously realizing high-performance enhancement type and depletion type GaN-based power diodes on the same substrate is high, and the development of GaN-based power integrated circuits towards high efficiency and small intelligent application is restricted. Therefore, it is desirable to provide a new monolithic integrated power inverter and a manufacturing method thereof, which can simultaneously implement enhancement and depletion modes on the same substrate, and the manufacturing process is simple and convenient, which is helpful to promote the application and development of GaN-based power integrated circuits.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a GaN-based monolithic power inverter and a method of fabricating the same to at least partially solve the above-presented technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a GaN-based monolithic power inverter including: a heterojunction epitaxial substrate comprising: a heterojunction formed by the GaN buffer layer and the thin barrier layer generates two-dimensional electron gas at the interface of the heterojunction; a passivation layer formed on the heterojunction epitaxial substrate, with a plurality of hollow regions between the passivation layers; enhancement mode power triode structure forms a plurality of hollow regions among a plurality of hollow regions, includes: the first source electrode and the first drain electrode are in ohmic contact with the thin barrier layer, and the first grid electrode is insulated from the thin barrier layer through a first grid dielectric layer positioned below the first grid electrode; and a depletion mode power transistor structure formed in other hollow regions among the plurality of hollow regions, including: the second source electrode and the second drain electrode are in ohmic contact with the thin barrier layer, and the second grid electrode is insulated from the passivation layer through a second grid dielectric layer positioned below the second grid electrode or directly contacts the passivation layer.
In some embodiments of the present disclosure, a GaN-based monolithic power inverter, further comprises: and the injection isolation region is arranged between the first drain electrode and the second source electrode and at the edges of the first source electrode and the second drain electrode, and extends from the passivation layer to the GaN buffer layer of the heterojunction epitaxial substrate.
In some embodiments of the present disclosure, the heterojunction of the heterojunction epitaxial substrate is formed on an epitaxial substrate, which is one of the following materials: si, SiC, sapphire or GaN wafers.
In some embodiments of the present disclosure, the material of the thin barrier layer is one of the following materials: AlGaN, AlInN ternary alloy or AlInGaN quaternary alloy; and/or the thickness t of the thin barrier layer satisfies: t is more than 0 and less than or equal to 6 nm.
In some embodiments of the present disclosure, the passivation layer is one of the following materials: SiN, SiO2Or SiON; and/or the thickness of the passivation layer is between 5nm and 120 nm.
In some embodiments of the present disclosure, the hollow region comprises, in order: a first source opening region, a first gate opening region, a first drain opening region, a second source opening region, and a second drain opening region; the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are correspondingly formed in the first source electrode opening area, the first drain electrode opening area, the second source electrode opening area and the second drain electrode opening area to realize ohmic contact; the first grid dielectric layer at least covers two side walls and the bottom of the first grid opening area and partial passivation layers on two sides of the first grid opening area, and has intervals with the source electrode and the drain electrode; and the second gate dielectric layer is positioned on the passivation layer between the second source electrode and the second drain electrode.
According to another aspect of the present disclosure, there is provided a method of fabricating a GaN-based monolithic power inverter, including: preparing a passivation layer on a heterojunction epitaxial substrate, wherein the heterojunction epitaxial substrate comprises: a heterojunction formed by the GaN buffer layer and the thin barrier layer generates two-dimensional electron gas at the interface of the heterojunction; etching the passivation layer to prepare a first source electrode opening area, a first grid electrode opening area, a first drain electrode opening area, a second source electrode opening area and a second drain electrode opening area; correspondingly depositing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode in the first source electrode opening area, the first drain electrode opening area, the second source electrode opening area and the second drain electrode opening area, and manufacturing ohmic contact; manufacturing a first gate dielectric layer and a first gate electrode in the first gate electrode opening area, and manufacturing a second gate dielectric layer and a second gate electrode on the passivation layer between the second source electrode and the second drain electrode or only manufacturing the second gate electrode; monolithic integration of GaN-based depletion mode and enhanced metal insulator semiconductor high electron mobility transistors (MIS-HEMTs) is completed.
In some embodiments of the present disclosure, the method further comprises the following steps after the ohmic contact is made: and ion implantation isolation is performed between the first drain electrode and the second source electrode and at the edges of the first source electrode and the second drain electrode.
In some embodiments of the present disclosure, in the step of etching the passivation layer to prepare the first source opening region, the first gate opening region, the first drain opening region, the second source opening region, and the second drain opening region: the first grid opening area, the first source opening area and the first drain opening area are opened simultaneously; or opening according to a sequence, wherein the first source opening region and the first drain opening region are opened first, or the first gate opening region is opened first.
In some embodiments of the present disclosure, the passivation layer is prepared using one of the following methods: MOCVD, LPCVD, or PECVD; and/or etching the passivation layer by adopting F-based plasma etching to realize etching self-stop on the surface of the thin barrier layer.
(III) advantageous effects
According to the technical scheme, the GaN-based monolithic power inverter and the manufacturing method thereof have the following beneficial effects:
(1) by adopting the hetero-epitaxial substrate comprising the hetero-junction formed by the GaN buffer layer and the thin barrier layer, two-dimensional electron gas is generated at the interface of the hetero-junction to form the enhanced gate without etching the Al (In, Ga) N barrier layer, and the two-dimensional electron gas outside the gate is recovered through the passivation layer, so that the manufacturing difficulty of the GaN-based enhanced gate is reduced, and the yield of devices is effectively improved;
(2) the passivation layer is selectively etched, and the integrated manufacturing of the enhancement type MIS-HEMTs and the depletion type MIS-HEMTs is realized at the same time, so that the process is simple and the cost is low;
(3) the source electrode, the drain electrode, the grid electrode and the like can be opened simultaneously or opened step by step, the manufacturing process is simplified, furthermore, the depletion type MIS-HEMT can be formed by adding a grid medium of the enhancement type MIS-HEMT below the grid electrode to form a double-layer grid medium, the grid medium of the depletion type MIS-HEMT can also be not added, only a passivation layer is used as a single-layer grid medium, the structure is diversified, the process is simple, and the GaN-based monolithic power integrated circuit is promoted to be applied and developed to higher efficiency and miniaturization.
Drawings
Fig. 1A is a schematic structural diagram of a GaN-based monolithic power inverter according to an embodiment of the present disclosure.
Fig. 1B is another schematic structural diagram of a GaN-based monolithic power inverter according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of a method of fabricating a GaN-based monolithic power inverter according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram corresponding to each step in the manufacturing method of the GaN-based monolithic power inverter according to the embodiment of the disclosure.
[ notation ] to show
10-a heterojunction epitaxial substrate;
101-an epitaxial substrate; 102-a GaN buffer layer;
103-a thin barrier layer; 111-two-dimensional electron gas;
20-a passivation layer;
201-first source opening area; 202-a first drain opening region;
203-first gate opening area; 204-a second source opening area;
205-a second drain opening region;
301-a first source; 302-a first drain;
304-a second source; 305-a second drain;
401 — first implanted isolation regions; 402-a second implant isolation region;
403-third implanted isolation regions;
501-a first gate dielectric layer; 502-a second gate dielectric layer;
601-a first gate; 602-second gate.
Detailed Description
The invention provides a GaN-based monolithic power inverter and a manufacturing method thereof.A polycrystalline SiN, SiO are deposited on an ultra-thin potential barrier Al (In, Ga) N/GaN heterojunction epitaxial substrate2The SiON passivation layer can realize the depletion type and enhancement type metal-insulator-semiconductor (MIS-HEMTs) of GaN base without etching Al (In, Ga) N barrier layerMonolithic integration and fabrication of capability transistors); the GaN-based enhanced and depletion type power triode is industrially prepared and monolithically integrated, and the GaN-based enhanced and depletion type power triode is powerfully promoted to develop towards high efficiency and small compactness.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In a first exemplary embodiment of the present disclosure, a GaN-based monolithic power inverter is provided.
Fig. 1A is a schematic diagram of a structure of a GaN-based monolithic power inverter according to an embodiment of the present disclosure; fig. 1B is another schematic structural diagram of a GaN-based monolithic power inverter according to an embodiment of the present disclosure.
Referring to fig. 1A and 1B, a GaN-based monolithic power inverter of the present disclosure includes: a heterojunction epitaxial substrate 10 comprising: a heterojunction formed by the GaN buffer layer 102 and the thin barrier layer 103, generating a two-dimensional electron gas 111 at an interface of the heterojunction; passivation layers 20 formed on the heterojunction epitaxial substrate 10 with a plurality of hollow regions therebetween; enhancement mode power triode structure forms a plurality of hollow regions among a plurality of hollow regions, includes: a first source electrode 301, a first drain electrode 302 and a first gate electrode 601, wherein the first source electrode 301 and the first drain electrode 302 are in ohmic contact with the thin barrier layer 103, and the first gate electrode 601 is insulated from the thin barrier layer 103 by a first gate dielectric layer 501 below the first gate electrode 601; and a depletion mode power transistor structure formed in other hollow regions among the plurality of hollow regions, including: a second source electrode 304, a second drain electrode 305, and a second gate electrode 602, wherein the second source electrode 304 and the second drain electrode 305 are in ohmic contact with the thin barrier layer 103, and the second gate electrode 602 is insulated from the passivation layer 20 by a second gate dielectric layer 502 located thereunder or directly contacts the passivation layer 20.
The specific structure of the GaN-based monolithic power inverter will be described below with reference to a first embodiment.
The GaN-based monolithic power inverter in the present embodiment includes:
a heterojunction epitaxial substrate 10;
a passivation layer 20 formed on the heterojunction epitaxial substrate 10, and a plurality of hollow regions formed between the passivation layer 20, the hollow regions sequentially including: a first source open region 201, a first gate open region 203, a first drain open region 202, a second source open region 204, and a second drain open region 205;
a first source electrode 301 covering at least the first source electrode opening region 201 and portions of the passivation layer 20 at both sides thereof;
a first drain electrode 302 at least covering the first drain opening region 202 and portions of the passivation layer 20 at both sides thereof;
a second source electrode 304 covering at least the second source electrode opening area 204 and portions of the passivation layer 20 at both sides thereof;
a second drain electrode 305 covering at least the second drain opening region 205 and portions of the passivation layer 20 at both sides thereof;
implant isolation regions disposed between the first drain electrode 302 and the second source electrode 304 and at edges of the first source electrode 301 and the second drain electrode 305, extending from the passivation layer 20 all the way into the GaN buffer layer 102 of the heterojunction epitaxial substrate 10;
a first gate dielectric layer 501 at least covering two sidewalls and bottom of the gate opening region 203 and a portion of the passivation layer 20 on two sides thereof, and having an interval with the source 301 and the drain 302;
a first gate 601 formed on the first gate dielectric layer 501; and
a second gate 602, located between the second source 304 and the second drain 305, formed on the passivation layer 20, and forming a single-layer gate dielectric structure, so as to implement monolithic integration of GaN-based depletion and enhancement MIS-HEMTs transistors, as shown in fig. 1A;
in other GaN-based monolithic power inverter structures, the depletion-type MIS-HEMTs transistor may be a double-layer gate dielectric structure, as shown in fig. 1B, the second gate dielectric 502 is formed on the passivation layer 20, and the second gate 602 is located on the second gate dielectric 502, so as to form a double-layer gate dielectric structure formed by the passivation layer 20 and the second gate dielectric 502, thereby realizing monolithic integration of the GaN-based depletion-type and enhancement-type MIS-HEMTs transistors.
In this embodiment, the heterojunction epitaxial substrate 10 is an epitaxial structure, and sequentially from bottom to top: an epitaxial substrate 101, a GaN buffer layer 102, and a thin barrier layer 103; a two-dimensional electron gas 111 is generated at the heterojunction interface where the GaN buffer layer 102 contacts the barrier layer, as shown in fig. 1A.
In this embodiment, the epitaxial substrate 101 may be selected from, but not limited to, one or more of the following materials: si, SiC, sapphire, or GaN wafers, etc.
In this embodiment, the thin barrier layer 103 may be selected from, but not limited to, one or more of the following materials: AlGaN, AlInN ternary alloy or AlInGaN quaternary alloy with a thickness of 0-6 nm, and Al (In, Ga) N is used as an example In this embodiment.
In the embodiment, the passivation layer 20 is used as a protective layer of the two-dimensional electron gas except the grid, so that the barrier layer is prevented from being etched when depletion type MIS-HEMTs and enhancement type MIS-HEMTs are prepared in the prior art, and the yield of devices is improved; meanwhile, the passivation layer is also used as a hard mask plate to manufacture hollow regions such as a first source opening region 201, a first drain opening region 202, a first gate opening region 203, a second source opening region 204, a second drain opening region 205 and the like.
In this embodiment, the material of the passivation layer 20 may be selected from, but not limited to, one of the following materials: SiN, SiO2Or SiON with a thickness of between 5nm and 120 nm.
In this embodiment, the passivation layer may be prepared by one of the following methods: MOCVD (metal-organic chemical vapor deposition), lpcvd (low pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), or the like.
In this embodiment, the passivation layer 20 is used as a hard mask to fabricate hollow regions such as the first source opening region 201, the first drain opening region 202, the first gate opening region 203, the second source opening region 204, and the second drain opening region 205, and then fabricate the first source 301, the first drain 302, the second source 304, and the second drain 305 in the hollow regions, thereby implementing ohmic contact.
Referring to fig. 1A, in the present embodiment, the implantation isolation regions are respectively labeled as a first implantation isolation region 401, a second implantation isolation region 402, and a third implantation isolation region 403 according to different positions, where the first implantation isolation region 401 is located at an edge of the first source 301, and extends from the passivation layer 20 to the GaN buffer layer 102 of the heterojunction epitaxial substrate 10; the second implantation isolation region 402 is located at the edge of the second drain electrode 305, extending from the passivation layer 20 all the way into the GaN buffer layer 102 of the heterojunction epitaxial substrate 10; a third implant isolation region 403 is located between the first drain electrode 302 and the second source electrode 304, extending from the passivation layer 20 all the way into the GaN buffer layer 102 of the heterojunction epitaxial substrate 10; the injection isolation regions realize the isolation of the active region, contribute to improving the breakdown voltage, are arranged at the edge of the device, contribute to reducing the electric leakage of a field region and improve the temperature stability of the device.
In this embodiment, the materials of the first gate dielectric layer 501 and the second gate dielectric layer 502 may be selected from, but are not limited to, one or more of the following materials: al (Al)2O3SiN, SiON or SiO2And the like.
In a second exemplary embodiment of the present disclosure, a method of fabricating a GaN-based monolithic power inverter is provided.
Fig. 2 is a flowchart of a method of fabricating a GaN-based monolithic power inverter according to an embodiment of the present disclosure. Fig. 3 is a schematic structural diagram corresponding to each step in the manufacturing method of the GaN-based monolithic power inverter according to the embodiment of the disclosure.
Referring to fig. 2 and 3, a method for manufacturing a GaN-based monolithic power inverter according to the present disclosure includes:
step S202: preparing a passivation layer on the heterojunction epitaxial substrate;
in this embodiment, the heterojunction epitaxial substrate 10 is an epitaxial structure, and sequentially from bottom to top: an epitaxial substrate 101, a GaN buffer layer 102, and a thin barrier layer 103; a two-dimensional electron gas 111 is generated at the heterojunction interface where the GaN buffer layer 102 is in contact with the barrier layer.
Referring to fig. 3 (a), a passivation layer 20 is deposited on the epitaxial structure of the heterojunction epitaxial substrate 10.
In this embodiment, the epitaxial substrate 101 may be selected from, but not limited to, one or more of the following materials: si, SiC, sapphire, GaN wafers, or the like; the thin barrier layer 103 may be selected from, but is not limited to, one or more of the following materials: AlGaN, AlInN ternary alloy or AlInGaN quaternary alloy with a thickness of 0-6 nm, and an Al (In, Ga) N/GaN heterojunction epitaxial substrate with an ultra-thin barrier is taken as an example In the present embodiment for description.
In this embodiment, the passivation layer 20 may be prepared by one of the following methods: MOCVD (metal-organic chemical vapor deposition), lpcvd (low pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), or the like.
Step S204: etching the passivation layer to prepare a first source electrode opening area, a first grid electrode opening area, a first drain electrode opening area, a second source electrode opening area and a second drain electrode opening area;
a plurality of hollow regions are etched in the passivation layer 20 as shown in fig. 3 (a), and the hollow regions sequentially include from left to right: the two-dimensional electron gas 111 under the corresponding first source opening area 201, first gate opening area 203, first drain opening area 202, second source opening area 204, and second drain opening area 205 also disappears, as shown in fig. 3 (b).
In this embodiment, the gate opening region of the enhancement MIS-HEMT may be opened simultaneously with the source opening region and the drain opening region, or may be opened sequentially, where the source opening region and the drain opening region may be opened first, or the gate opening region may be opened first. That is, the first gate opening area, the first source opening area and the first drain opening area are opened simultaneously; or opening according to a sequence, wherein the first source opening region and the first drain opening region are opened first, or the first gate opening region is opened first.
The etching method can adopt the etching means In the prior art, preferably adopts F-based plasma etching, and can realize etching self-stop on the surface of a thin barrier layer of Al (In, Ga) N and the like.
Step S206: correspondingly depositing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode in the first source electrode opening area, the first drain electrode opening area, the second source electrode opening area and the second drain electrode opening area, and manufacturing ohmic contact;
referring to fig. 3 (c), ohmic contacts are formed by depositing the first source electrode 301, the first drain electrode 302, the second source electrode 304 and the second drain electrode 305 in the first source opening area 201, the first drain opening area 202, the second source opening area 204 and the second drain opening area 205, respectively, and at this time, the two-dimensional electron gas 111 filled with the electrode area is recovered.
Step S208: ion implantation isolation is carried out between the first drain electrode and the second source electrode and at the edges of the first source electrode and the second drain electrode;
referring to (d) in fig. 3, ion implantation is performed in the GaN buffer layer 102 extending from the passivation layer 20 all the way to the heterojunction epitaxial substrate 10; the regions of implant isolation are: the edges of the first source 301, the second drain 305, and the first drain 302 and the second source 304 are illustrated with reference to the first implanted isolation region 401, the second implanted isolation region 402, and the third implanted isolation region 403 in (d) of fig. 3. The injection isolation regions realize the isolation of the active region, contribute to improving the breakdown voltage, are arranged at the edge of the device, contribute to reducing the electric leakage of a field region and improve the temperature stability of the device.
Step S210: manufacturing a first gate dielectric layer and a first gate in the first gate opening area, manufacturing a second gate dielectric layer and a second gate on the passivation layer between the second source electrode and the second drain electrode or only manufacturing the second gate, and completing the monolithic integration of the GaN-based depletion type and enhancement type MIS-HEMTs;
corresponding to the fabrication of the structure shown in fig. 1A, in step S210: referring to fig. 3 (e), when the dotted line is considered to be absent, a first gate dielectric layer 501 is formed in the first gate opening region 203, such that the first gate dielectric layer 501 at least covers two sidewalls and a bottom of the first gate opening region 203 and portions of the passivation layer 20 at two sides thereof, and has an interval with the first source 301 and the first drain 302; then, referring to (f) in fig. 3, when the dotted line is considered to be absent, a first gate electrode 601 is deposited over the first gate dielectric layer 501, and a second gate electrode 602 is formed on the passivation layer 20 between the second source electrode 304 and the second drain electrode 305.
Corresponding to the fabrication of the structure shown in fig. 1B, in step S210: referring to fig. 3 (e), regarding the dotted line as existing, a first gate dielectric layer 501 is formed in the first gate opening region 203, such that the first gate dielectric layer 501 at least covers two sidewalls and a bottom of the first gate opening region 203 and portions of the passivation layer 20 at two sides thereof, and has an interval with the first source 301 and the first drain 302; a second gate dielectric layer 502 is manufactured on the passivation layer 20 between the second source electrode 304 and the second drain electrode 305; then, referring to (f) in fig. 3, when the dotted line is regarded as existing, a first gate 601 is deposited on the first gate dielectric layer 501, and a second gate 602 is formed on the second gate dielectric layer 502.
In summary, the present disclosure provides a GaN-based monolithic power inverter and a method for fabricating the same, wherein a hetero-epitaxial substrate including a hetero-junction formed by a GaN buffer layer and a thin barrier layer is used to generate two-dimensional electron gas at an interface of the hetero-junction, thereby forming an enhanced gate without etching an Al (In, Ga) N barrier layer, and the two-dimensional electron gas outside a gate is recovered through a passivation layer, thereby reducing the difficulty In fabricating the GaN-based enhanced gate and effectively improving the yield of devices; the passivation layer is selectively etched, and the integrated manufacturing of the enhancement type MIS-HEMTs and the depletion type MIS-HEMTs is realized at the same time, so that the process is simple and the cost is low; the source electrode, the drain electrode, the grid electrode and the like can be opened simultaneously or opened step by step, the manufacturing process is simplified, furthermore, depletion type MIS-HEMTs can be formed by adding enhanced MIS-HEMTs under the grid electrode to form a double-layer grid medium, the grid medium can also be not added, only a passivation layer is used as a single-layer grid medium, the structure is diversified, the process is simple, and the GaN-based single-chip power integrated circuit is promoted to be applied and developed to higher efficiency and small compactness.
It should be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, mentioned in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A GaN-based monolithic power inverter comprising:
a heterojunction epitaxial substrate comprising: a thin barrier heterojunction formed by the GaN buffer layer and the thin barrier layer, wherein two-dimensional electron gas is generated at the interface of the thin barrier heterojunction;
a passivation layer formed on the heterojunction epitaxial substrate, with a plurality of hollow regions between the passivation layers;
enhancement mode power triode structure forms a plurality of hollow regions among a plurality of hollow regions, includes: the first source electrode and the first drain electrode are in ohmic contact with the thin barrier layer, and the first grid electrode is insulated from the thin barrier layer through a first grid dielectric layer positioned below the first grid electrode; and
a depletion mode power triode structure formed in another hollow region of a plurality of hollow regions, comprising: the second source electrode and the second drain electrode are in ohmic contact with the thin barrier layer, and the second grid electrode is insulated from the passivation layer through a second grid dielectric layer positioned below the second grid electrode or directly contacts the passivation layer;
the thickness t of the thin barrier layer satisfies: t is more than 0 and less than or equal to 6 nm; the passivation layer is used for recovering two-dimensional electron gas outside the grid electrode.
2. The GaN-based monolithic power inverter of claim 1, further comprising:
and the injection isolation region is arranged between the first drain electrode and the second source electrode and at the edges of the first source electrode and the second drain electrode, and extends from the passivation layer to the GaN buffer layer of the heterojunction epitaxial substrate.
3. The GaN-based monolithic power inverter of claim 1, wherein the thin barrier heterojunction of the heterojunction epitaxial substrate is formed on an epitaxial substrate that is one of the following materials: si, SiC, sapphire or GaN wafers.
4. The GaN-based monolithic power inverter of claim 1, wherein:
the thin barrier layer is made of one of the following materials: AlGaN, AlInN ternary alloy or AlInGaN quaternary alloy.
5. The GaN-based monolithic power inverter of claim 1, wherein:
the passivation layer is one of the following materials: SiN, SiO2Or SiON; and/or
The thickness of the passivation layer is between 5nm and 120 nm.
6. The GaN-based monolithic power inverter of claim 1, wherein the hollow region comprises, in order: a first source opening region, a first gate opening region, a first drain opening region, a second source opening region, and a second drain opening region; the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are correspondingly formed in the first source electrode opening area, the first drain electrode opening area, the second source electrode opening area and the second drain electrode opening area to realize ohmic contact; the first grid dielectric layer at least covers two side walls and the bottom of the first grid opening area and partial passivation layers on two sides of the first grid opening area, and has intervals with the source electrode and the drain electrode; and the second gate dielectric layer is positioned on the passivation layer between the second source electrode and the second drain electrode.
7. A method of fabricating the GaN-based monolithic power inverter of any of claims 1 to 6, comprising:
preparing a passivation layer on a heterojunction epitaxial substrate, wherein the heterojunction epitaxial substrate comprises: a thin barrier heterojunction is formed by the GaN buffer layer and the thin barrier layer, and two-dimensional electron gas is generated at the interface of the thin barrier heterojunction;
etching the passivation layer to prepare a first source electrode opening area, a first grid electrode opening area, a first drain electrode opening area, a second source electrode opening area and a second drain electrode opening area;
correspondingly depositing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode in the first source electrode opening area, the first drain electrode opening area, the second source electrode opening area and the second drain electrode opening area, and manufacturing ohmic contact; and
manufacturing a first gate dielectric layer and a first gate in the first gate opening area, and manufacturing a second gate dielectric layer and a second gate or only manufacturing a second gate on the passivation layer between the second source and the second drain; completing the monolithic integration of GaN-based depletion mode and enhanced metal insulator semiconductor high electron mobility transistors (MIS-HEMTs);
the thickness t of the thin barrier layer satisfies: t is more than 0 and less than or equal to 6 nm; the passivation layer is used for recovering two-dimensional electron gas outside the grid electrode.
8. The method of claim 7, further comprising, after forming the ohmic contact, the steps of:
and ion implantation isolation is performed between the first drain electrode and the second source electrode and at the edges of the first source electrode and the second drain electrode.
9. The method of claim 7, wherein in the step of etching the passivation layer to form the first source opening region, the first gate opening region, the first drain opening region, the second source opening region, and the second drain opening region:
the first grid opening area, the first source opening area and the first drain opening area are opened simultaneously; or
The opening is performed in a sequential order, wherein the first source opening region and the first drain opening region are opened first, or the first gate opening region is opened first.
10. The production method according to any one of claims 7 to 9, wherein:
the passivation layer is prepared by adopting one of the following methods: MOCVD, LPCVD, or PECVD; and/or
And the etching passivation layer is etched by adopting F-based plasma, and etching self-stopping is realized on the surface of the thin barrier layer.
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| CN110970498B (en) * | 2018-09-29 | 2022-07-26 | 苏州能讯高能半导体有限公司 | Semiconductor device and preparation method thereof |
| CN112345614B (en) * | 2019-08-08 | 2023-07-21 | 中国科学院微电子研究所 | Detector based on gallium nitride-based enhanced device and manufacturing method thereof |
| CN111710651B (en) * | 2020-08-20 | 2020-11-13 | 浙江集迈科微电子有限公司 | Integrated GaN device and preparation method thereof |
| CN112466941A (en) * | 2020-11-27 | 2021-03-09 | 南方科技大学 | Preparation method of E/D-mode GaN HEMT integrated device |
| CN113053826A (en) * | 2021-03-19 | 2021-06-29 | 厦门市三安集成电路有限公司 | Integrated enhancement mode and depletion mode HEMT device and preparation method thereof |
| CN113823681A (en) * | 2021-08-30 | 2021-12-21 | 瑶芯微电子科技(上海)有限公司 | HEMT device based on grid field plate and double-source field plate and preparation method thereof |
| CN113871477A (en) * | 2021-08-30 | 2021-12-31 | 瑶芯微电子科技(上海)有限公司 | Double-heterojunction HEMT device based on grid field plate and source field plate and preparation method thereof |
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