CN107887343A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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CN107887343A
CN107887343A CN201710408106.9A CN201710408106A CN107887343A CN 107887343 A CN107887343 A CN 107887343A CN 201710408106 A CN201710408106 A CN 201710408106A CN 107887343 A CN107887343 A CN 107887343A
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semiconductor package
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conductive layer
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CN107887343B (zh
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吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本揭露提供半导体封装结构包含第一芯片、支撑件、导电层、绝缘层和模封层。第一芯片具有第一表面和与第一表面相对的第二表面。支撑件围绕第一芯片的边缘。导电层位在第一芯片的第一表面上并电连接到第一芯片。绝缘层位在第一芯片的第一表面上方，绝缘层朝向支撑件延伸并在垂直投影方向上与支撑件重叠。模封层在第一芯片和支撑件之间，并且至少围绕芯片的边缘。

Description

半导体封装结构及其制造方法
技术领域
本揭露涉及半导体封装结构及其制造方法，更具体地，涉及具有在垂直投影方向上 与支撑件重叠的绝缘层的半导体封装结构及其制造方法。
背景技术
由于对高性能和高密度半导体封装的需求，半导体封装结构设会计成具有高密度输 入和输出数和更薄的厚度。通常，公知半导体封装由于其薄厚度设计而具有不对称结构， 并且与具有硅通孔(TSV)的中介板整合形成在载体上以满足高密度要求。
然而，公知半导体封装结构由于具有不对称结构及在其不同材料层之间的热膨胀系 数(CTE)的差异而产生翘曲问题。另外，使用中介板和永久载体增加了制造成本并且 使得半导体封装结构的厚度难以进一步减小。
发明内容
在本揭露的一个或多个实施例中，半导体封装结构包含第一芯片、支撑件、导电层、 绝缘层和模封层。第一芯片具有第一表面和与第一表面相对的第二表面。支撑件围绕第 一芯片的边缘。导电层位在第一芯片的第一表面上并电连接到第一芯片。绝缘层位在第一芯片的第一表面上方，绝缘层朝向支撑件延伸并在垂直投影方向上与支撑件重叠。模 封层在第一芯片和支撑件之间，并且至少围绕芯片的边缘。
在本揭露的一个或多个实施例中，半导体封装结构包含第一芯片、支撑件、导电层、 绝缘层和模封层。第一芯片具有第一表面和与第一表面相对的第二表面。支撑件围绕第 一芯片的边缘。导电层位在第一芯片的第一表面上并电连接到第一芯片。绝缘层位在第一芯片的第一表面上。绝缘层包含第一部分和连接到第一部分的第二部分，第一部分在 垂直投影方向上与第一芯片重叠，第二部分在垂直投影方向上与支撑件重叠，并且第一 部分和第二部分位在不同的水平高度。模封层在第一芯片和支撑件之间，并且少围绕所 述第一芯片的边缘。
在本揭露的一个或多个实施例中，一种用于制造半导体封装结构的方法包含在临时 载体上形成支撑件，以及在临时载体上设置芯片，其中芯片的第一表面面向临时载体。所述制造方法还包含形成覆盖支撑件和芯片的第二表面的模封层，以及从支撑件和芯片去除临时载体。
附图说明
由以下详细说明与附随图式得以最佳了解本申请案揭示内容的各方面。注意，根据 产业的标准实施方式，各种特征并非依比例绘示。实际上，为了清楚讨论，可任意增大或缩小各种特征的尺寸。
图1是根据本揭露的一些实施例的半导体封装结构的剖面图；
图2A、图2B、图2C、图2D、图2E、图2F、图2G及图2H绘示根据本揭露的一 些实施例的半导体封装结构的制造方法；
图3是根据本揭露的一些实施例的临时载体和支撑件的示意图；
图4绘示根据本揭露的一些实施例的半导体封装结构的制造方法；
图5是根据本揭露的一些实施例的半导体封装结构的示意图；
图6是根据本揭露的一些实施例的半导体封装结构的示意图；
图7是根据本揭露的一些实施例的半导体封装结构的示意图；
图8是根据本揭露的一些实施例的半导体封装结构的示意图；
图9是根据本揭露的一些实施例的半导体封装结构的示意图；
图10A、图10B、图10C、图10D、图10E、图10F、图10G、图10H、图10I、图 10J、图10K、图10L及图10M绘示本揭露的一些实施例的半导体封装结构的制造方法；
图11A、图11B、图11C及图11D是根据本揭露的一些实施例的临时载体和支撑件 的示意图；
图12A及图12B绘示本揭露的一些实施例的制造半导体封装结构的方法；
图13是根据本揭露的一些实施例的半导体封装结构的示意图；
图14是根据本揭露的一些实施例的半导体封装结构的示意图；
图15是根据本揭露的一些实施例的半导体封装结构的示意图；
图16是根据本揭露的一些实施例的半导体封装结构的示意图；及
图17是根据本揭露的一些实施例的半导体封装结构的示意图。
具体实施方式
本揭露提供了数个不同的实施方法或实施例，可用于实现本发明的不同特征。为简 化说明起见，本揭露也同时描述了特定零组件与布置的范例。请注意提供这些特定范例的目的仅在于示范，而非予以任何限制。举例来说，在以下说明第一特征如何在第二特 征上或上方的叙述中，可能会包含某些实施例，其中第一特征与第二特征为直接接触， 而叙述中也可能包含其它不同实施例，其中第一特征与第二特征中间另有其它特征，以 致于第一特征与第二特征并不直接接触。此外，本揭露中的各种范例可能使用重复的参 考数字及/或文字注记，以使文件更加简单化和明确，这些重复的参考数字与注记不代表 不同的实施例与配置之间的关联性。
另外，本揭露在使用与空间相关的叙述词汇，如“在…之上”、“在…之下”、“上”、“左”、“右”、“下”、“顶”、“底”、“垂直”、“水平”、“侧”、“较高”、“较低”、“较下方”、 “较上方”、“上方”、“下方”、和类似词汇时，为便于叙述，其用法均在于描述图示中一 个组件或特征与另一个(或多个)组件或特征的相对关系。除了图示中所显示的角度方向 外，这些空间相对词汇也用来描述所述装置在使用中以及操作时的可能角度和方向。所 述装置的角度方向可能不同，而在本揭露所使用的这些空间相关叙述可以同样方式加以 解释。
下文描述一种半导体封装结构。所述半导体封装结构包含封装在其中的芯片。芯片 可以是各种类型的芯片中的一种，例如光电芯片、半导体芯片、电子芯片或微机电***(MEMS)芯片。
下文还描述一种制造半导体封装结构的方法。在一些实施例中，所述制造方法使用 临时载体作为衬底以形成支撑件、芯片及模封层。模封层覆盖支撑件，从而形成具有足够的机械强度以保持芯片的结构。因此，可以去除临时载体，并且因此可以减小半导体 封装结构的厚度。
图1是根据本揭露的一些实施例的半导体封装结构1的剖面图。如图1所示，半导体封装结构1包含一个或多个芯片(例如，一个或多个第一芯片)20、一个或多个支撑 件10、导电层16、绝缘层18及模封层30。芯片20具有第一表面201及与第一表面201 相对的第二表面202。在一个或多个实施例中，芯片20可以包含专用集成电路(ASIC) 芯片，存储器芯片或任何其它合适的主动(active)芯片或被动(passive)芯片。支撑件10围 绕芯片20的边缘20E。支撑件10可以是刚性支撑件或软支撑件。用于刚性支撑物的材 料可以是包含例如铜、镍、金、银或不锈钢的金属或合金，例如硅、玻璃、陶瓷或有机 材料的绝缘材料或任何其它合适材料的导电材料。用于软支撑物的材料可以是橡胶、热 塑性材料、热弹性材料或任何其它合适的材料。支撑件10经配置为加强件(stiffener)以 提供机械坚固性(mechanicalrobustness)。
在一个或多个实施例中，导电层16位在芯片20的第一表面201上，并且电连接到芯片20。绝缘层18位在芯片20的第一表面201上方。绝缘层18朝向支撑件10延伸并 在垂直投影方向Z上重叠。在一个或多个实施例中，导电层16嵌入绝缘层18中，形成 一重布层(RDL)15。例如，导电层16包含一层或多层的导电图案，并且绝缘层18包 含一层或多层绝缘膜层。导电图案的最顶层及最底层从重布层15的相对侧暴露。
在一个或多个实施例中，模封层30位在芯片20及支撑件10之间，并且模封层30 至少围绕芯片20的边缘20E。在一个或多个实施例中，模封层30覆盖芯片20的第二表 面202及支撑件10。模封层30、支撑件10及绝缘层18可以彼此接合以增强半导体封 装结构1的坚固性，并且因此可以不使用载体或中介板。因此，可以减小半导体封装结 构1的厚度。
在一个或多个实施例中，半导体封装结构1还包含形成在芯片20的第一表面201及导电层16之间的一个或多个导体(例如，一个或多个第一导体)24。芯片20及导电 层16通过导体24彼此电连接。在一个或多个实施例中，导体24可以包含接触垫(contact pad)，并且一填胶层(underfill layer)26可以填充在芯片20及重布层15之间。在一个或 多个实施例中，填胶层26可以由通过凝胶分配(gel dispensing)形成的粘合剂层代替。
在一个或多个实施例中，半导体封装结构1还包含封装衬底40及位在绝缘层18和封装衬底40之间的一个或多个第二导体44。导电层16和封装衬底40通过第二导体44 电连接。封装衬底40可以包含形成在其中的内部导体。第二导体44可以是但不限于由 填胶层46围绕的焊料凸块(solder bump)。
在一个或多个实施例中，半导体封装结构1还包含电路板50及形成在封装衬底40和电路板50之间的一个或多个第三导体48。封装衬底40及电路板50通过第三导体48 电连接。电路板50可以包含形成在其中的电路。第三导体48可以是但不限于例如C4 凸块的焊料凸块。在一个或多个实施例中，封装衬底40及电路板50可以通过栅格阵列 (LGA)接合、球栅阵列(BGA)接合或任何其它合适的接合技术电连接。
在一个或多个实施例中，模封层30、支撑件10及绝缘层18可以彼此结合以增强半导体封装结构1的坚固性，并且因此可以不使用载体或中介板。因此，可以减小半导体 封装结构1的厚度，并且可以减轻半导体封装结构1的翘曲。另外，绝缘层18或模封 层30可以部分地固定在支撑件10上，因此可以减轻表面褶皱。
图2A、图2B、图2C、图2D、图2E、图2F、图2G及图2H绘示根据本揭露的一 些实施例的半导体封装结构的制造方法。应当理解，所述方法可以是晶圆级(wafer level) 制造方法，并且为了清楚地讨论而示出了一个半导体封装结构。如图2A及图2所示， 支撑件10形成在临时载体12上，其中图2A是透视图，图2B是图2A的局部剖面图。 在一个或多个实施例中，临时载体12是单层膜，并且临时载体12的材料包含例如铜或 镍的导电材料，或者绝缘材料例如东京应化(TOK)的介电材料(商品名TMMR)。在一个 或多个实施例中，临时载体12具有如图2B所示的矩形形状。支撑件10可以是但不限 于硅支撑件。支撑件10可以具有网格图案，定义出用于容纳芯片的一个或多个腔10A。 在一个或多个实施例中，支撑件10包含彼此连接的第一区段101及第二区段102，并且 第二区段102的厚度小于第一区段101的厚度。第二区段102具有凹陷部分102R从支 撑件10的上表面凹陷。
如图2C所示，芯片20位在临时载体12上方及由支撑件10定义出的空腔10A中。 芯片20具有面向临时载体12的第一表面201及背向临时载体12的第二表面202。在一 个或多个实施例中，芯片20包含导体24，例如形成在第一表面201上的接触垫，并且 填胶层26分配(dispense)在芯片20及临时载体12之间，且填胶层26围绕导体24。
接着，如图2D所示，形成膜封层30，覆盖支撑件10与芯片20的第二表面202。 在一个或多个实施例中，膜封层30通过模制(molding)形成，第二区段102的凹部102R(如 图2A所示)允许模制材料在由支撑件10定义的空间之间流动。随后，模制材料可以被 热及/或光学固化以形成模封层30。模封层30覆盖并与支撑件10接合，由此形成足够 机械强度以保持芯片20的结构。因此，临时载体12可以通过例如蚀刻(etching)、掀开 (prying off)或任何其它合适的方法从支撑件10及芯片20移除。
如图2E所示，在临时载体12从支撑件10及芯片20移除之后，将芯片20翻转， 并且将导电层16及绝缘层18形成在芯片20的第一表面201上。在一个或多个实施例 中，绝缘层18朝向支撑件10延伸并在垂直投影方向Z上与支撑件10重叠。导电层16 嵌入绝缘层18中，形成重布层15。在一个或多个实施例中，重布层15可以通过堆叠 多个绝缘膜及导电图案来形成。导电图案的最底层及最顶层从绝缘层18暴露，其中导 电图案的最底层及最顶层中的其中一个导电图案电连接到芯片20的导体24，且导电图 案的最底层及最顶层中的其中另一个导电图案电连接到后续形成的另一电子装置。
如图2F所示，在重布层15上方形成第二导体44。在一个或多个实施例中，第二导体44是焊料凸块，例如C4凸块，但不限于此。参考图2G，通过例如刀片切割，蚀刻 或激光切割来执行切割工艺，以形成多个半导体封装结构1。参考图2H，半导体封装结 构1经由第二导体44电连接到封装衬底40。填胶层46可以填充在重布层15及封装衬 底40之间，以围绕及保护第二导体44。
随后，在一个或多个实施例中，将第三导体48形成在封装衬底40上。第三导体48可以是但不限于焊料凸块。封装衬底40可以通过第三导体48电连接到电路板50，以形 成如图1所示的半导体封装结构1。
本揭露的半导体封装结构及制造方法不限于上述实施例，且可根据其它实施例实施。为简化以下描述且为方便本揭露的各种实施例之间的比较，用与在上文所使用编号 相同的编号标记每一以下实施例中的类似于上文所描述的组件的组件，且可省略对那些 组件的描述。
图3是根据本揭露的一些实施例的临时载体及支撑件的示意图。如图3所示，临时载体12具有圆形形状。
图4绘示根据本揭露的一些实施例的半导体封装结构的制造方法。如图4所示，临时载体12是包含膜堆叠的复合载体。例如，临时载体12包含彼此堆叠的导电膜121和 绝缘膜122。
图5是根据本揭露的一些实施例的半导体封装结构2的示意图。如图5所示，半导体封装结构2的膜封层30可通过研磨等方式进行薄化，以暴露出芯片20的第二表面202， 但膜封层30仍覆盖于支撑件10上。
图6是根据本揭露的一些实施例的半导体封装结构3的示意图。如图6所示，将半导体封装结构3的膜封层30薄化，以暴露出芯片20的第二表面202及支撑件10。
图7是根据本揭露的一些实施例的半导体封装结构4的示意图。如图7所示，半导体封装结构4包含覆盖或围绕芯片20并填充在芯片20和重布层15之间的空间的模封 填胶(MUF)层31。模制填胶层31可以通过模制，凝胶分配或其它合适的方法。
图8是根据本揭露的一些实施例的半导体封装结构5的示意图。如图8所示，半导体封装结构8包含面向芯片(例如，第一芯片)20的第二表面202并通过导电层16电 连接到芯片20的第二芯片60。在一个或多个实施例中，半导体封装结构5包含一个或 多个模封通孔(through molding via,TMV)52和第四导体54。模封通孔52贯穿模封层30， 从而将重布层15的导电层16电连接到第四导体54。第四导体54形成在模封通孔52上。 第四导体54可以是但不限于焊料凸块。第二芯片60通过第四导体54和模封通孔52电 连接到导电层16。
图9是根据本揭露的一些实施例的半导体封装结构100的示意图。参考图9，半导体封装结构100包含一个或多个芯片20、支撑件10、导电层16、绝缘层18和模封层 30。芯片20具有第一表面201和与第一表面201相对的第二表面202。支撑件10围绕 芯片20的边缘20E。支撑件10可以是刚性支撑件或软支撑件。用于刚性支撑物的材料 可以是包含例如铜、镍、金、银或不锈钢的金属或合金，例如硅、玻璃、陶瓷、有机材 料或其它合适材料的绝缘材料的导电材料。用于软支撑物的材料可以是橡胶、热塑性材 料、热弹性材料或其它合适的材料。支撑件10经配置为加强件以增强机械坚固性。导 电层16位在芯片20的第一表面201上方并且电连接到芯片20。绝缘层18位在导电层 16上。绝缘层18包含彼此连接的第一部分181和第二部分182。第一部分181在垂直 投影方向Z上与芯片20重叠，第二部分182在垂直投影方向Z上与支撑件10重叠，并 且第一部分181和第二部分182位在不同的水平高度。模封层30位在芯片20和支撑件 10之间，并且膜封层30至少围绕芯片20的边缘20E。在一个或多个实施例中，模封层 30覆盖芯片20的第二表面202和支撑件10。
在一个或多个实施例中，半导体封装结构100还包含位在芯片20和绝缘层18之间的钝化层76。钝化层76可以进一步延伸而在垂直投影方向Z上与支撑件10重叠。
半导体封装结构100还包含形成在芯片20的第一表面201和导电层16之间的导体24。芯片20和导电层16通过导体24彼此电连接。在一个或多个实施例中，导体24可 以包含电连接到相应接合垫80的接触垫，及填充在芯片20和导电层16之间的填胶层 26。
在一个或多个实施例中，半导体封装结构100还包含嵌入在绝缘层18中并通过导电层16电连接到芯片20的重布层14。在一个或多个实施例中，半导体封装结构100进 一步包含封装衬底40，及在绝缘层18和封装衬底40之间的第二导体44。重布层14和 封装衬底40通过第二导体44电连接。在一个或多个实施例中，凸块下金属(UBM)86 可以设置在第二导体44和重布层14之间。
在一些实施例中，将种子层(例如，第一种子层)72形成在绝缘层18上及绝缘层 18的开口中，并且将另一种子层(例如，第二种子层)81形成在种子层72的背面。在 一些实施例中，将接合垫82和凸块下金属86形成在种子层81上。
在一些实施例中，模封层30、支撑件10和绝缘层18彼此接合以增强半导体封装结构100的坚固性，因此不使用载体或中介板。因此，可以减小半导体封装结构100的厚 度，并且可以减轻半导体封装结构100的翘曲。另外，绝缘层18或模封层30部分地固 定在支撑件10上，从而减轻了表面褶皱。
图10A、图10B、图10C、图10D、图10E、图10F、图10G、图10H、图10I、图 10J、图10K、图10及图10M绘示本揭露的一些实施例的半导体封装结构的制造方法。 应当理解，所述方法可以是晶圆级制造方法，并且为了清楚地讨论而示出了一个半导体 封装结构。如图10A及图10B所示，将支撑件10形成在临时载体12上，其中图10A 是俯视图，图10B是图10A的局部剖面图。在一个或多个实施例中，临时载体12被释 放层11覆盖，并且支撑件10通过粘合层(例如，第一粘合层)13粘附到释放层11。 在一个或多个实施例中，粘合层13位在临时载体12的一部分和支撑件10之间。在一 个或多个实施例中，临时载体12具有正方形形状，并且支撑件10定义出具有多个方形 空腔10A的正方形栅格图案，用来容纳芯片。支撑件10可以是刚性支撑件或软性支撑 件。支撑件10经配置为加强件以提供机械坚固性。
参考图10B，在临时载体12和支撑件10上方形成绝缘层18。绝缘层18包含彼此 连接的第一部分181和第二部分182。第一部分181形成在空腔10A中，第二部分182 在垂直投影方向Z上与支撑件10重叠，并且第一部分181和第二部分182位在不同的 水平高度。绝缘层18的第一部分181具有暴露出临时载体12的一个或多个开口。
参考图10C，在绝缘层18上和绝缘层18的开口中形成种子层72。随后，在绝缘层 18上形成抗蚀剂层74例如干膜光致抗蚀剂层。抗蚀剂层74包含一个或多个开口，基本 上对应于绝缘层18的开口，并部分地暴露种子层72。在一个或多个实施例中，抗蚀剂 层74的开口的尺寸大于绝缘层18的开口的尺寸。
参考图10D，在种子层72上形成重布层14。在一个或多个实施例中，通过电镀形 成重布层14。重布层14可以包含一个或多个导电图案层。随后，去除从重布层14暴 露的抗蚀剂层74和种子层72。参考图10E，钝化层76形成在绝缘层18上。钝化层76 具有暴露重布层14的一个或多个部分的一个或多个开口。
参考图10F，导电层16形成在钝化层76上方，并且通过钝化层76的开口电连接到重布层14。在一个或多个实施例中，导电层16经配置为种子层。然后，在导电层16上 形成另一抗蚀剂层78例如干膜光致抗蚀剂层。抗蚀剂层78具有暴露出一部分的导电层 16的一个或多个开口。
参考图10G，在从抗蚀剂层78暴露的导电层16上形成一个或多个接合垫80。在一个或多个实施例中，通过电镀形成接合垫80。然后去除抗蚀剂层78。
如图10H所示，在临时载体12上方及支撑件10定义出的空腔10A中设置一个或 多个芯片20位。芯片20具有面向临时载体12的第一表面201和背向临时载体12的第 二表面202。在一个或多个实施例中，芯片20包含形成在第一表面201上并且电连接到 接合垫80的导体24。随后，在芯片20和钝化层76之间形成填胶层26，填胶层26可 以由通过凝胶分配形成的粘合剂层代替。
参见图10I，形成模封层30，覆盖支撑件10和芯片20的第二表面202。在一个或 多个实施例中，模封层30通过模制形成。模封层30覆盖支撑件10并与支撑件10接合， 从而形成足够的机械强度以保持芯片20的结构。
参照图10J，将临时载体12从支撑件10和芯片20移除。在一个或多个实施例中， 释放层11被光学固化以降低其对绝缘层18的粘附强度，使得临时载体12以及释放层 11可以从绝缘层18释放。在一个或多个实施例中，粘合层13被热固化以从支撑件10 释放。
如图10K所示，在种子层(例如，第一种子层)72的背面上形成另一种子层(例 如，第二种子层)81。然后，在种子层81上形成抗蚀剂层84。抗蚀剂层84具有暴露一 部分的种子层81的一个或多个开口。随后，通过抗蚀剂层84的开口在暴露的种子层81 上形成接合垫82和凸块下金属86。之后，在凸块下金属86上方形成第二导体44。如 图10L所示，去除抗蚀剂层84和未被第二导体44覆盖的种子层81的部分。
如图10M所示，通过例如刀片切割，蚀刻或激光切割来执行切割工艺，以形成多个半导体封装结构100。随后，半导体封装结构100通过第二导体44电连接到封装衬底 40，如图9所示。
图11A、图11B、图11C及图11D是根据本揭露的一些实施例的临时载体和支撑件 的示意图。如图11A所示，临时载体12具有正方形形状，并且支撑件10具有定义出多 个圆形空腔10A的正方形栅格图案。如图11B所示，临时载体12具有圆形形状，并且 支撑件10具有定义出多个方形空腔10A的正方形栅格图案。如图11C所示，临时载体 12具有正方形形状，并且支撑件10具有定义出一个或多个方形空腔10A的圆形网格图 案。如图11D所示，临时载体12具有圆形形状，并且支撑件10具有定义出多个方形空 腔10A的圆形网格图案。
图12A及图12B绘示本揭露的一些实施例的制造半导体封装结构的方法。参考图12A，在形成支撑件10之前，在释放层11上形成第二粘合层90和导电层92。在一个 或多个实施例中，导电层92的材料包含例如铜合金、镍合金或其他合适的导电材料。 参考图12B，进行后续工艺(例如，类似于图10A-10M所示的工艺)以形成半导体封装 结构1200。
图13是根据本揭露的一些实施例的半导体封装结构1300的示意图。参考图13，通过例如研磨使半导体封装结构1300的模封层30变薄，以暴露芯片20的第二表面202。 然而，模封层30仍然可以覆盖钝化层76。在一个或多个实施例中，模封层30暴露芯片 20的第二表面202并且覆盖支撑件10上方的钝化层76。
图14是根据本揭露的一些实施例的半导体封装结构103的示意图。如图14所示，将半导体封装结构103的模封层30薄化，以暴露芯片20的第二表面202和钝化层76。 在一个或多个实施例中，模封层30暴露芯片20的第二表面202和钝化层76。
图15是根据本揭露的一些实施例的半导体封装结构104的示意图。如图15所示，半导体封装结构104包含面向芯片20的第二表面202的第二芯片60。导电层16朝向支 撑件10延伸并且在垂直投影方向Z上与支撑件10重叠，并且第二芯片60通过导电层 16电连接到芯片20。在一个或多个实施例中，半导体封装结构104还包含一个或多个 模封通孔52和第四导体54。模封通孔52贯穿模封层30，从而在支撑件10上方与导电 层16电连接。第四导体54形成在模封通孔52上。第四导体54可以是但不限于焊料凸 块。第二芯片60通过第四导体54和模封通孔52电连接到导电层16。
图16是根据本揭露的一些实施例的半导体封装结构105的示意图。如图16所示，半导体封装结构105包含面向芯片20的第二表面202的第二芯片60。导电层16朝向支 撑件10延伸并在垂直投影方向Z上与支撑件10重叠，并且第二芯片60通过导电层16 电连接到芯片20。模封层30在支撑件10上暴露导电层16。在一个或多个实施例中， 半导体封装结构105还包含一个或多个接合垫58和第四导体54。导电层16形成在支撑 件10上并且电连接到导电层16。第四导体54形成在接合垫58上。第四导体54可以是 但不限于焊料凸块。第二芯片60通过第四导体54及接合垫58电连接到导电层16。
图17是根据本揭露的一些实施例的半导体封装结构106的示意图。参考图17，半导体封装结构106包含覆盖芯片20并填充在芯片20和导电层16之间的模封填胶层31。 模封填胶层31可以通过模制、凝胶分配或其他方法形成。
本揭露的半导体封装结构使用支撑件(也称为加强件)与模封层结合以增强结构坚 固性，因此不使用载体或中介板。因此，减小了半导体封装结构的厚度，并且减轻了半导体封装结构的翘曲。此外，重布层或模封层部分地固定在支撑物上，因此减轻了表面 褶皱。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含复数指示物。
如本文中所使用，术语“导电”、“导电性”和“导电率”是指输送电流的能力。导 电性材料通常指示对电流的的流动呈现极少或无对抗的那些材料。电导率的一个度量为 西门子/米(S/m)。通常，导电性材料为导电率大于约104S/m(例如至少105S/m或至少 106S/m)的材料。材料的导电率有时可随温度变化而变化。除非另外说明，否则在室温 下测量材料的导电率。
如本文中所使用，术语“大致”、“基本上”、“大体上”以及“约”用以描述和考虑 小的变化。当与事件或情形结合使用时，所述术语可指事件或情形明确发生的情况以及 事件或情形极近似于发生的情况。举例来说，当结合数值使用时，术语可指小于或等于 所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、 小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、 小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数 值“基本上”相同或相等。举例来说，“基本上”平行可指相对于0°的小于或等于±10°(例 如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、 小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°)的角度变化范围。举例来说， “基本上”垂直可指相对于90°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、 小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、 或小于或等于±0.05°)的角度变化范围。
另外，有时在本文中按范围格式呈现量、比率和其它数值。应理解，此类范围格式是用于便利和简洁起见，且应灵活地理解，不仅包含明确地指定为范围限制的数值，而 且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围 一般。
尽管已参考本揭露的特定实施例描述并说明本揭露，但这些描述和说明并不限制本 揭露。所属领域的技术人员应理解，可在不脱离如由所附权利要求书界定的本揭露的真实精神和范围的情况下，作出各种改变且可取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和公差，本揭露中的艺术再现与实际设备之间可存在区别。可存在并未 特定说明的本揭露的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可 做出修改，以使特定情况、材料、物质组成、方法或工艺适应于本揭露的目标、精神和 范围。所有此类修改意图在所附权利要求书的范围内。虽然本文中所揭露的方法已参考 按特定次序执行的特定操作加以描述，但应理解，可在不脱离本揭露的教示的情况下组 合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作 的次序和分组不是对本揭露的限制。

Claims (20)

1.一种半导体封装结构，其包含：
一第一芯片，其具有一第一表面及相对于所述第一表面的一第二表面；
一支撑件，其围绕所述第一芯片的一边缘；
一导电层，其位在所述第一芯片的所述第一表面上方并电连接到所述第一芯片；
一绝缘层，其位在所述第一芯片的所述第一表面上方，其中所述绝缘层朝向所述支撑件延伸并在一垂直投影方向上与所述支撑件重叠；及
一模封层，其位在所述第一芯片及所述支撑件之间并至少围绕所述第一芯片的所述边缘。
2.根据权利要求1所述的半导体封装结构，其中所述封模层覆盖所述第一芯片的所述第二表面及所述支撑件；所述封模层暴露所述第一芯片的所述第二表面并覆盖所述支撑件；或者所述封模层暴露所述第一芯片的所述第二表面及所述支撑件。
3.根据权利要求1所述的半导体封装结构，其进一步包含一第一导体，其位在所述第一芯片的所述第一表面及所述导电层之间，其中所述第一芯片及所述导电层通过所述第一导体电连接。
4.根据权利要求1所述的半导体封装结构，其进一步包含：
一封装衬底；及
一第二导体，其位在所述绝缘层及所述封装衬底之间，其中所述导电层及所述封装衬底通过所述第二导体电连接。
5.根据权利要求4所述的半导体封装结构，其进一步包含：
一电路板；及
一第三导体，其位在所述封装衬底及所述电路板之间，其中所述封装衬底及所述电路板通过所述第三导体电连接。
6.根据权利要求1所述的半导体封装结构，其中所述支撑件包括一第一区段及连接到所述第一区段的一第二区段，所述第二区段包括一凹陷部分，且所述第二区段的一厚度小于所述第一区段的一厚度。
7.根据权利要求1所述的半导体封装结构，其中所述导电层是位在所述绝缘层中的一重布层。
8.根据权利要求1所述的半导体封装结构，其进一步包含一第二芯片，其面向所述第一芯片的所述第二表面并通过所述导电层电连接到所述第一芯片。
9.一种半导体封装结构，其包含：
一第一芯片，其具有一第一表面及相对于所述第一表面的一第二表面；
一支撑件，其围绕所述第一芯片的一边缘；
一导电层，其位在所述第一芯片的所述第一表面上方并电连接到所述第一芯片；
一绝缘层，其位在所述导电层上方，其中所述绝缘层包含一第一部分及连接到所述第一部分的一第二部分，所述第一部分在一垂直投影方向上与所述第一芯片重叠，所述第二部分在所述垂直投影方向上与所述支撑件重叠，且所述第一部分及所述第二部分位在不同的水平高度上；及
一模封层，其位在所述第一芯片及所述支撑件之间并至少围绕所述第一芯片的所述边缘。
10.根据权利要求9所述的半导体封装结构，其进一步包含一第一导体，其位在所述第一芯片的所述第一表面及所述导电层之间，其中所述第一芯片及所述导电层通过所述第一导体电连接。
11.根据权利要求9所述的半导体封装结构，其进一步包含：
一重布层，其位在所述绝缘层中并通过所述导电层电连接到所述第一芯片；
一封装衬底；及
一第二导体，其位在所述绝缘层及所述封装衬底之间，其中所述重布层及所述封装衬底通过所述第二导体电连接。
12.根据权利要求9所述的半导体封装结构，其中所述封模层覆盖所述第一芯片的所述第二表面及所述支撑件；所述封模层暴露所述第一芯片的所述第二表面并覆盖所述支撑件；或者所述封模层暴露所述第一芯片的所述第二表面及所述支撑件。
13.根据权利要求9所述的半导体封装结构，其进一步包含面向所述第一芯片的所述第二表面的一第二芯片，其中所述导电层朝向所述支撑件延伸且在所述垂直投影方向上与所述支撑件重叠，且所述第二芯片通过导电层电连接到所述第一芯片。
14.一种半导体封装结构的制造方法，其包含：
在一暂时载体上方形成一支撑件；
将一芯片设置在所述暂时载体上，其中所述芯片的一第一表面面向所述暂时载体；
形成一模封层，其覆盖所述支撑件及所述芯片的一第二表面；及
从所述支撑件及所述芯片移除所述暂时载体。
15.根据权利要求14所述的制造半导体封装结构的方法，其进一步包含在将所述芯片设置在所述暂时载体上方之前，在所述暂时载体上及一绝缘层中形成一重布层。
16.根据权利要求15所述的制造半导体封装结构的方法，其中所述绝缘层包含一第一部分及连接到所述第一部分的一第二部分，所述第一部分在一垂直投影方向上与所述第一芯片重叠，所述第二部分在所述垂直投影方向上与所述支撑件重叠，且所述第一部分及所述第二部分位在不同的水平高度上。
17.根据权利要求14所述的制造半导体封装结构的方法，其进一步包含：在将所述芯片设置在所述暂时载体上方之前，在一重布层上方形成与所述重布层电连接的一导电层，其中所述导电层至少设置在所述暂时载体及所述芯片之间，且所述芯片电连接到所述导电层。
18.根据权利要求17所述的制造半导体封装结构的方法，其中所述导电层进一步朝向所述支撑件延伸并在一垂直投影方向上与所述支撑件重叠。
19.根据权利要求14所述的制造半导体封装结构的方法，其进一步包含在从所述支撑件及所述芯片移除所述暂时载体之后，在所述芯片的所述第一表面及所述支撑件上方的一绝缘层中形成一导电层。
20.根据权利要求19所述的制造半导体封装结构的方法，其中所述支撑件包括一第一区段及连接到所述第一区段的一第二区段，所述第二区段包括一凹陷部分，且所述第二区段的一厚度小于所述第一区段的一厚度。
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