CN107884641B - Test circuit for spacecraft - Google Patents
Test circuit for spacecraft Download PDFInfo
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- CN107884641B CN107884641B CN201711039327.XA CN201711039327A CN107884641B CN 107884641 B CN107884641 B CN 107884641B CN 201711039327 A CN201711039327 A CN 201711039327A CN 107884641 B CN107884641 B CN 107884641B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The invention relates to a test circuit for a spacecraft, comprising: the input end of the isolation circuit is used for receiving an input signal; the input end of the delay circuit is connected with the output end of the isolation circuit; the input end of the driving circuit is connected with the output end of the delay circuit; and the input end of the event timer is connected with the output end of the driving circuit. The input signals are isolated by the isolation circuit, so that the complete isolation of the input signals from subsequent circuits is ensured, and the safety of the whole test circuit is further ensured. By adopting the optical coupling isolation mode, the input signal is completely isolated from the circuit behind the isolation circuit. The electric isolation between the spacecraft test point and the ground test system is realized in the ground test process of the spacecraft. The safety of the internal circuit of the spacecraft in the ground test process of the spacecraft is ensured.
Description
Technical Field
The invention relates to a test circuit, in particular to a test circuit for a spacecraft.
Background
In the process of testing the spacecraft, some key time sequence signals are transmitted to ground test equipment in the form of multi-channel pulse signals for measurement. The ground needs to measure the sending condition of each channel signal and the occurrence time sequence of the signal. Due to the safety requirement of the spacecraft, when the pulse signals are tested, the electrical isolation between a spacecraft measuring point and a ground test system is ensured.
At present, most of general pulse signal test circuits adopt single-channel pulse counting circuits, and test circuits on part of special pulse signal test circuits realize counting functions among multiple channels. However, no isolation means is provided in the circuit of the existing test board, and the circuit does not have a complex logic relationship of multiple channels. Therefore, the test circuit on the existing test board card cannot meet the test requirements for the spacecraft.
Disclosure of Invention
The invention aims to provide a test circuit for a spacecraft, which can electrically isolate a spacecraft measurement point from a bottom surface test system.
To achieve the above object, the present invention provides a test circuit for a spacecraft, comprising:
the input end of the isolation circuit is used for receiving an input signal;
the input end of the delay circuit is connected with the output end of the isolation circuit;
the input end of the driving circuit is connected with the output end of the delay circuit;
and the input end of the event timer is connected with the output end of the driving circuit.
According to one aspect of the invention, the isolation circuit employs a TLP521-4 optocoupler.
According to an aspect of the present invention, the delay circuit includes a logical operation circuit and a JK flip-flop, wherein,
the input end of the logic operation circuit is connected with the output end of the isolation circuit;
the output end of the logic operation circuit is connected with the input end of the JK trigger;
and the output end of the JK trigger is connected with the input end of the driving circuit.
According to one aspect of the present invention, the logical operation circuit includes a first gate circuit which is a logical or gate circuit;
the input end of the first gate circuit is connected with the output end of the isolation circuit, and the output end of the first gate circuit is connected with the clock end of the JK trigger.
According to an aspect of the present invention, the logical operation circuit further includes a second gate circuit, the second gate circuit being a logical nand gate circuit;
the input end of the second gate circuit is connected with the output end of the isolation circuit, and the output end of the second gate circuit is connected with the clock end of the JK trigger.
According to an aspect of the present invention, when the timing signal received by the clock terminal of the JK flip-flop is a falling edge, the data latch output terminal of the JK flip-flop is switched from a high impedance state to a high level state.
According to one aspect of the invention, the data latch output end of the JK flip-flop is connected with the input end of the driving circuit;
and the output signal of the JK trigger is converted into a step signal through the driving circuit and is transmitted to the event timer.
According to one aspect of the invention, the driving circuit employs a darlington tube.
According to one aspect of the invention, the JK trigger further comprises a reset circuit, and the reset circuit is connected with the zero clearing end of the JK trigger.
According to one aspect of the invention, the input signal is a voltage signal; alternatively, the input signal is a contact signal.
According to the test circuit, the input signals are isolated by the isolation circuit, so that the input signals are completely isolated from the subsequent test circuit, the influence of the input signals on the subsequent test circuit is avoided, and the safety of the whole test circuit is further ensured. By adopting the optical coupling isolation mode, the input signal is completely isolated from the circuit behind the isolation circuit. The electric isolation between the spacecraft testing point and the ground testing system is realized in the ground testing process of the spacecraft, and the spacecraft is not influenced by the ground testing system in the ground testing process. The isolation test circuit is adopted to further ensure the safety of the internal circuit of the spacecraft, prevent the electronic elements in the spacecraft from being damaged and ensure the service life of the spacecraft. Meanwhile, the isolation test circuit has strong anti-interference performance, and the accuracy of the test result of the spacecraft test point is also ensured.
According to the test circuit, on the basis of ensuring the isolation safety between the spacecraft measurement point and the ground test system, the timing of various input signals can be met. The logic operation circuit integrates input signals, and the JK trigger latches the signals. The combination of the logic operation circuit and the JK trigger can be used for timing the input complex multi-channel signals after logic operation, so that high-precision time measurement of the multi-channel signals is guaranteed.
According to the test circuit, different delay circuits can be combined and arranged according to the number and types of test signals, and the test circuit is combined with the isolation circuit, so that the applicability of the test circuit is improved. The test and accurate timing of the complex signals of the spacecraft are further met.
Drawings
FIG. 1 is a block diagram schematically illustrating the structure of a test circuit according to the present invention;
FIG. 2 schematically shows a block diagram of a test circuit according to an embodiment of the invention;
FIG. 3 schematically shows a diagram of input signals of a test circuit according to an embodiment of the invention;
FIG. 4 is a signal diagram schematically illustrating an input signal of a test circuit after logic operation according to an embodiment of the present invention;
FIG. 5 schematically shows a block diagram of a test circuit according to another embodiment of the invention;
FIG. 6 schematically shows a diagram of input signals for a test circuit according to another embodiment of the present invention;
FIG. 7 is a signal diagram schematically illustrating an input signal of a test circuit after logic operation according to another embodiment of the present invention;
FIG. 8 schematically shows a block diagram of a test circuit according to another embodiment of the invention;
FIG. 9 schematically shows a contact signal conversion circuit diagram of a test circuit according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
In describing embodiments of the present invention, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship that is based on the orientation or positional relationship shown in the associated drawings, which is for convenience and simplicity of description only, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, the above-described terms should not be construed as limiting the present invention.
The present invention is described in detail below with reference to the drawings and the specific embodiments, which are not repeated herein, but the embodiments of the present invention are not limited to the following embodiments.
As shown in fig. 1, according to one embodiment of the present invention, the test circuit for a spacecraft of the present invention includes an isolation circuit 1, a delay circuit 2, a drive circuit 3, an event timer 4, and a reset circuit 5. In the present embodiment, the isolation circuit 1, the delay circuit 2, the driver circuit 3, and the event timer 4 are connected in this order. Wherein, the input end of the isolation circuit 1 is used for receiving input signals, and the isolation circuit 1 isolates the input signals. The input end of the delay circuit 2 is connected with the output end of the isolation circuit 1, and the delay circuit 2 receives the signal sent by the isolation circuit 1 and performs logic operation on the signal. The output end of the delay circuit 2 is connected with the input end of the driving circuit 3, and the driving circuit 3 is connected with the event timer 4 through the output end. The driving circuit 3 receives the signal processed by the delay circuit and sends a driving signal to the event timer 4 to operate the event timer 4. The event timer 4 receives the driving signal of the driving circuit 3, and performs channel and timing acquisition on the signal. The reset circuit 5 is connected to the delay circuit 2.
As shown in fig. 1, according to an embodiment of the present invention, the delay circuit 2 includes a logic operation circuit 21 and a JK flip-flop 22. In the present embodiment, the input terminal of the logical operation circuit 21 is connected to the output terminal of the isolation circuit 1, and the output terminal of the logical operation circuit 21 is connected to the input terminal of the JK flip-flop 22. The output of the JK flip-flop 22 is connected to the input of the driving circuit 3.
To further elaborate the test circuit of the present invention, the test circuit of the present invention is described in detail with reference to fig. 1 and 2.
Referring to fig. 1 and 2, according to an embodiment of the present invention, an isolation circuit 1 includes a first isolation sub-circuit 10 and a second isolation sub-circuit 11. In the present embodiment, the first isolation sub-circuit 10 and the second isolation sub-circuit 11 are independent from each other. Each separate isolation subcircuit receives a separate input signal. As shown in fig. 3, a first input signal a is input to the first isolation sub-circuit 10, and a second input signal B is input to the second isolation sub-circuit 11.
As shown in fig. 2 and fig. 3, the negative output terminal outputting the first input signal a is connected to the first positive input terminal 10a of the first isolation sub-circuit 10, and the positive output terminal outputting the first input signal a is connected to the first negative input terminal 10b of the first isolation sub-circuit 10. The positive output end outputting the second input signal B is connected to the second positive input end 11a of the second isolation sub-circuit 11, and the negative output end outputting the second input signal B is connected to the second negative input end 11B of the second isolation sub-circuit 11. The input signal is input into the corresponding isolation sub-circuit, so that the isolation of the input signal is realized. Through the arrangement, the input signals are isolated through the isolation circuit 1, so that the complete isolation of the input signals and a subsequent test circuit is ensured, and the safety of the whole test circuit is further ensured. In the present embodiment, the isolation circuit 1 employs optical coupling isolation. By adopting the optical coupling isolation mode, the input signal is completely isolated from the circuit behind the isolation circuit. The electric isolation between the spacecraft testing point and the ground testing system is realized in the ground testing process of the spacecraft, and the spacecraft is not influenced by the ground testing system in the ground testing process. The isolation test circuit is adopted to further ensure the safety of the internal circuit of the spacecraft, prevent the electronic elements in the spacecraft from being damaged and ensure the service life of the spacecraft. Meanwhile, the isolation test circuit has strong anti-interference performance, and the accuracy of the test result of the spacecraft test point is also ensured. In this embodiment, the isolation circuit 1 may be implemented by a TLP521-4 photocoupler.
As shown in fig. 2, the first positive output terminal 10c of the first isolation sub-circuit 10 is connected to the 5V power supply, and the first negative output terminal 10d thereof is connected to the ground, so as to output the signal of the first isolation sub-circuit 10. And a second positive output end 11c of the second isolation sub-circuit 11 is connected with a 5V power supply, and a second negative output end 11d of the second isolation sub-circuit 11 is connected with the ground, so that the signal output of the second isolation sub-circuit 11 is realized.
As can be seen from the foregoing, the delay circuit 2 includes a logic operation circuit 21 and a JK flip-flop 22. Referring to fig. 1 and 2, according to an embodiment of the present invention, the logic operation circuit 21 includes a first gate circuit 210. In this embodiment, the first gate circuit 210 is a logical or gate circuit. The first input end 210a of the first gate circuit 210 is connected to the first positive output end 10c of the first isolated sub-circuit 10. Second input 210b of first gate circuit 210 is connected to second positive output 11c of second isolated sub-circuit 11. Referring to fig. 3 and 4, the first input signal a and the second input signal B pass through the isolation circuit 1 and are transmitted to the first gate circuit 210, and the first input signal a and the second input signal B are operated as a one-way timing signal by a logical operation of the first gate circuit 210.
As shown in fig. 2, according to one embodiment of the present invention, the first output 210c of the first gate circuit 210 is connected to the clock terminal 22a of the JK flip-flop 22. In the present embodiment, when the timing signal received by the clock terminal 22a of the JK flip-flop 22 is a falling edge, the data latch output terminal 22b of the JK flip-flop 22 is switched from the high impedance state to the high level state, and the JK flip-flop 22 is turned on. In the present embodiment, the J input terminal 22c of the JK flip-flop 22 is connected to the 5V power supply, and the K input terminal 22d thereof is connected to the ground.
As shown in fig. 2, according to an embodiment of the present invention, the data latch output terminal 22b of the JK flip-flop 22 is connected to the driving input terminal 3a of the driving circuit 3, and the output signal of the JK flip-flop 22 is transmitted to the driving circuit 3. The input signal is converted into a step signal by the driving circuit 3 and transmitted to the event timer 4, the event timer 4 and the driving circuit 3 form a loop, and the event timer 4 starts timing. In the present embodiment, a darlington tube is used as the drive circuit 3. In practical application, the driving circuit 3 can be realized by adopting an MC1413 chip, and the event timer 4 is realized by adopting an aerospace measurement and control AMC4500 board.
As shown in fig. 2, the test circuit of the present invention further includes a reset circuit 5 according to an embodiment of the present invention. In the present embodiment, the reset circuit 5 is connected to the clear terminal 23e of the JK flip-flop 22. When the reset switch 5a of the reset circuit 5 is closed, the reset circuit 5 is turned on, and the clear terminal 23e of the JK flip-flop 22 is turned on, and the JK flip-flop 22 performs a clear operation.
Referring to fig. 1 and 5, according to another embodiment of the present invention, the isolation circuit 1 includes a third isolation sub-circuit 12 and a fourth isolation sub-circuit 13. In the present embodiment, the third isolation sub-circuit 12 and the fourth isolation sub-circuit 13 are independent of each other. Each separate isolation subcircuit receives a separate input signal. As shown in fig. 6, the third input signal C is input to the third isolation sub-circuit 12, and the fourth input signal D is input to the fourth isolation sub-circuit 13.
As shown in fig. 5 and fig. 6, the positive output terminal outputting the third input signal C is connected to the third positive input terminal 12a of the third isolation sub-circuit 12, and the negative output terminal outputting the third input signal C is connected to the third negative input terminal 12b of the third isolation sub-circuit 12. The negative output end outputting the fourth input signal D is connected to the fourth positive input end 13a of the fourth isolation sub-circuit 13, and the positive output end outputting the fourth input signal D is connected to the fourth negative input end 13b of the fourth isolation sub-circuit 13. The input signal is input into the corresponding isolation sub-circuit, so that the isolation of the input signal is realized. Through the arrangement, the input signals are isolated through the isolation circuit 1, so that the complete isolation of the input signals and a subsequent test circuit is ensured, and the safety of the whole test circuit is further ensured. In the present embodiment, the isolation circuit 1 employs optical coupling isolation. By adopting the optical coupling isolation mode, the input signal is completely isolated from the circuit behind the isolation circuit. The electric isolation between the spacecraft testing point and the ground testing system is realized in the ground testing process of the spacecraft, and the spacecraft is not influenced by the ground testing system in the ground testing process. The isolation test circuit is adopted to further ensure the safety of the internal circuit of the spacecraft, prevent the electronic elements in the spacecraft from being damaged and ensure the service life of the spacecraft. Meanwhile, the isolation test circuit has strong anti-interference performance, and the accuracy of the test result of the spacecraft test point is also ensured. In this embodiment, the isolation circuit 1 may be implemented by a TLP521-4 photocoupler.
As shown in fig. 5, the third positive output terminal 12c of the third isolation sub-circuit 12 is connected to the 5V power supply, and the third negative output terminal 12d thereof is connected to the ground, so as to output the signal of the third isolation sub-circuit 12. And a fourth positive output end 13c of the fourth isolation sub-circuit 13 is connected with a 5V power supply, and a fourth negative output end 13d of the fourth isolation sub-circuit 13 is connected with the ground, so that the signal output of the fourth isolation sub-circuit 13 is realized.
As can be seen from the foregoing, the delay circuit 2 includes a logic operation circuit 21 and a JK flip-flop 22. Referring to fig. 1 and 5, according to another embodiment of the present invention, the logic operation circuit 21 includes a second gate circuit 211. In this embodiment, the second gate circuit 211 is a nand gate circuit. The third input terminal 211a of the second gate circuit 211 is connected to the third positive output terminal 12c of the third isolated sub-circuit 12. A fourth input terminal 211b of the second gate circuit 211 is connected to a fourth positive output terminal 13c of the fourth isolated sub-circuit 13. Referring to fig. 6 and 7, the third input signal C and the fourth input signal D pass through the isolation circuit 1 and are transferred to the second gate circuit 211, and are operated into a single timing signal by a logic operation of the second gate circuit 211.
As shown in fig. 5, according to another embodiment of the present invention, the second output terminal 211c of the second gate circuit 211 is connected to the clock terminal 22a of the JK flip-flop 22. In the present embodiment, when the timing signal received by the clock terminal 22a of the JK flip-flop 22 is a falling edge, the data latch output terminal 22b of the JK flip-flop 22 is switched from the high impedance state to the high level state, and the JK flip-flop 22 is turned on. In the present embodiment, the J input terminal 22c of the JK flip-flop 22 is connected to the 5V power supply, and the K input terminal 22d thereof is connected to the ground.
As shown in fig. 5, according to another embodiment of the present invention, the data latch output terminal 22b of the JK flip-flop 22 is connected to the driving input terminal 3a of the driving circuit 3, and the output signal of the JK flip-flop 22 is transmitted to the driving circuit 3. The input signal is converted into a step signal by the driving circuit 3 and transmitted to the event timer 4, the event timer 4 and the driving circuit 3 form a loop, and the event timer 4 starts timing. In the present embodiment, a darlington tube is used as the drive circuit 3. In practical application, the driving circuit 3 can be realized by adopting an MC1413 chip, and the event timer 4 is realized by adopting an aerospace measurement and control AMC4500 board.
As shown in fig. 5, according to another embodiment of the present invention, the test circuit of the present invention further includes a reset circuit 5. In the present embodiment, the reset circuit 5 is connected to the clear terminal 23e of the JK flip-flop 22. When the reset switch 5a of the reset circuit 5 is closed, the reset circuit 5 is turned on, and the clear terminal 23e of the JK flip-flop 22 is turned on, and the JK flip-flop 22 performs a clear operation.
According to the test circuit, on the basis of ensuring the isolation safety between the spacecraft measurement point and the ground test system, the timing of various input signals can be met. The logic operation circuit 21 integrates the input signals, and the JK flip-flop 22 latches the signals. The combination of the logic operation circuit 21 and the JK trigger 22 can count time after performing logic operation on the input complex multi-channel signals, and high-precision testing on the multi-channel signals is guaranteed.
In conjunction with fig. 1 and 8, according to another embodiment of the present invention, the input signal inputted by the isolation circuit 1 may be more than two. The number of the isolation sub-circuits in the corresponding isolation circuit 1 is increased. The arrangement of the delay circuits 2 connected to the isolation circuit 1 is changed, especially the arrangement number and the arrangement of the logic operation circuits in the delay circuits 2. In this embodiment, the connection modes of the isolation circuit 1, the delay circuit 2, the driving circuit 3, the event timer 4 and the reset circuit 5 have been described in detail in the foregoing embodiment, and are not described again here.
According to the time delay circuit, different time delay circuits 2 can be combined and arranged according to the number and types of test signals, and the use of the isolation circuit 1 is combined, so that the applicability of the test circuit is improved. The test and accurate timing of the complex signals of the spacecraft are further met.
Note that, in this embodiment, the input signal is a voltage signal or a contact signal. If the input signal is a voltage signal, the output end for outputting the input signal is connected with the input end of the isolation circuit. If the input signal is a contact signal, the contact signal is converted into a voltage signal through the power supply driving conversion device. The output terminal for outputting the input signal is then connected to the input terminal of the isolation circuit. As shown in fig. 9, the contact signal X is connected to the switching device 6, and the switching device 6 is a relay switch. The contact signal X is connected via a line to a coil 61 on the switching device 6, and a switch contact 62 on the switching device 6 is connected to the power supply. The switch contact 61 on the conversion device 6 is switched on and off through the contact signal X, so that a voltage signal Y is generated at the switch contact 61, and the process of converting the contact signal X into the voltage signal Y is realized.
The foregoing is illustrative of specific embodiments of the present invention and reference should be made to the implementation of apparatus and structures not specifically described herein, which is understood to be a general purpose apparatus and method of operation known in the art.
The above description is only one embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A test circuit for a spacecraft, comprising:
the input end of the isolation circuit is used for receiving an input signal;
the input end of the delay circuit is connected with the output end of the isolation circuit;
the input end of the driving circuit is connected with the output end of the delay circuit;
the input end of the event timer is connected with the output end of the driving circuit;
the delay circuit comprises a logic operation circuit and a JK trigger, wherein the input end of the logic operation circuit is connected with the output end of the isolation circuit; the output end of the logic operation circuit is connected with the input end of the JK trigger; the output end of the JK trigger is connected with the input end of the driving circuit;
the logic operation circuit comprises a first gate circuit and a second gate circuit, wherein the first gate circuit is a logic OR gate circuit, and the second gate circuit is a logic NAND gate circuit;
the input end of the first gate circuit is connected with the output end of the isolation circuit, and the output end of the first gate circuit is connected with the clock end of the JK trigger;
the input end of the second gate circuit is connected with the output end of the isolation circuit, and the output end of the second gate circuit is connected with the clock end of the JK trigger;
when the clock end of the JK trigger receives a time sequence signal which is a falling edge, the data latch output end of the JK trigger is switched from a high-impedance state to a high-level state;
the data latch output end of the JK trigger is connected with the input end of the driving circuit;
and the output signal of the JK trigger is converted into a step signal through the driving circuit and is transmitted to the event timer.
2. The test circuit of claim 1, wherein the isolation circuit employs a TLP521-4 optocoupler.
3. The test circuit of claim 1, wherein the driver circuit employs a darlington tube.
4. The test circuit of claim 1, further comprising a reset circuit connected to the clear terminal of the JK flip-flop.
5. The test circuit of claim 1, wherein the input signal is a voltage signal; alternatively, the input signal is a contact signal.
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| CN201711039327.XA CN107884641B (en) | 2017-10-27 | 2017-10-27 | Test circuit for spacecraft |
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| CN201711039327.XA CN107884641B (en) | 2017-10-27 | 2017-10-27 | Test circuit for spacecraft |
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| CN107884641A CN107884641A (en) | 2018-04-06 |
| CN107884641B true CN107884641B (en) | 2020-09-15 |
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| CN201681144U (en) * | 2010-04-15 | 2010-12-22 | 佛山奇正电气有限公司 | Sample action detection switching circuit of time-delay characteristic testing equipment |
| CN202013387U (en) * | 2011-01-13 | 2011-10-19 | 东莞桥头技研新阳电器厂 | Charger detection circuit |
| CN104142651B (en) * | 2014-07-21 | 2017-06-27 | 北京宇航***工程研究所 | A kind of switch gate signal measuring circuit |
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