CN107862101B

CN107862101B - Circuit structure of completely new architecture physical unclonable function based on arbiter

Info

Publication number: CN107862101B
Application number: CN201710816440.8A
Authority: CN
Inventors: 徐崇耀; 熊晓明; 郑欣
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2017-09-12
Filing date: 2017-09-12
Publication date: 2021-01-05
Anticipated expiration: 2037-09-12
Also published as: CN107862101A

Abstract

The invention discloses a circuit structure of a physical unclonable function with a reconfigurable structure based on an arbiter, which consists of n MUX groups, n arbiters and 2n-2 MUXs. The internal structure of each MUX Group is formed by j groups of MUXs which are symmetrically arranged and are transmitted in a front-back cross mode. The two paths of output signals of the MUX Group are connected with the arbiter and also used as the input of two symmetrically arranged MUXs, the other input ends of the two MUXs are connected with a system clock, and the output ends of the MUXs are connected with the input of the next-stage MUX Group. The selection signal of the MUX can control whether the input signal of the next level MUX Group comes from the output of the previous level or the system clock. The PUF structure can realize series connection and parallel connection of MUX groups at all levels, thereby realizing the reconfiguration of the PUF structure and realizing the simultaneous output of single-bit or multi-bit effective data.

Description

Circuit structure of completely new architecture physical unclonable function based on arbiter

Technical Field

The invention relates to a design of a physical unclonable function in the field of integrated circuits, in particular to a circuit structure of a physical unclonable function with a reconfigurable structure based on an arbiter.

Background

The unclonable function based on the arbiter is an implementation form of a Physical Unclonable Function (PUF) on a silicon chip, and a characteristic quantity uniquely related to an object is extracted mainly by utilizing physical randomness generated by manufacturing process deviation of a device. By means of the characteristic quantity, the corresponding object can be uniquely identified and the characteristic quantity cannot be copied because process variations in the production process cannot be copied. Therefore, PUFs based on semiconductor technology have the properties of irreproducibility, uniqueness, stability, immune-invasive attack. The current popular symmetric encryption algorithms AES, SM4, etc. need to store the key in the non-volatile storage, which is easily attacked by intrusion, resulting in the key being copied and stolen. The silicon-based arbiter PUF can prevent invasive attack and prevent the key from being copied and stolen, so the PUF can be widely applied to the fields of chip authentication, key storage and the like. Fig. 1 is a circuit schematic of a conventional fabric arbiter PUF circuit, which consists of a delay path and an arbiter at the end of the delay path. The delay path is composed of a plurality of nodes, each node being composed of two 1-out-of-2 data Selectors (MUXs). Two MUXs in a node must be symmetrically arranged, and a connecting line with the next node MUX must be symmetrical. When the control signal is 1, the output of the two MUXs of the previous node is transmitted to the output of the two MUXs of the node in parallel; when the control signal is 0, the outputs of the two MUXs of the previous node are transmitted to the outputs of the two MUXs of the current node in a cross way. When a transition signal from 0 to 1 enters the delay path, the transition signal will pass through each node in parallel or in cross, depending on the node control signals (C1, C2, …, C N). If the delay path has n nodes, there are 2n transmission paths. Finally, the jump signal will arrive at two input ends of the arbiter in sequence after being output from the two MUXs of the end node of the delay path, and the arbiter judges which signal arrives first by outputting 0 or 1. Ideally, when the two MUXs of each node are physically placed in strict symmetry, the connection lines between the nodes are also strictly symmetric, and then the transition signal theoretically arrives at the two input ends of the arbiter at the same time. In fact, there is a process variation in the chip manufacturing process, which causes the lengths of two delay paths through which the jump signal passes to be different, and thus causes transmission delays to be different, and the output of the arbiter reflects this physical randomness. As can be seen from the structure of a conventional PUF, the structure cannot be dynamically altered and only one bit of valid data can be generated per cycle.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, and provides a brand-new PUF structure based on the original structure, wherein the structure can select a signal S_i,i∈[1,n-1]The trend of a clock signal and a preceding-stage output signal is changed to realize reconstruction of the PUF circuit structure and change of output, meanwhile, the circuit structure can realize simultaneous output of multi-bit effective data in one period, and at most, n-bit effective data output can be realized in one period.

The purpose of the invention is realized by the following technical scheme: the structure consists of n MUX groups, n arbiters and 2n-2 MUXs. The internal structure of each MUX Group is shown in fig. 3, which is similar to a conventional arbiter-based PUF circuit, and the muxes are symmetrically arranged by j pairs and cross-transmitted back and forth. The two paths of output signals of the MUX Group are connected with the arbiter and also used as the input of two symmetrically arranged MUXs, the other input ends of the two MUXs are connected with a system clock, and the output ends of the MUXs are connected with the input of the next-stage MUX Group. Therefore, the selection signal S of MUX_i,i∈[1,n-1]It is possible to control whether the input signal of the next stage MUX Group comes from the output of the previous stage or from the system clock. By controlling S_i,i∈[1,n-1]The serial connection and the parallel connection of MUX groups at each level can be realized, so that the reconfiguration of the PUF structure is realized, and the simultaneous output of single-bit or multi-bit effective data is realized.

Compared with the prior art, the invention has the following advantages and effects:

1. the dynamic adjustment of the PUF circuit structure based on the arbiter is realized;

2. the simultaneous output of single-bit effective data or multi-bit effective data in a single clock cycle can be realized.

Drawings

FIG. 1 is a diagram of a conventional architecture of an arbiter-based PUF;

FIG. 2 is a circuit configuration of the present invention;

FIG. 3 shows the internal structure of the MUX Group in the present invention.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.

The PUF circuit comprises n MUX groups, n arbiters and 2n-2 MUXs. The internal structure of the MUX Group is shown in fig. 3, and it is mainly composed of a plurality of nodes, and each node is composed of two 2-to-1 data Selectors (MUXs). Two MUXs in a node must be strictly symmetrically arranged, and a connecting line with the next node MUX must be symmetrical. When the control signal is 0, the output of the two MUXs of the previous node is transmitted to the output of the two MUXs of the node in parallel; when the control signal is 1, the outputs of the two MUXs of the previous node are transmitted to the outputs of the two MUXs of the current node in a cross way. When a transition signal from 0 to 1 enters the delay path, the transition signal will pass through each node in parallel or in cross, depending on the node control signals (C1, C2, …, C N). If the delay path has n nodes, there are 2n transmission paths. Finally, the transition signal is output from both MUXs of the delay path end node. When the two MUXs of each node are placed strictly symmetrically physically, the connecting line between the nodes is also strictly symmetrical, and then the jump signals theoretically reach the output end at the same time. In fact, there is a process variation in the chip manufacturing process, which causes the lengths of the two delay paths through which the jump signal passes to be different, and thus causes the transmission delay to be different. Therefore, the arrival time of the transition signal at the output terminal also varies.

After two paths of jump signals are output, the two paths of jump signals are connected to the input ends of the MUX which are symmetrically arranged in the other group, and the signals S are used for outputting_i,i∈[1,n-1]And controlling whether the input is input into the next-stage MUX Group. If the control signal is 0, the jump signal is input to the next-stage MUX Group to be continuously transmitted, and at the moment, the front stage and the rear stage form a series structure. If the control signal is 1, the two paths of jump signals are input into the arbiter and generate 1-bit effective signals, and the signals reflect physical random information such as process deviation and the like existing in the current MUX Group in the chip manufacturing process; meanwhile, the input of the next-stage MUX Group is a system clock, and the preceding stage and the subsequent stage form a parallel structure at the moment.

The arbiter in the PUF structure is composed of a D trigger, and the main function of the D trigger is to judge which path of the two paths of jump signals arrives first and output 0 or 1 according to different arrival sequences.

In the practical application process, the number of the MUX groups and the number of nodes in each MUX Group can be determined according to the practical requirements. The PUF circuit has data inputs C1, C2, …, Ci, data outputs R1, R2, …, Rn, and control inputs S1, S2, …, Sn.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims

1. A circuit structure of a reconfigurable physical unclonable function based on the structure of an arbiter, the circuit structure comprising n MUX groups, n arbiters, an n-level structure of 2n-2 MUXs and a system clock,

wherein the MUX Group has 4 inputs and 2 outputs, the arbiter has 2 inputs and 2 outputs, and the MUX has 2 inputs and 1 output;

each stage of the n-stage structure comprises one MUX Group and one arbiter, wherein 2 outputs of the MUX Group of each stage are used as 2 inputs of the arbiter, 2 MUXs are arranged between every two stages, the 2 outputs of the MUX Group of each stage except the MUX Group of the last stage are also respectively used as one input of each MUX of the 2 MUXs between the two stages, the other input of each MUX is the system clock, the 2 outputs of the 2 MUXs between the two stages are also used as the MUX Group inputs except the first stage, and the input of the first MUX Group is the system clock;

the outputs of the n arbiters are the outputs of the circuit arrangement.

2. The circuit structure of a physically unclonable function reconfigurable based on the structure of an arbiter of claim 1,

each MUX Group consists of j groups of symmetrically arranged MUXs which are transmitted in a front-back cross way, and a selection signal S of each MUX_i,i∈[1，n-1]The input signal of the next-stage MUX Group can be controlled to be from the output of the previous stage or from the system clock; by controlling S_i,i∈[1，n-1]The serial connection and the parallel connection of MUX groups at each level can be realized, so that the reconfiguration of the PUF structure is realized, and the simultaneous output of single-bit or multi-bit effective data is realized.