CN107861775A - A kind of SSD starts control device and method - Google Patents
A kind of SSD starts control device and method Download PDFInfo
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- CN107861775A CN107861775A CN201711260942.3A CN201711260942A CN107861775A CN 107861775 A CN107861775 A CN 107861775A CN 201711260942 A CN201711260942 A CN 201711260942A CN 107861775 A CN107861775 A CN 107861775A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44568—Immediately runnable code
- G06F9/44578—Preparing or optimising for loading
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Abstract
The invention discloses a kind of SSD to start control device and method, including：Main control chip, CPLD chips and multiple storage chips；Wherein, main control chip is connected with CPLD chips, and CPLD chips are connected with multiple storage chips respectively；When write-in starts code, main control chip will start code and send to CPLD chips, CPLD chips by the data received be divided into storage chip quantity identical some, and various pieces are written in parallel to multiple storage chips；When reading startup code, CPLD chips are read from multiple storage chips parallel starts code, and the data read are sent to main control chip, to realize SSD startup.The characteristics of the application is far above storage chip using the characteristic and CPLD of CPLD internal module concurrent workings with main control chip clock frequency, reduces main control chip and read the time started needed for code, so as to significantly reduce the SSD startup time.
Description
Technical field
The present invention relates to computer memory technical field, starts control device and method more particularly to a kind of SSD.
Background technology
Solid state hard disc (Solid State Drives, SSD) is manufactured hard disk with solid-state electronic storage chip array,
It is made up of control unit and memory cell (FLASH chip, dram chip).Solid state hard disc has what traditional mechanical hard disk did not possessed
Fast reading and writing, light weight, energy consumption be low and the features such as small volume.
NVMe standards are the new storage specification standards established for SSD, and NVMe standards make SSD support PCIe buses to enter line number
According to interaction, and support SMBus buses or I2C buses as outband management interface.
Influenceing the factor of SSD startup times includes SSD power supply settling times, master control startup code (BootLoader) loading
Time and System Initialization time.Due to the development of power technology, SSD power supply settling times have shortened to Millisecond, and
Improved constantly with the clock frequency of master control, storage medium chip, System Initialization time has also significantly shortened, therefore, main
Control chip and start the code load time into the principal element for restricting SSD toggle speeds.The startup code of main control chip leads to
Often it is stored in the non-volatile memory chips such as EEPROM or NorFLASH, after power supply is established, main control chip passes through serial total
Line (being usually spi bus or I2C buses) is read from storage chip starts code, and SSD function is abundanter, then starts code
Size of code it is bigger, in the case where the clock frequency of universal serial bus is certain, it is longer to start the load time of code, due to current
The universal serial bus clock frequency that EEPROM or NorFLASH storage chips are supported typically only has several M to tens M, far below master control core
The clock frequency of piece, therefore the load time for starting code may be up to several seconds even tens of seconds.
Therefore, how to reduce the SSD startup time is those skilled in the art's technical problem urgently to be resolved hurrily.
The content of the invention
It is an object of the invention to provide a kind of SSD to start control device and method, longer to solve the existing SSD startup times
The problem of.
In order to solve the above technical problems, the present invention, which provides a kind of SSD, starts control device, including：
Main control chip, CPLD chips and multiple storage chips；
Wherein, the main control chip is connected with the CPLD chips, the CPLD chips respectively with multiple storage cores
Piece is connected；
When write-in starts code, the main control chip is sent code is started to the CPLD chips, the CPLD cores
Piece by the data received be divided into the storage chip quantity identical some, and by various pieces be written in parallel to
Multiple storage chips；When reading startup code, the CPLD chips read from multiple storage chips open parallel
Dynamic code, and the data read are sent to the main control chip, to realize SSD startup.
Alternatively, the storage chip is two panels, and the startup code is divided into two parts by the CPLD chips, will be strange
The data of numeral section are written to the first storage chip, and the data of even bytes are written into the second storage chip.
Alternatively, the main control chip is connected by the first universal serial bus with the CPLD chips.
Alternatively, first universal serial bus is SMBus buses or I2C buses.
Alternatively, the CPLD chips are connected with multiple storage chips respectively by the second universal serial bus.
Alternatively, second universal serial bus is spi bus or I2C buses.
Alternatively, the universal serial bus clock frequency between the CPLD chips and the main control chip is the CPLD chips
More than twice of universal serial bus clock frequency between the storage chip.
Present invention also offers a kind of SSD to start control method, including：
When write-in starts code, main control chip will start code and send to CPLD chips, the CPLD chips and will receive
To data be divided into storage chip quantity identical some, and various pieces are written in parallel to multiple storages
Chip；
When reading startup code, the CPLD chips are read from multiple storage chips parallel starts code, and
The data read are sent to the main control chip, to realize SSD startup.
Alternatively, the CPLD chips by the data received be divided into storage chip quantity identical some, and
And various pieces are written in parallel to multiple storage chips included：
The storage chip is two panels, and the startup code is divided into two parts by the CPLD chips, by odd bytes
Data be written to the first storage chip, the data of even bytes are written to the second storage chip.
SSD provided by the present invention starts control device, including：Main control chip, CPLD chips and multiple storage chips；
Wherein, main control chip is connected with CPLD chips, and CPLD chips are connected with multiple storage chips respectively；When write-in starts code,
Main control chip sends startup code to be divided into the data received identical with storage chip quantity to CPLD chips, CPLD chips
Some, and various pieces are written in parallel to multiple storage chips；When reading startup code, CPLD chips are parallel
Read from multiple storage chips and start code, and the data read are sent to main control chip, to realize SSD startup.
The application is far above storage chip using the characteristic and CPLD of CPLD internal module concurrent workings with main control chip clock frequency
The characteristics of, reduce main control chip and read the time started needed for code, so as to significantly reduce the SSD startup time.In addition,
Present invention also provides a kind of SSD with above-mentioned technological merit to start control method.
Brief description of the drawings
, below will be to embodiment or existing for the clearer explanation embodiment of the present invention or the technical scheme of prior art
The required accompanying drawing used is briefly described in technology description, it should be apparent that, drawings in the following description are only this hair
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of structured flowchart for embodiment that SSD provided by the present invention starts control device；
Fig. 2 is the structured flowchart for another embodiment that SSD provided by the present invention starts control device；
Fig. 3 is the flow chart that SSD provided in an embodiment of the present invention starts control method.
Embodiment
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.Obviously, described embodiment is only part of the embodiment of the present invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to the scope of protection of the invention.
SSD provided by the present invention starts a kind of structured flowchart of embodiment of control device as shown in figure 1, should
Equipment includes：
Main control chip 1, CPLD chips 2 and multiple storage chips 3；
Wherein, the main control chip 1 is connected with the CPLD chips 2, the CPLD chips 2 respectively with multiple storages
Chip 3 is connected；
When write-in starts code, the main control chip 1 is sent code is started to the CPLD chips 2, the CPLD
Chip 2 by the data received be divided into the quantity identical some of storage chip 3, and by various pieces concurrent write
Enter to multiple storage chips 3；When reading startup code, the CPLD chips 2 are parallel from multiple storage chips 3
Read and start code, and the data read are sent to the main control chip 1, to realize SSD startup.
It is pointed out that storage chip can be multiple in the embodiment of the present application, its quantity is not limited to.Have as one kind
Body embodiment, storage system can be carried out using two panels storage chip and starts code.
The application uses outband management chip of the CPLD chips as SSD, and as startup code storage chip and master control
The transfer of data transfer between chip.
It is possible to further respectively configure a serial communication bus interface to master control and storage chip for CPLD chips, with
The serial bus interface clock frequency of Master Communications is twice with storage chip communication clock frequency.
SSD provided by the present invention starts control device, including：Main control chip, CPLD chips and multiple storage chips；
Wherein, main control chip is connected with CPLD chips, and CPLD chips are connected with multiple storage chips respectively；When write-in starts code,
Main control chip sends startup code to be divided into the data received identical with storage chip quantity to CPLD chips, CPLD chips
Some, and various pieces are written in parallel to multiple storage chips；When reading startup code, CPLD chips are parallel
Read from multiple storage chips and start code, and the data read are sent to main control chip, to realize SSD startup.
The application is far above storage chip using the characteristic and CPLD of CPLD internal module concurrent workings with main control chip clock frequency
The characteristics of, reduce main control chip and read the time started needed for code, so as to significantly reduce the SSD startup time.
As a kind of embodiment, storage chip can be specially two panels in the application.CPLD chips open described
Dynamic code is divided into two parts, and the data of odd bytes are written into the first storage chip, the data of even bytes are written to
Second storage chip.
Main control chip is connected by the first universal serial bus with the CPLD chips.Main control chip by the first universal serial bus with
The CPLD chips connection.CPLD chips are connected with multiple storage chips respectively by the second universal serial bus.Described second
Universal serial bus is spi bus or I2C buses.
As shown in the structured flowchart of Fig. 2 SSD provided by the present invention another embodiments for starting control device,
Startup code is divided into two parts and is respectively stored into two panels storage chip by the present embodiment, and the storage chip capacity of selection can reduce
To 50% of capacity needed for original, outband management chip selects piece of CPLD chip, the VPD generally carried out except outband management chip
Information storage, SSD monitoring running states, and function is interacted etc. by SMBus buses or I2C buses and HOST (main frame)
Outside, two-way serial bus interface (spi bus or I2C buses, be consistent with storage chip serial line interface) is configured in addition respectively
Two panels storage chip is connected to, serial bus interface all the way is configured in addition and is connected to main control chip.CPLD chips and main control chip
Between universal serial bus clock frequency can be configured to twice of the universal serial bus clock frequency between CPLD chips and storage chip
More than.
When that will start in code write-in storage chip, main control chip is sent code to CPLD cores by universal serial bus
Piece, code is write two panels storage chip by CPLD chips simultaneously respectively by universal serial bus, during write-in, by odd number word
The data of section write the first storage chip, and the data of even bytes are write into the second storage chip.Read and start in main control chip
During code, CPLD chips read data from the first storage chip and the second storage chip by universal serial bus simultaneously,
And send the data read to master control by universal serial bus, during transmission, the number that is read from the first storage chip
According to preceding, rear, order when being write with code is consistent the data read from the second storage chip.
Start control method to SSD provided in an embodiment of the present invention below to be introduced, SSD described below starts control
Method starts control device with above-described SSD can be mutually to should refer to.
Fig. 3 is the flow chart that SSD provided in an embodiment of the present invention starts control method, and reference picture 3SSD starts control method
It can include：
Step S101：When write-in starts code, main control chip is sent code is started to CPLD chips, the CPLD cores
Piece by the data received be divided into storage chip quantity identical some, and various pieces are written in parallel to multiple
The storage chip；
Step S102：When reading startup code, the CPLD chips read from multiple storage chips open parallel
Dynamic code, and the data read are sent to the main control chip, to realize SSD startup.
Alternatively, the CPLD chips by the data received be divided into storage chip quantity identical some, and
And various pieces are written in parallel to multiple storage chips included：
The storage chip is two panels, and the startup code is divided into two parts by the CPLD chips, by odd bytes
Data be written to the first storage chip, the data of even bytes are written to the second storage chip.
The SSD of the present embodiment starts control method and is used for foregoing SSD startup control devices, therefore SSD starts controlling party
The visible SSD hereinbefore of embodiment in method starts the embodiment part of control device, so, its embodiment
The description of corresponding various pieces embodiment is referred to, will not be repeated here.
SSD provided by the present invention starts control method, and when write-in starts code, main control chip will start code and send
To CPLD chips, CPLD chips by the data received be divided into storage chip quantity identical some, and will be each
Part parallel is write to multiple storage chips；When reading startup code, CPLD chips are read from multiple storage chips parallel
Start code, and the data read are sent to main control chip, to realize SSD startup.The application utilizes CPLD internal modes
The characteristics of characteristic and CPLD of block concurrent working are far above storage chip with main control chip clock frequency, reduce main control chip
The time needed for startup code is read, so as to significantly reduce the SSD startup time.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be with it is other
The difference of embodiment, between each embodiment same or similar part mutually referring to.For dress disclosed in embodiment
For putting, because it is corresponded to the method disclosed in Example, so description is fairly simple, related part is referring to method part
Explanation.
Professional further appreciates that, with reference to the unit of each example of the embodiments described herein description
And algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, the composition and step of each example are generally described according to function in the above description.These
Function is performed with hardware or software mode actually, application-specific and design constraint depending on technical scheme.Specialty
Technical staff can realize described function using distinct methods to each specific application, but this realization should not
Think beyond the scope of this invention.
Directly it can be held with reference to the step of method or algorithm that the embodiments described herein describes with hardware, processor
Capable software module, or the two combination are implemented.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Control device is started to SSD provided by the present invention above and method is described in detail.It is used herein
Specific case is set forth to the principle and embodiment of the present invention, and the explanation of above example is only intended to help and understands
The method and its core concept of the present invention.It should be pointed out that for those skilled in the art, this is not being departed from
On the premise of inventive principle, some improvement and modification can also be carried out to the present invention, these are improved and modification also falls into the present invention
In scope of the claims.
Claims (9)
1. a kind of SSD starts control device, it is characterised in that including：
Main control chip, CPLD chips and multiple storage chips；
Wherein, the main control chip is connected with the CPLD chips, the CPLD chips respectively with multiple storage chip phases
Even；
When write-in starts code, startup code is sent to the CPLD chips, the CPLD chips and incited somebody to action by the main control chip
The data received be divided into the storage chip quantity identical some, and various pieces are written in parallel to multiple
The storage chip；When reading startup code, the CPLD chips are read from multiple storage chips parallel starts generation
Code, and the data read are sent to the main control chip, to realize SSD startup.
2. SSD as claimed in claim 1 starts control device, it is characterised in that the storage chip is two panels, the CPLD
The startup code is divided into two parts by chip, the data of odd bytes is written into the first storage chip, by even bytes
Data be written to the second storage chip.
3. SSD as claimed in claim 1 or 2 starts control device, it is characterised in that the main control chip is serial by first
Bus is connected with the CPLD chips.
4. SSD as claimed in claim 3 starts control device, it is characterised in that first universal serial bus is SMBus buses
Or I2C buses.
5. SSD as claimed in claim 3 starts control device, it is characterised in that the CPLD chips are serial total by second
Line is connected with multiple storage chips respectively.
6. SSD as claimed in claim 5 starts control device, it is characterised in that second universal serial bus be spi bus or
I2C buses.
7. SSD as claimed in claim 5 starts control device, it is characterised in that the CPLD chips and the main control chip
Between universal serial bus clock frequency of the universal serial bus clock frequency between the CPLD chips and the storage chip two
More than times.
8. a kind of SSD starts control method, it is characterised in that including：
When write-in starts code, main control chip will start code and send to CPLD chips, and the CPLD chips will receive
Data be divided into storage chip quantity identical some, and various pieces are written in parallel to multiple storage cores
Piece；
When reading startup code, the CPLD chips are read from multiple storage chips parallel starts code, and will read
The data got are sent to the main control chip, to realize SSD startup.
9. SSD as claimed in claim 8 starts control method, it is characterised in that the data that the CPLD chips will receive
Be divided into storage chip quantity identical some, and various pieces are written in parallel to multiple storage chip bags
Include：
The storage chip is two panels, and the startup code is divided into two parts by the CPLD chips, by the number of odd bytes
According to the first storage chip is written to, the data of even bytes are written to the second storage chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711260942.3A CN107861775A (en) | 2017-12-04 | 2017-12-04 | A kind of SSD starts control device and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711260942.3A CN107861775A (en) | 2017-12-04 | 2017-12-04 | A kind of SSD starts control device and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109144914A (en) * | 2018-07-25 | 2019-01-04 | 郑州云海信息技术有限公司 | Communication means and CPLD between a kind of storage server, mainboard and hard disk |
| WO2021159494A1 (en) * | 2020-02-14 | 2021-08-19 | 华为技术有限公司 | Solid-state drive and control method for solid-state drive |
| CN116719583A (en) * | 2023-08-08 | 2023-09-08 | 飞腾信息技术有限公司 | Starting method, programmable logic device, computing equipment and storage medium |
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| US20140115315A1 (en) * | 2011-12-27 | 2014-04-24 | Prasun Ratn | Optimized cold boot for non-volatile memory |
| CN107273316A (en) * | 2017-06-08 | 2017-10-20 | 迈普通信技术股份有限公司 | Parallel FLASH accesses system and method |
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| CN201741409U (en) * | 2010-07-26 | 2011-02-09 | 浪潮电子信息产业股份有限公司 | Large-capacity NAND FLASH expansion module |
| US20140115315A1 (en) * | 2011-12-27 | 2014-04-24 | Prasun Ratn | Optimized cold boot for non-volatile memory |
| CN102609291A (en) * | 2012-02-29 | 2012-07-25 | 记忆科技(深圳)有限公司 | Solid-state disk and system start-up method based on same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109144914A (en) * | 2018-07-25 | 2019-01-04 | 郑州云海信息技术有限公司 | Communication means and CPLD between a kind of storage server, mainboard and hard disk |
| WO2021159494A1 (en) * | 2020-02-14 | 2021-08-19 | 华为技术有限公司 | Solid-state drive and control method for solid-state drive |
| CN116719583A (en) * | 2023-08-08 | 2023-09-08 | 飞腾信息技术有限公司 | Starting method, programmable logic device, computing equipment and storage medium |
| CN116719583B (en) * | 2023-08-08 | 2023-11-10 | 飞腾信息技术有限公司 | Starting method, programmable logic device, computing equipment and storage medium |
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Application publication date: 20180330 |