CN107844330A - A kind of method and system of enhancing ARM startup of server code reliabilities - Google Patents
A kind of method and system of enhancing ARM startup of server code reliabilities Download PDFInfo
- Publication number
- CN107844330A CN107844330A CN201711011982.4A CN201711011982A CN107844330A CN 107844330 A CN107844330 A CN 107844330A CN 201711011982 A CN201711011982 A CN 201711011982A CN 107844330 A CN107844330 A CN 107844330A
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- Prior art keywords
- code
- flash chip
- spi
- startup
- backup
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1417—Boot up procedures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1456—Hardware arrangements for backup
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Hardware Redundancy (AREA)
Abstract
The present invention provides a kind of method and system of enhancing ARM startup of server code reliabilities, and methods described includes：Main Flash chip and backup Flash chip are set；When upgrading BIOS code or modification configuration parameter, circuit switching is carried out, amended startup code is transmitted to backup Flash chip from main Flash chip；When working properly, using the startup code in main Flash chip；When bios code damage or main Flash chip are damaged, Flash chip switching is carried out, uses the startup code of backup Flash chip.The present invention is by setting backup Flash chip, backed up to starting code, it is low so as to solve existing startup code reliability, when start code damage when easily cause system delay machine the problem of, by switching switching of the switch to annexation, backup and the switch operating of startup code can be achieved, enhance and start code reliability, improve server stability.
Description
Technical field
The present invention relates to server technology field, particularly a kind of method of enhancing ARM startup of server code reliabilities
With system.
Background technology
For current ARM server systems, after startup of server, CPU can read startup code, and then according to startup
Code configures to system, finally enters operating system, starts normal work.And the startup code of server is stored in circuit
In Flash chip in, in the course of server use, operation maintenance personnel can to start code carry out online updating, can also
Configured by user interface to starting code.
As shown in figure 1, in current server design, the Flash Memory chips that storage starts code pass through SPI
Bus is connected with PCH, and CPU reads the startup code in Flash chip by PCH.
If during server use because it is artificial the reason for cause to start the factor (example in code damage or the external world
Such as system voltage fluctuation or electrostatic) cause the damage of Flash chip physical property all to cause server failure.To ensure to start
Code section normal operation, in hardware design, ensure system after power-up, CPU enters to Flash Memory content again
Row read-write, that is, meet the electrifying timing sequence of Flash chip interlock circuit part.On Software for Design, generally in Flash chip
A region is individually done in inside, for being backed up to starting key parameter in code, can add again when starting code damage
Carry covering.But it has the drawback that Flash finite capacity, it is impossible to all backs up whole bios code, can only back up pass
Key section, and when the part of damage is not backed up, the technical scheme does not have feasibility.
The content of the invention
It is an object of the invention to provide a kind of method and system of enhancing ARM startup of server code reliabilities, it is intended to solves
Certainly it is existing startup code reliability it is low, when start code damage when easily cause system delay machine the problem of, enhancing start code can
By property, server stability is improved.
To reach above-mentioned technical purpose, the invention provides a kind of method of enhancing ARM startup of server code reliabilities,
Comprise the following steps：
Main Flash chip and backup Flash chip are set；
When upgrading BIOS code or modification configuration parameter, circuit switching is carried out, by the amended code that starts from master
Flash chip is transmitted to backup Flash chip；
When working properly, using the startup code in main Flash chip；When bios code damage or main Flash cores
When piece damages, Flash chip switching is carried out, uses the startup code of backup Flash chip.
Preferably, the circuit, which switches, is specially：
In normal operation, spi bus and the SPI for transmitting SPI_FLASH1 signals for transmitting SPI_CPU signals are total
Line is connected, and after circuit switching, transmits spi bus phase of the spi bus of SPI_FLASH1 signals with transmitting SPI_MCU1 signals
Even and by the spi bus for transmitting SPI_FLASH2 signals with transmitting the spi bus of SPI_MCU2 signals it is connected.
Preferably, methods described also includes：
After the completion of upgrading BIOS code or modification configuration parameter, circuit is switched into normal operating conditions.
Preferably, the Flash chip, which switches, is specially：
The spi bus for transmitting SPI_CPU signals is connected with transmitting the spi bus of SPI_FLASH2 signals.
Present invention also offers a kind of system of enhancing ARM startup of server code reliabilities, including：Controller, switching
Switch, main Flash chip and backup Flash chip；
When server normal work, the main Flash chip is connected with CPU；
When server needs upgrading BIOS code or modification configuration parameter, the controller control switching switch carries out electricity
Road switches, and the controller is connected main Flash chip and backup Flash chip respectively, after the completion of backup code, the control
Circuit is switched to normal operating conditions by device control switching switch processed；
When the damage of server B ios code or main Flash chip are damaged, the controller control switching switch is carried out
Flash chip switches, and CPU is connected with backup Flash chip.
Preferably, communicated between the CPU and controller for UART.
Preferably, it is total for SPI between the switching switch and CPU, controller, main Flash chip and backup Flash chip
Line connects.
Preferably, the switching switch is the multi-channel switch based on CPLD.
The effect provided in the content of the invention is only the effect of embodiment, rather than whole effects that invention is all, above-mentioned
A technical scheme in technical scheme has the following advantages that or beneficial effect：
Compared with prior art, the present invention is backed up, so as to solve by setting backup Flash chip to starting code
Determined it is existing startup code reliability it is low, when start code damage when easily cause system delay machine the problem of, and without having to worry about
The problem of memory capacity of Flash chip is inadequate.
By setting the single-chip microcomputer of switching switch and control switching switch, in code upgrade or switching is stored with and opened
During the Flash chip of dynamic code, the switching of spi bus is carried out.By switching switching of the switch to annexation, you can realization is opened
The backup of dynamic code and switch operating, enhance and start code reliability, improve server stability.
Brief description of the drawings
Fig. 1 reads design principle figure for a kind of startup of server code of the prior art；
Fig. 2 is a kind of method flow of enhancing ARM startup of server code reliability provided in the embodiment of the present invention
Figure；
Fig. 3 is a kind of system architecture of enhancing ARM startup of server code reliability provided in the embodiment of the present invention
Schematic diagram.
Embodiment
In order to the technical characterstic of clear explanation this programme, below by embodiment, and its accompanying drawing is combined, to this
Invention is described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relation between various embodiments are discussed and/or set.It should be noted that part illustrated in the accompanying drawings is not necessarily to scale
Draw.Present invention omits the description to known assemblies and treatment technology and process to avoid being unnecessarily limiting the present invention.
A kind of side of the enhancing ARM startup of server code reliability provided below in conjunction with the accompanying drawings the embodiment of the present invention
Method is described in detail with system.
As shown in Fig. 2 the embodiment of the invention discloses a kind of method of enhancing ARM startup of server code reliabilities, bag
Include following operation：
Main Flash chip and backup Flash chip are set；
When upgrading BIOS code or modification configuration parameter, circuit switching is carried out, by the amended code that starts from master
Flash chip is transmitted to backup Flash chip；
When working properly, using the startup code in main Flash chip；When bios code damage or main Flash cores
When piece damages, Flash chip switching is carried out, uses the startup code of backup Flash chip.
A region is individually done when storage due to starting code in the prior art is usual inside Flash chip, is used for
Backed up to starting key parameter in code, covering can be reloaded when starting code damage.But it has the drawback that
Flash finite capacity, it is impossible to all back up whole bios code.To solve the above problems, backup Flash chip is set,
So as to solve the problems, such as finite capacity.
Increase by one piece of Flash chip, be arranged to backup Flash chip, original Flash chip is main Flash chip.Separately
It is outer to set up switching switch, for carrying out circuit switching, realize the backup for starting code and main Flash chip and backup Flash
Switching between chip.Control for switching switch, using the single-chip microcomputer with SPI interface as controller.
In normal operation, CPU is connected by SPI_CPU signals with switching switch, will by SPI_FLASH1 signals
Main Flash chip is connected into circuit.CPU is read from main Flash chip starts code, completes the startup work of system.
When user carries out upgrading BIOS code or modification configuration parameter, CPU notice single-chip microcomputers are needed to amended
Start code to be backed up, communicated between CPU and single-chip microcomputer using UART.Modification for bios code belongs to prior art,
Do not repeat.
After the instruction for needing to carry out startup backup code is received, single-chip microcomputer control switching switch is carried out to spi bus
Switching.By the way that the spi bus for transmitting SPI_FLASH1 signals to be connected with the spi bus of transmission SPI_MCU1 signals and will pass
The spi bus of defeated SPI_FLASH2 signals with transmit SPI_MCU2 signals spi bus be connected, realize single-chip microcomputer respectively with master
Flash chip connects with backup Flash chip.Single-chip microcomputer is by the startup code copies in main Flash chip after the completion of switching
Into backup Flash, the back-up job to amended startup code is completed.
After the completion of backup, spi bus is switched back into normal operating conditions by switching switch, that is, transmits SPI_CPU signals
Spi bus is connected with transmitting the spi bus of SPI_FLASH1 signals.Meanwhile single-chip microcomputer is communicated back-up job by UART
To CPU, CPU carries out normal system and starts work the information transfer of completion.
When bios code damage or main Flash chip are damaged, system is because startup code breaks down and opens
Dynamic failure, now CPU will use to back up by UART communication notifications single-chip microcomputer starts code.
After receiving needs and carrying out starting the instruction of code using backup, single-chip microcomputer control switches switch to Flash cores
Piece switches over.By the way that the spi bus for transmitting SPI_CPU signals is connected with transmitting the spi bus of SPI_FLASH2 signals,
Realize that CPU is connected with backup Flash chip, so as to which CPU carries out system startup using the startup code in backup Flash chip
Work.
Before being switched over to Flash chip, notice custom system starts code and damaged.
The embodiment of the present invention backs up to starting code by setting backup Flash chip, realizes that server is starting
In the case that code damages, stand-by circuit is switched to, it is low so as to solve existing startup code reliability, damaged when starting code
When easily cause system delay machine the problem of, and without having to worry about the memory capacity of Flash chip it is inadequate the problem of.Switched by setting
The single-chip microcomputer of switch and control switching switch, in code upgrade or when switching is stored with the Flash chip for starting code,
Carry out the switching of spi bus.By switching switching of the switch to annexation, you can realize the backup and switching for starting code
Work, enhance and start code reliability, improve server stability.
As shown in figure 3, the embodiment of the invention also discloses a kind of system of enhancing ARM startup of server code reliabilities,
Including：Controller, switching switch, main Flash chip and backup Flash chip；
The controller is singlechip controller, and the switching switch is the multi-channel switch based on CPLD, its multichannel
Switching system is maximum to support switching road Shuo Wei 32 tunnels, singlechip controller can independent control per paths, every road that can also read back leads to
Road on off state.
When server normal work, the main Flash chip is connected with CPU, i.e. CPU by SPI_CPU signals with
Switching switch is connected, and main Flash chip is connected into circuit by SPI_FLASH1 signals.CPU is read from main Flash chip
Start code, complete the startup work of system.
When server needs upgrading BIOS code or modification configuration parameter, CPU passes through UART communication notifications single-chip microcomputer controls
Device processed needs to back up amended startup code, and the controller control switching switch carries out circuit switching, makes described
Controller connects main Flash chip and backup Flash chip respectively.Need to carry out the instruction for starting backup code receiving
Afterwards, singlechip controller control switching switch switches over to spi bus.It is total by the SPI that will transmit SPI_FLASH1 signals
Line is connected and will transmitted the spi bus of SPI_FLASH2 signals with transmitting SPI_ with the spi bus of transmission SPI_MCU1 signals
The spi bus of MCU2 signals is connected, and realizes that singlechip controller is connected with main Flash chip and backup Flash chip respectively.
Singlechip controller is completed in the startup code copies in main Flash chip to backup Flash to after modification after the completion of switching
Startup code back-up job.After the completion of backup code, the controller control switching switch switches to circuit normally
Working condition；
When the damage of server B ios code or main Flash chip are damaged, CPU will pass through UART communication notifications single-chip microcomputer controls
Device processed starts code using backup, and the controller control switching switch carries out Flash chip switching, makes CPU and backup Flash
Chip is connected.After receiving needs and carrying out starting the instruction of code using backup, singlechip controller control switches switch
Flash chip is switched over.By the way that the spi bus and the SPI for transmitting SPI_FLASH2 signals that transmit SPI_CPU signals is total
Line is connected, and realizes that CPU is connected with backup Flash chip, so as to which CPU is entered using the startup code in backup Flash chip
Row system starts work.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (8)
- A kind of 1. method of enhancing ARM startup of server code reliabilities, it is characterised in that including following operation：Main Flash chip and backup Flash chip are set；When upgrading BIOS code or modification configuration parameter, circuit switching is carried out, by the amended code that starts from main Flash cores Piece is transmitted to backup Flash chip；When working properly, using the startup code in main Flash chip；When bios code damage or main Flash chip damage Bad when, Flash chip switching is carried out, uses the startup code of backup Flash chip.
- A kind of 2. method of enhancing ARM startup of server code reliabilities according to claim 1, it is characterised in that institute Stating circuit switching is specially：In normal operation, spi bus phase of the spi bus of SPI_CPU signals with transmitting SPI_FLASH1 signals is transmitted Connection, circuit switching after, transmit SPI_FLASH1 signals spi bus with transmission SPI_MCU1 signals spi bus be connected with And the spi bus for transmitting SPI_FLASH2 signals is connected with transmitting the spi bus of SPI_MCU2 signals.
- A kind of 3. method of enhancing ARM startup of server code reliabilities according to claim 1, it is characterised in that institute Stating method also includes：After the completion of upgrading BIOS code or modification configuration parameter, circuit is switched into normal operating conditions.
- A kind of 4. method of enhancing ARM startup of server code reliabilities according to claim 1, it is characterised in that institute Stating Flash chip switching is specially：The spi bus for transmitting SPI_CPU signals is connected with transmitting the spi bus of SPI_FLASH2 signals.
- A kind of 5. system of enhancing ARM startup of server code reliabilities, it is characterised in that including：Controller, switching switch, Main Flash chip and backup Flash chip；When server normal work, the main Flash chip is connected with CPU；When server needs upgrading BIOS code or modification configuration parameter, the controller control switching switch carries out circuit and cut Change, the controller is connected main Flash chip and backup Flash chip respectively, after the completion of backup code, the controller Circuit is switched to normal operating conditions by control switching switch；When the damage of server B ios code or main Flash chip are damaged, the controller control switching switch carries out Flash cores Piece switches, and CPU is connected with backup Flash chip.
- A kind of 6. system of enhancing ARM startup of server code reliabilities according to claim 5, it is characterised in that institute State and communicated between CPU and controller for UART.
- A kind of 7. system of enhancing ARM startup of server code reliabilities according to claim 5, it is characterised in that institute State and connected between switching switch and CPU, controller, main Flash chip and backup Flash chip for spi bus.
- 8. a kind of system of enhancing ARM startup of server code reliability according to claim 5-7 any one, it is special Sign is that the switching switch is the multi-channel switch based on CPLD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711011982.4A CN107844330A (en) | 2017-10-25 | 2017-10-25 | A kind of method and system of enhancing ARM startup of server code reliabilities |
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| CN201711011982.4A CN107844330A (en) | 2017-10-25 | 2017-10-25 | A kind of method and system of enhancing ARM startup of server code reliabilities |
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| CN201711011982.4A Pending CN107844330A (en) | 2017-10-25 | 2017-10-25 | A kind of method and system of enhancing ARM startup of server code reliabilities |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110442482A (en) * | 2019-07-31 | 2019-11-12 | 苏州中科全象智能科技有限公司 | A kind of the mistake proofing framework and its control method of high-speed industrial camera firmware |
| CN110688263A (en) * | 2019-09-30 | 2020-01-14 | 中国工程物理研究院计算机应用研究所 | FPGA-based hard disk automatic switching device and application method |
| CN111078261A (en) * | 2019-11-13 | 2020-04-28 | 汉纳森（厦门）数据股份有限公司 | Flash memory upgrading device and vehicle |
| CN111399880A (en) * | 2020-03-13 | 2020-07-10 | 浪潮商用机器有限公司 | PCIe Switch configuration system, method, device and medium |
| CN111949283A (en) * | 2020-09-03 | 2020-11-17 | 苏州浪潮智能科技有限公司 | BMC Flash mirror image self-recovery system and method |
| CN112084064A (en) * | 2020-08-05 | 2020-12-15 | 锐捷网络股份有限公司 | Master-slave BIOS switching method, board card and equipment |
| CN113805786A (en) * | 2021-09-27 | 2021-12-17 | 北京微纳星空科技有限公司 | Analog signal acquisition system |
| WO2022037014A1 (en) * | 2020-08-21 | 2022-02-24 | 苏州浪潮智能科技有限公司 | Boot restoration method for arm server, and related apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110442482A (en) * | 2019-07-31 | 2019-11-12 | 苏州中科全象智能科技有限公司 | A kind of the mistake proofing framework and its control method of high-speed industrial camera firmware |
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| CN111949283B (en) * | 2020-09-03 | 2022-08-02 | 苏州浪潮智能科技有限公司 | BMC Flash mirror image self-recovery system and method |
| CN113805786A (en) * | 2021-09-27 | 2021-12-17 | 北京微纳星空科技有限公司 | Analog signal acquisition system |
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Application publication date: 20180327 |