CN107834981A - A kind of loop discharge circuit of anti-PV changes - Google Patents
A kind of loop discharge circuit of anti-PV changes Download PDFInfo
- Publication number
- CN107834981A CN107834981A CN201711114028.8A CN201711114028A CN107834981A CN 107834981 A CN107834981 A CN 107834981A CN 201711114028 A CN201711114028 A CN 201711114028A CN 107834981 A CN107834981 A CN 107834981A
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- Prior art keywords
- pmos
- nmos tube
- grid
- circuit
- drain electrode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The present invention discloses a kind of loop discharge circuit of anti-PV changes, including three-stage cascade reverser；Also include the biasing circuit being connected between the second level reverser of three-stage cascade reverser and third level reverser.Such a circuit will be applied directly to the grid of third level reverser for the bias voltage for controlling amplifier stability and precision, separated with second level reverser output with electric capacity, resetting phase, the second level exports sets DC offset voltage respectively with third level input, in work phase, second level output and third level input are passed through into electric capacity AC coupled, can avoid biasing size change caused by technique, mains voltage variations, so as to improve the stability of loop amplifier and precision.
Description
Technical field
The invention belongs to high-operational amplifier design field, more particularly to a kind of circuit knot of loop amplifier biasing technique
Structure.
Background technology
With gradually reducing for integrated circuit technology size, the intrinsic gain of metal-oxide-semiconductor declines, meanwhile, supply voltage reduces,
So that the design of high-gain amplifier is more and more difficult；In addition, traditional amplifier has at a relatively high power consumption mostly, which also limits it
Application.Loop amplifier was proposed first by Benjamin Hershberg in 2012, was applied in pipeline analog-to-digital conversions
In device.Loop amplifier it is low in energy consumption, it is simple in construction, be easy to size reduction, there are very high Research Prospects.
The stability and precision of loop amplifier, now most popular resistance biasing in close relations with its biasing circuit,
Influenceed by technique, supply voltage (abbreviation PV) serious.The change of biasing can cause loop amplifier the risk vibrated occur, together
When, precision also changes, this in operational amplifier design, be not intended to it is existing.
The content of the invention
The purpose of the present invention, it is to provide a kind of loop discharge circuit of anti-PV changes, it can make bias voltage not by electricity
The interference of source voltage change, improve the stability of loop amplifier.
In order to reach above-mentioned purpose, solution of the invention is：
A kind of loop discharge circuit of anti-PV changes, including three-stage cascade reverser；It is also anti-including being connected to three-stage cascade
Biasing circuit between the second level reverser and third level reverser of device.
Above-mentioned three-stage cascade reverser includes the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first PMOS, the
Two PMOSs and the 3rd PMOS, the drain electrode of the first NMOS tube are connected with the drain electrode of the first PMOS, the first order as circuit
Reverser, the grid of the first NMOS tube are connected with the grid of the first PMOS, and collectively as the input of circuit；2nd NMOS
The drain electrode of pipe is connected with the drain electrode of the second PMOS, as the second level reverser of circuit, the grid of the second NMOS tube and second
After the grid connection of PMOS, the drain electrode of the first NMOS tube is commonly connected to；The drain electrode of 3rd NMOS tube and the 3rd PMOS
Drain electrode connection, the third level reverser as circuit；The source electrode of first NMOS tube, the source electrode of the second NMOS tube, the 3rd
The source electrode of NMOS tube is all connected with VSS, and the source electrode of the source electrode of the first PMOS, the source electrode of the second PMOS and the 3rd PMOS connects
Meet VDD.
Above-mentioned biasing circuit includes the first electric capacity and the second electric capacity, and the both ends of the first electric capacity connect the second PMOS respectively
Drain electrode and the grid of the 3rd PMOS, the both ends of the second electric capacity connect drain electrode and the grid of the 3rd NMOS tube of the second NMOS tube respectively
Pole.
Above-mentioned biasing circuit includes the 4th PMOS, and draining for the 4th PMOS connects the grid of the 3rd PMOS, and the 4th
The source electrode of PMOS connects the first bias voltage, and the grid of the 4th PMOS connects clock signal.
Above-mentioned biasing circuit includes the 4th NMOS tube, and draining for the 4th NMOS tube N connects the grid of the 3rd NMOS tube, and the 4th
The source electrode of NMOS tube connects the second bias voltage, and the grid of the 4th NMOS tube connects clock signal.
During above-mentioned discharge circuit Closed loop operation, the grid of the first NMOS tube is connected the 3rd electric capacity with the grid of the first PMOS
Cin one end, the input of the other end of the 3rd electric capacity as circuit；The grid of the grid of first NMOS tube and the first PMOS
The 4th electric capacity Cf one end is also connected with, the other end of the 4th electric capacity connects the drain electrode of the 3rd PMOS, the drain electrode of the 3rd PMOS
Also through the 5th electric capacity CL connections VSS.
After such scheme, the present invention is by for controlling the bias voltage of amplifier stability and precision to be applied directly to the 3rd
The grid of level reverser, is separated with second level reverser output with electric capacity, is resetting phase, second level output and third level input point
DC offset voltage is not set, in work phase, second level output and third level input are passed through into electric capacity AC coupled.The present invention can
Avoid biasing size change caused by technique, mains voltage variations, so as to improve the stability of loop amplifier and precision.
Brief description of the drawings
Fig. 1 is the circuit diagram of the present invention；
Fig. 2 is the circuit diagram of Closed loop operation of the present invention；
Fig. 3 is the circuit diagram of conventional loop amplifier Closed loop operation；
When Fig. 4 is Closed loop operation of the present invention, the output simulation curve figure under TT, FS, SF, SS, FF process corner；
When Fig. 5 is conventional loop amplifier Closed loop operation, the output simulation curve figure under TT, FS, SF, SS, FF process corner；
Fig. 6 is change curve of of the invention and conventional loop amplifier the bias voltage with supply voltage.
Embodiment
Below with reference to accompanying drawing, technical scheme and beneficial effect are described in detail.
As shown in figure 1, the present invention provides a kind of loop discharge circuit of anti-PV changes, it is in loop amplifier shown in Fig. 3
On the basis of be improved, mainly second level reverser export third level reverser input between add electric capacity, multiple
It is that the input of the third level sets direct current biasing by fixed bias voltage during the phase of position, when amplifying phase, biasing circuit disconnects, the
Three-level passes through Capacitance Coupled with the second level.
Loop discharge circuit provided by the present invention, including three-stage cascade reverser and biasing circuit, wherein, three-stage cascade
Reverser includes the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, the first PMOS PM1, the second PMOS
PM2 and the 3rd PMOS PM3, the first NMOS tube NM1 drain electrode are connected with the first PMOS PM1 drain electrode, and as circuit
One-level reverser, the first NMOS tube NM1 grid are connected with the first PMOS PM1 grid, and collectively as the input of circuit
End, for connecting input signal IN；Second NMOS tube NM2 drain electrode is connected with the second PMOS PM2 drain electrode, as circuit
Second level reverser, after the second NMOS tube NM2 grid is connected with the second PMOS PM2 grid, it is commonly connected to first
NMOS tube NM1 drain electrode and the first PMOS PM1 drain electrode；3rd NMOS tube NM3 drain electrode and the 3rd PMOS PM3 drain electrode
Connection, as the third level reverser of circuit, while it is also the output end OUT of circuit；The source electrode of the first NMOS tube NM1,
Second NMOS tube NM2 source electrode, the 3rd NMOS tube NM3 source electrode is all connected with VSS, the first PMOS PM1 source electrode, the 2nd PMOS
Pipe PM2 source electrode and the 3rd PMOS PM3 source electrode are all connected with VDD.
The biasing circuit includes electric capacity C1, C2, the 4th PMOS PM4 and the 4th NMOS tube NM4, wherein, electric capacity C1's
Both ends connect the second PMOS PM2 drain electrode and the 3rd PMOS PM3 grid respectively, and electric capacity C2 both ends connect second respectively
NMOS tube NM2 drain electrode and the 3rd NMOS tube NM3 grid；4th PMOS PM4 the 3rd PMOS PM3 of drain electrode connection grid
Pole, the 4th PMOS PM4 source electrode connection bias voltage VRP, the 4th PMOS PM4 grid meet clock Rst_n；4th NMOS
Pipe NM4 drain electrode connection the 3rd NMOS tube NM3 grid, the 4th NMOS tube NM4 source electrode connection bias voltage VRP, the 4th
NMOS tube NM4 grid meets clock Rst.
As shown in Fig. 2 the present invention, in Closed loop operation, clock Rst is reset clock, Rst_n is that it is reverse, and Vthp is
The threshold voltage of PMOS, Vthn are the threshold voltages of NMOS tube.When Rst is high, NM4, PM4 are opened, and PM3 grid is set
For VRP, NM3 grid is arranged to VRN；When Rst is low, NM4, PM4 are closed, and from the second level, output passes through electric capacity to AC signal
It is coupled to the input of the third level.When amplifier establishes beginning, | Vp1-Vdd|>|Vthp|, or Vn1>Vthn.It is assumed to be | Vp1-Vdd|>|
Vthp|, load capacitance charging, output rises, by feedback, Vp1Become big, when | Vp1-Vdd|<|Vthp|,Vn1<Vthn, stop to load
Electric capacity charges, but due to overshoot current, output voltage may proceed to improve.After if overshoot occurred, | Vp1-Vdd|<|Vthp|, Vn1
<Vthn, then circuit stability.If | Vp1-Vdd|<|Vthp|,Vn1>Vthn, then output loading can be discharged, carried out and above-mentioned phase
Counter voltage change procedure.Circulation work, until | Vp1-Vdd|<|Vthp|,Vn1<Vthn, PM3, NM3 are operated in subthreshold region, whole
Individual circuit stability.
Emulated under different process angle, that observes amplifier establishes curve map, can be seen that from Fig. 4 curve of output
The precision and stability of establishing of the loop amplifier of anti-PV changes is basically unchanged.
By comparison, from fig. 5, it can be seen that traditional loop amplifier, precision changes greatly under different process angle, and establish
During there is vibration by a small margin, stability is bad.
From fig. 6, it can be seen that traditional structure, bias voltage Vp1-Vn1In mains voltage variations, significantly change, and
The circuit of anti-PV changes is basically unchanged.
The technological thought of above example only to illustrate the invention, it is impossible to protection scope of the present invention is limited with this, it is every
According to technological thought proposed by the present invention, any change done on the basis of technical scheme, the scope of the present invention is each fallen within
Within.
Claims (6)
1. a kind of loop discharge circuit of anti-PV changes, including three-stage cascade reverser；It is characterized in that：Also include being connected to three
Biasing circuit between the second level reverser and third level reverser of level cascade reverser.
A kind of 2. loop discharge circuit of anti-PV changes as claimed in claim 1, it is characterised in that：The three-stage cascade is reverse
Device includes the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first PMOS, the second PMOS and the 3rd PMOS, and first
The drain electrode of NMOS tube is connected with the drain electrode of the first PMOS, as the first order reverser of circuit, the grid of the first NMOS tube with
The grid connection of first PMOS, and collectively as the input of circuit；The drain electrode and the leakage of the second PMOS of second NMOS tube
Pole connects, and as the second level reverser of circuit, after the grid of the second NMOS tube is connected with the grid of the second PMOS, connects jointly
It is connected to the drain electrode of the first NMOS tube；The drain electrode of 3rd NMOS tube is connected with the drain electrode of the 3rd PMOS, the third level as circuit
Reverser；The source electrode of first NMOS tube, the source electrode of the second NMOS tube, the source electrode of the 3rd NMOS tube are all connected with VSS, and first
The source electrode of the source electrode of PMOS, the source electrode of the second PMOS and the 3rd PMOS is all connected with VDD.
A kind of 3. loop discharge circuit of anti-PV changes as claimed in claim 2, it is characterised in that：The biasing circuit includes
First electric capacity and the second electric capacity, the both ends of the first electric capacity connect drain electrode and the grid of the 3rd PMOS of the second PMOS respectively,
The both ends of second electric capacity connect drain electrode and the grid of the 3rd NMOS tube of the second NMOS tube respectively.
A kind of 4. loop discharge circuit of anti-PV changes as claimed in claim 2 or claim 3, it is characterised in that：The biasing circuit
Including the 4th PMOS, the grid of drain electrode the 3rd PMOS of connection of the 4th PMOS, the source electrode connection first of the 4th PMOS
Bias voltage, the grid of the 4th PMOS connect clock signal.
A kind of 5. loop discharge circuit of anti-PV changes as claimed in claim 2 or claim 3, it is characterised in that：The biasing circuit
Including the 4th NMOS tube, the grid of the 4th NMOS tube N drain electrode the 3rd NMOS tube of connection, the source electrode connection second of the 4th NMOS tube
Bias voltage, the grid of the 4th NMOS tube connect clock signal.
A kind of 6. loop discharge circuit of anti-PV changes as claimed in claim 2 or claim 3, it is characterised in that：The discharge circuit
During Closed loop operation, the grid of the first NMOS tube is connected one end of the 3rd electric capacity with the grid of the first PMOS, the 3rd electric capacity it is another
Input of the one end as circuit；The grid of first NMOS tube and the grid of the first PMOS are also connected with one end of the 4th electric capacity,
The other end of 4th electric capacity connects the drain electrode of the 3rd PMOS, and the drain electrode of the 3rd PMOS is also through the 5th capacitance connection VSS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711114028.8A CN107834981A (en) | 2017-11-13 | 2017-11-13 | A kind of loop discharge circuit of anti-PV changes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711114028.8A CN107834981A (en) | 2017-11-13 | 2017-11-13 | A kind of loop discharge circuit of anti-PV changes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107834981A true CN107834981A (en) | 2018-03-23 |
Family
ID=61655116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711114028.8A Pending CN107834981A (en) | 2017-11-13 | 2017-11-13 | A kind of loop discharge circuit of anti-PV changes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107834981A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4253033A (en) * | 1979-04-27 | 1981-02-24 | National Semiconductor Corporation | Wide bandwidth CMOS class A amplifier |
| CN2777853Y (en) * | 2004-11-01 | 2006-05-03 | 中国科学院半导体研究所 | Stable micro-power consumption CMOS voltage integrator |
| CN101640539A (en) * | 2009-06-19 | 2010-02-03 | 浙江大学 | Sigma-delta analog-to-digital converter |
| JP2014107651A (en) * | 2012-11-27 | 2014-06-09 | Asahi Kasei Electronics Co Ltd | Ring amplifier |
| CN105958948A (en) * | 2016-04-26 | 2016-09-21 | 西安电子科技大学昆山创新研究院 | Low-power-consumption wide-range operational transconductance amplifier |
| WO2017019973A1 (en) * | 2015-07-30 | 2017-02-02 | Circuit Seed, Llc | Multi-stage and feed forward compensated complementary current field effect transistor amplifiers |
-
2017
- 2017-11-13 CN CN201711114028.8A patent/CN107834981A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4253033A (en) * | 1979-04-27 | 1981-02-24 | National Semiconductor Corporation | Wide bandwidth CMOS class A amplifier |
| CN2777853Y (en) * | 2004-11-01 | 2006-05-03 | 中国科学院半导体研究所 | Stable micro-power consumption CMOS voltage integrator |
| CN101640539A (en) * | 2009-06-19 | 2010-02-03 | 浙江大学 | Sigma-delta analog-to-digital converter |
| JP2014107651A (en) * | 2012-11-27 | 2014-06-09 | Asahi Kasei Electronics Co Ltd | Ring amplifier |
| WO2017019973A1 (en) * | 2015-07-30 | 2017-02-02 | Circuit Seed, Llc | Multi-stage and feed forward compensated complementary current field effect transistor amplifiers |
| CN105958948A (en) * | 2016-04-26 | 2016-09-21 | 西安电子科技大学昆山创新研究院 | Low-power-consumption wide-range operational transconductance amplifier |
Non-Patent Citations (3)
| Title |
|---|
| JASON MUHLESTEIN1: "A Multi-path Ring Amplifier with Dynamic Biasing", 《2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)》 * |
| SONG CHEN等: "A time-resolved CMOS image sensor with high conversion-gain pixels and pipelined ADCs", 《2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)》 * |
| 郭艳颖等: "《航空电子技术基础》", 30 September 2016, 西北工业大学出版社 * |
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Application publication date: 20180323 |