CN107818959A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN107818959A CN107818959A CN201711180440.XA CN201711180440A CN107818959A CN 107818959 A CN107818959 A CN 107818959A CN 201711180440 A CN201711180440 A CN 201711180440A CN 107818959 A CN107818959 A CN 107818959A
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- substrate
- conductive pad
- semiconductor package
- width
- covering material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 242
- 239000000463 material Substances 0.000 claims abstract description 104
- 239000013078 crystal Substances 0.000 claims abstract description 30
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 239000002245 particle Substances 0.000 claims description 28
- 239000000853 adhesive Substances 0.000 claims description 22
- 230000001070 adhesive effect Effects 0.000 claims description 22
- 239000002131 composite material Substances 0.000 claims description 20
- 239000003292 glue Substances 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 5
- 238000009826 distribution Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 238000002844 melting Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000005253 cladding Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention is on a kind of semiconductor package.The semiconductor package includes first substrate, second substrate, crystal grain, several interior connecting elements and covering material.First substrate has upper surface.Second substrate has lower surface, and the upper surface of wherein first substrate is in face of the lower surface of second substrate.Crystal grain is electrically connected to the upper surface of first substrate.Several interior connecting elements are electrically connected with first substrate and second substrate, interior connecting element includes top and bottom, wherein upper bond bottom is to form junction surface, bottom has shoulder, shoulder surrounds junction surface, bottom has more top surface and peripheral surface, and top surface is plane, and shoulder is the junction positioned at top surface and peripheral surface.Covering material coats crystal grain and interior connecting element between the upper surface of first substrate and the lower surface of second substrate.Thereby, in reflow, warpage will not occur for second substrate, and solve the problems, such as first and second strippable substrate.
Description
The application is to apply on December 4th, 2013, Application No. 201310645713.9, entitled " semiconductor
The divisional application of the Chinese invention patent application of encapsulating structure and semiconductor technology "
Technical field
The present invention is on a kind of semiconductor package.In detail, the present invention is to stack semiconductor packages on one kind
Structure.
Background technology
It is known stack semiconductor package manufacture method it is as follows, first, by a crystal grain and several soldered ball (Solder
Ball) it is bonded on the upper surface of an infrabasal plate.Then, using seal mold technique (Molding Process) formed a seal glue
Expect on the upper surface of the infrabasal plate, to coat the crystal grain and these soldered balls.Then, after solidifying the adhesive material, high temperature is utilized
Laser forms several openings to appear the top of these soldered balls in the adhesive material upper surface.Then, a upper substrate is put in this
On adhesive material so that positioned at these soldered balls of the solder contact of the upper substrate lower surface.Then, first is carried out with a heating oven
Secondary heating so that the solder and these soldered balls melting and formed in connecting element.Then, number is formed in the lower surface of the infrabasal plate
After individual soldered ball, reflow process is carried out.Finally cutting step is carried out again.
In the known manufacturing methods, during the heating oven is moved to, upper substrate lower surface and the seal glue
Material only contact and without engaging force, and the solder also only contacted with these soldered balls and without engaging force, therefore, upper substrate and the seal glue
Material can shift (Shift).In addition, after first time heats, the only solder of the upper substrate and the soldered ball of infrabasal plate is mutual
Engagement, but upper substrate lower surface still only contacted with the adhesive material and without engaging force.Therefore, after reflow, upper substrate is easy
Generation warpage (Warpage), or even the upper substrate and the infrabasal plate can peel off (Peeling off), influence product yield.
In order to improve above mentioned problem, a kind of new solution is suggested.The solution is connect first with these soldered balls
Infrabasal plate is closed, carries out envelope mold technique again afterwards, to form an adhesive material between the upper and lower base plate.However, such a mode
Envelope mold technique in, the adhesive material is that therefore, these soldered balls can influence the seal glue between injecting the upper and lower base plate by side
The flowing of material so that the skewness of the particle filled composite in the adhesive material, and because the mode of the technique is in order to allow this
Adhesive material can be successfully between the crystal grain and the upper substrate by the way that therefore these solder balls maintain certain height so that
The size of these soldered balls is larger so that the spacing of these soldered balls can not effectively reduce.
The content of the invention
The one side of the disclosure is on a kind of semiconductor package.In one embodiment, the semiconductor package
Including a first substrate, a second substrate, a crystal grain, several interior connecting elements and a covering material.The first substrate has one
Upper surface.The second substrate has a lower surface, and the upper surface of the wherein first substrate is in face of the lower surface of the second substrate.
The crystal grain is electrically connected to the upper surface of the first substrate.Several interior connecting elements be electrically connected with the first substrate and this second
Substrate, the interior connecting element include a top and a bottom, and wherein upper bond bottom is to form the junction surface, the bottom
With a shoulder, a shoulder surrounds the junction surface, and the bottom has more a top surface and a peripheral surface, and the top surface is plane, should
Shoulder is the junction positioned at the top surface and the peripheral surface.The covering material be located at the first substrate upper surface and this second
Between the lower surface of substrate, and coat the crystal grain and the interior connecting element.
Another aspect of the present disclosure is on a kind of semiconductor technology.In one embodiment, the semiconductor technology include with
Lower step：(a) several first conductive parts are formed on the first substrate of a first substrate on conductive pad, wherein the first substrate is more
With a upper surface, conductive pad is the upper surface for being revealed in the first substrate on these first substrates；(b) (Leveling) is flattened
These first conductive parts so that these each first conductive parts have a top surface, and these top surfaces are copline；(c) it is brilliant by one
Grain is electrically connected to a upper surface of a first substrate, and the wherein first substrate shows with more conductive pad on several first substrates
It is exposed to the upper surface of the first substrate；(d) apply a covering material in the upper surface of the first substrate with coat the crystal grain and this
A little first conductive parts, the wherein covering material are B-stage (B-stage) glue material；(e) formed it is several be opened on the covering material with
Appear these top surfaces of these the first conductive parts；(f) second substrate is pressed in the covering material so that the second substrate
A lower surface is attached in the covering material, and wherein the second substrate has more conductive pad and several second under several second substrates
Conductive part, conductive pad is the lower surface for being revealed in the second substrate under the second substrate, and these second conductive parts are to be located at these
Under second substrate on conductive pad, and these second conductive parts contact these top surfaces of these the first conductive parts；And (g) carries out one and added
Hot step so that these second conductive parts and these first conductive parts melt and form several interior connecting elements, and the cladding material
Material is solidified into C-stage.
In the present embodiment, because the lower surface of the second substrate attaches to the covering material, therefore, in whole encapsulation knot
In the moving process of structure, the second substrate will not shift with the covering material.In addition, in reflow, the second substrate is not
Warpage can occur, and solve the problems, such as first and second strippable substrate, and product yield can be improved.
Brief description of the drawings
Fig. 1 shows the schematic cross-sectional view of an embodiment of semiconductor package of the present invention.
Fig. 2 shows Fig. 1 region A enlarged diagram.
Fig. 2A shows the enlarged diagram of another embodiment of these interior connecting elements.
Fig. 3 to Figure 11 shows the schematic diagram of an embodiment of semiconductor technology of the present invention.
Figure 12 shows the schematic cross-sectional view of another embodiment of semiconductor package of the present invention.
Figure 13 shows Figure 12 region B enlarged diagram.
Figure 14 shows the schematic cross-sectional view of another embodiment of semiconductor package of the present invention.
Embodiment
With reference to figure 1, the schematic cross-sectional view of an embodiment of semiconductor package of the present invention is shown.The semiconductor packages knot
Structure 1 includes a first substrate 10, a second substrate 12, a crystal grain 14, several interior connecting elements 16, a covering material 18 and several
Lower soldered ball 20.
The first substrate 10 has a upper surface 101, a lower surface 102, conductive pad 103 and several on several first substrates
Conductive pad 104 under first substrate.In the present embodiment, the first substrate 10 is a package substrate, conductive under these first substrates
Pad 104 is revealed in the lower surface 102 of the first substrate 10, and conductive pad 103 is revealed in the first substrate on these first substrates
10 upper surface 101.Conductive pad 104 is electrically connected to conductive pad 103 on these first substrates under these first substrates.
The second substrate 12 has a upper surface 121, a lower surface 122, conductive pad 123 and several on several second substrates
Conductive pad 124 under second substrate.The upper surface 101 of the first substrate 10 is in face of the lower surface 122 of the second substrate 12.At this
In embodiment, the second substrate 12 is a package substrate or an intermediate plate (Interposer), conductive pad on these second substrates
123 are revealed in the upper surface 121 of the second substrate 12, and conductive pad 124 is revealed in the second substrate 12 under these second substrates
Lower surface 122.Conductive pad 123 is electrically connected to conductive pad 124 under these second substrates on these second substrates.
The crystal grain 14 is electrically connected to the upper surface 101 of the first substrate 10.In the present embodiment, the crystal grain 14 be with
Chip bonding mode is attached to the upper surface 101 of the first substrate 10, that is, the crystal grain 14 is electrically connected with using its active surface
To the upper surface 101 of the first substrate 10, and its back side is upward.These interior connecting elements 16 connect to be led on these first substrates
Conductive pad 124 under electrical pad 103 and these second substrates.In the present embodiment, these each interior connecting elements 16 are by one first
Conductive part (such as：Soldered ball (Solder Ball)) and one second conductive part (such as：Pre-welding material (Pre-solder)) mutually melt afterwards
There is a shoulder 1621 into a top 161 and a bottom 162, the wherein bottom 162 respectively.These interior connecting elements 16 are mainly
Conductive pad 124 under conductive pad 103 and these second substrates is for electrically connecting on these first substrates.
On the first substrate of the present invention under conductive pad 103 and the first substrate on conductive pad 104 or the second substrate
Conductive pad 124 can be used as electric connection by the use of conductive trace (Trace) (not shown) under conductive pad 123 and the second substrate
Technical approach, conductive pad 124 optionally can be with the conductive trace copline (coplanar) or protrusion under above-mentioned second substrate
(projecting) on the conductive trace.
The covering material 18 is located between the upper surface 101 of the first substrate 10 and the lower surface 122 of the second substrate 12,
And coat the crystal grain 14 and these interior connecting elements 16.The covering material 18 is to stick the upper surface of the first substrate 10 respectively
101 and the lower surface 122 of the second substrate 12, and sticking between the upper surface 101 of the covering material 18 and the first substrate 10
Power is approximately identical to the adhesive force between the lower surface 122 of the covering material 18 and the second substrate 12.In the present embodiment, the bag
Cover material 18 for non-conductive film (Non Conductive Film, NCF), non-conductive adhesive (Non Conductive Paste,
) or ABF (Ajinomoto Build-up Film) NCP.When the covering material 18 is in the state of B-stage (B-stage) glue material
When, that is, bind the upper surface 101 of the first substrate 10 and the lower surface 122 of the second substrate 12.Due to the second substrate 12
Lower surface 122 attaches to the covering material 18, and therefore, in the moving process of whole encapsulating structure, the second substrate 12 is with being somebody's turn to do
Covering material 18 will not shift.In addition, after the heating, the covering material 18 solidifies and the shape in C-stage (C-stage)
State, the adhesive force between its upper surface 101 with the first substrate 10 are approximately identical to its lower surface 122 with the second substrate 12
Between adhesive force, plus the conjugation of these interior connecting elements 16, therefore, in reflow, the second substrate 12 will not occur
Warpage (Warpage), and product yield can be improved.
In the present embodiment, the covering material 18 has several holding tanks 181 to accommodate these interior connecting elements 16, these
The shape of the side wall of holding tank 181 is consistent completely with these interior connecting elements 16, and the outer surface of these interior connecting elements 16 is complete
The side wall of these holding tanks 181 of Full connected, that is, the shape of these holding tanks 181 is defined by these interior connecting elements 16.
In other words, any space is not had to exist between these interior connecting elements 16 and the side wall of these holding tanks 181.Therefore, connect in these
It is to combine closely that element 16, which is connect, with the covering material 18.
In addition, the covering material 18 has more several particle filled composites (Fillers) 182, these particle filled composites 182 have size
Different particle diameters, and be uniformly distributed in the covering material 18, without in these interior connecting elements 16.Meanwhile these
The density of particle filled composite 182 is also uniform in the covering material 18.It should be noted that in process, equally distributed filling
Particle 182 can be beneficial to the hole uniformity that laser drill is carried out in the covering material 18, and then improve these interior connecting elements
16 uniformity, improve the reliability (Reliability) of the semiconductor package 1.
Furthermore these particle filled composites 182 are not necessary to the flow process by die channel (Molding Channel), therefore
The integral thickness of the covering material 18 can be reduced, the particularly covering material 18 is between the second substrate 12 and the crystal grain 14
Thickness.In one embodiment, thickness of the covering material 18 between the second substrate 12 and the crystal grain 14 can be not more than these
Maximum particle diameter size in particle filled composite 182；In another embodiment, the covering material 18 is in the second substrate 12 and the crystal grain 14
Between thickness be less than 20 microns (μm).
For example, region A in figure1And region A2The covering material 18 in left side and the covering material 18 on right side are represented respectively,
Wherein region A1Extend a pre-determined distance to the right for the leftmost side side of the covering material 18, the pre-determined distance is the covering material 18
The 10% of Breadth Maximum, and region A2Extend the pre-determined distance to the left for the rightmost side side of the covering material 18.Positioned at region A1And
Region A2Particle filled composite 182 particle diameter distribution and density it is identical.It is difference acquisition area A in actual experiment1And region A2
In the amplification of any zonule, respectively take wherein 100 particle filled composites to compare, it is possible to find region A1In 100 particle filled composites and
Region A2In 100 particle filled composites, the particle diameter distribution and density of the two are substantially identical.
These lower soldered balls 20 are located under these first substrates on conductive pad 104, are electrically connected to an outer member.
With reference to figure 2, Fig. 1 region A enlarged diagram is shown.In the present embodiment, the interior connecting element 16 includes one
The bottom 162 of top 161 and one.The top 161 is electrically connected with conductive pad 124 under these second substrates, and the bottom 162 is electrically connected with
Conductive pad 103 on these first substrates, the wherein volume of the bottom 162 are more than the volume on the top 161.The top 161 engages
The bottom 162 is to form a junction surface 163.The bottom 162 has a shoulder 1621, a top surface 1622 and a peripheral surface
1623.The shoulder 1621 is the junction positioned at the top surface 1622 and the peripheral surface 1623, and the shoulder 1621 connects around this
Conjunction portion 163.In the present embodiment, the top surface 1622 is plane, and the peripheral surface 1623 is cambered surface, and wherein the top surface 1622 is flat
Conductive pad 103 on the row first substrate.The junction surface 163 be with the copline of top surface 1622, and the top surface 1622 connects around this
Conjunction portion 163.
The bottom 162 has one first width W with the region that conductive pad 103 contacts on the first substrate1, and the top
161 have one second width W with the region that conductive pad 124 contacts under the second substrate2.The bottom has a Breadth Maximum in itself
Wm, the top surface 1622 has one the 3rd width W3, the junction surface 163 has one the 4th width W4, wherein Breadth Maximum WmIt is more than
First width W1, second width W2And the 3rd width W3, and the 3rd width W3More than the 4th width W4。
First width W1Approximately equal to the 4th width W4.In the present embodiment, due to these each interior connecting elements 16
Be by the first conductive part (such as：Soldered ball (Solder Ball)) and one second conductive part (such as：Pre-welding material (Pre-solder))
Respectively into the top 161 and the bottom 162, therefore, the Breadth Maximum W of these interior connecting elements 16 after mutually meltingmCan effectively it contract
It is small so that the spacing of these interior connecting elements 16 can effectively reduce, and be applied to thin space (Fine Pitch) circuit.
The distance at the back side of the crystal grain 14 and the upper surface 101 of the first substrate 10 is the first height h1, the shoulder 1621
(or the top surface 1622) and the distance of the upper surface 101 of the first substrate 10 are the second height h2, the shoulder 1621 (or the top surface
1622) distance with the lower surface 122 of the second substrate 12 is third height h3, wherein h1＞ h2, and h2+h3＞ h1。
With reference to figure 2A, the enlarged diagram of another embodiment of these interior connecting elements is shown.In the present embodiment, due to
These each interior connecting elements 16 be by after flattening the first conductive part (such as：Soldered ball (Solder Ball)) and one second lead
Electric portion (such as：Pre-welding material (Pre-solder)) mutually melt afterwards respectively into the top 161 and the bottom 162.Because this first is led
Electric portion 15 be advance leveling to form flat top surface 151 (Fig. 4), and increase accessible area, therefore, even if this second is led
There is a skew S, second conductive part still can contact the top surface 151, and can ensure that this between electric portion and first conductive part
Top 161 and the connection of bottom 162 to each other, to improve yield.
With reference to figure 3 to Figure 11, the schematic diagram of an embodiment of semiconductor technology of the present invention is shown.With reference to figure 3, there is provided this
One substrate 10.The first substrate 10 is with conductive pad 103 on a upper surface 101, a lower surface 102, several first substrates and number
Conductive pad 104 under individual first substrate.In the present embodiment, the first substrate 10 is a package substrate, is led under these first substrates
Electrical pad 104 is revealed in the lower surface 102 of the first substrate 10, and conductive pad 103 is revealed in first base on these first substrates
The upper surface 101 of plate 10.Conductive pad 104 is electrically connected to conductive pad 103 on these first substrates under these first substrates.
Then, several first conductive parts 15 are formed in conductive pad 103 on these first substrates.In the present embodiment, these
First conductive part 15 is several soldered balls, and it has Radius R to be spherical.
With reference to figure 4, (Leveling) these first conductive parts 15 are flattened so that these each first conductive parts 15 have one
Top surface 151, and these top surfaces 151 are copline.In the present embodiment, it is after being first heated to about 170 DEG C, recycles a mould pressure
Put down these first conductive parts 15.First conductive part 15 after leveling has one second height h2, wherein R ＜ h2＜ 2R, and the top
Face has a Breadth Maximum W, wherein W<2.2R.Breadth Maximum W is approximately equal to the 3rd width in final encapsulating structure
W3(Fig. 2).
Second height h of these the first conductive parts 15 after leveling2It is almost identical, its tolerance can be reduced, reduces follow-up work
The degree of difficulty that the second substrate 12 engages in skill.Furthermore the similarity of the outward appearance of these the first conductive parts 15 after leveling is suitable
Height, can be as the anchor point of other techniques, thus can provide the selection in more technological designs.In addition, after leveling these the
One conductive part 15 can also reduce the thickness of overall package structure.
With reference to figure 5, the crystal grain 14 is electrically connected to the upper surface 101 of the first substrate 10.In the present embodiment, the crystalline substance
Grain 14 is the upper surface 101 that the first substrate 10 is attached in a manner of chip bonding.That is, the crystal grain 14 is to utilize its active surface
The upper surface 101 of the first substrate 10 is electrically connected to, and its back side is upward.The back side of the crystal grain 14 and the first substrate 10
The distance of upper surface 101 be the first height h1, the distance of the upper surface 101 of the top surface 151 and the first substrate 10 is second
Height h2, wherein h1＞ h2。
With reference to figure 6, there is provided the covering material 18.In the present embodiment, the covering material 18 is non-conductive film (Non
Conductive Film, NCF), non-conductive adhesive (Non Conductive Paste, NCP) or ABF (Ajinomoto Build-
Up Film), and it has several particle filled composites (Fillers) 182.These particle filled composites 182 have particle diameter of different sizes, and
It is uniformly distributed in the covering material 18.Now, the covering material 18 is in the state of B-stage (B-stage) glue material.
With reference to figure 7, apply the covering material 18 in the upper surface 101 of the first substrate 10 with coat the crystal grain 14 and these
First conductive part 15.Now state of the covering material 18 still in B-stage.In the present embodiment, the covering material 18 is profit
It is formed at the upper surface 101 of the first substrate 10 from top to bottom or from bottom to top with the mode such as pressing or printing, therefore, this
A little first conductive parts 15 do not interfere with the flowing of the particle filled composite 182 in the covering material 18, and these particle filled composites 182 are not necessary to
By die channel (Molding Channel) flow process so that these particle filled composites 182 are still uniformly distributed in the cladding
In material 18.
With reference to figure 8, formed several openings 183 in the covering material 18 to appear the top surface of these the first conductive parts 15
151.In the present embodiment, it is to form these openings 183 using low temperature laser.Now, the covering material 18 is still in B-stage
State.
With reference to figure 9, there is provided the second substrate 12.The second substrate 12 has a upper surface 121, a lower surface 122, several
Conductive pad 124 and several second conductive parts 125 under conductive pad 123, several second substrates on second substrate.The second substrate 12
Lower surface 122 is in face of the upper surface 101 of the first substrate 10.In the present embodiment, the second substrate 12 is a package substrate
Or an intermediate plate (Interposer), conductive pad 123 is revealed in the upper surface 121 of the second substrate 12 on these second substrates,
And conductive pad 124 is revealed in the lower surface 122 of the second substrate 12 under these second substrates.Conductive pad on these second substrates
123 are electrically connected to conductive pad 124 under these second substrates.These second conductive parts 125 are located under these second substrates
On conductive pad 124.In the present embodiment, these second conductive parts 125 are several pre-welding materials, and its outer surface is a cambered surface.It is each
The volume of second conductive part 125 is less than the volume of every one first conductive part 15.
Then, apply pressure to press the second substrate 12 in the covering material 18.Due to the covering material 18
Still in the state of B-stage so that the lower surface 122 of the second substrate 12 can be attached in the covering material 18, and the bag
Cover the adhesive force between the upper surface 101 of material 18 and the first substrate 10 and be approximately identical to the covering material 18 and the second substrate
Adhesive force between 12 lower surface 122.According in an embodiment, applying the lower pressure while being heated to about 90 DEG C, now, the bag
It is flowable state to cover material 18, and can fill up any space.Further, since the covering material 18 does not need the flowing space, because
This, via the amount and the lower pressure for controlling the covering material 18, can be greatly reduced the thickness of overall package structure.
With reference to figure 10, first time heating is carried out with a heating oven so that first conductive part 15 and second conductive part
125 mutually melt and engage after respectively into the top 161 and the bottom 162 of the interior connecting element 16.Operating temperature now is about
For 245 DEG C.It should be noted that during the heating oven is moved to, the lower surface 122 of the second substrate 12 has attached to
In the covering material 18, therefore, the second substrate 12 will not shift with the adhesive material 18.In the present embodiment, this
One conductive part 15 has flat top surface 151, and the volume of second conductive part 125 is less than the body of first conductive part 15
Product.Therefore, after mutually melting, the bottom 162 can have a shoulder 1621.Now, the covering material 18 can fill up the shoulder 1621
In the space of top.That is, the shape of these holding tanks 181 in the covering material 18 is determined by these interior connecting elements 16
Justice.
Now, the shoulder 1621 and the distance of the lower surface 122 of the second substrate 12 are third height h3, wherein h2+h3＞
h1。
After a period of time is heated, the covering material 18 is solidified into C-stage.There are these appearances in the covering material 18 of solidification
Groove 181 is received to accommodate these interior connecting elements 16, the shape of the side wall of these holding tanks 181 and these interior connecting elements 16 are complete
It is consistent, and the outer surface of these interior connecting elements 16 completely attaches to the side wall of these holding tanks 181.In other words, connected in these
There is no any space to exist between the side wall of element 16 and these holding tanks 181, and these interior connecting elements 16 and the covering material
18 be to combine closely.
With reference to figure 11, the several lower soldered balls 20 of formation are under these first substrates on conductive pad 104.Then, reflow is carried out.Will
It is noted that the now second substrate 12 on close attachment to adhesive material 18 and the first substrate 10, therefore after reflow,
Warpage will not occur for the second substrate 12, can thereby improve product yield.Then, cut, it is several as shown in Figure 1 to be formed
Semiconductor package.In cutting process, the second substrate 12 equally close attachment to the adhesive material 18 and this
On one substrate 10, thus cut when caused stress cause the second substrate 12 peel off the problem of will not also occur.
With reference to figure 12, the schematic cross-sectional view of another embodiment of semiconductor package of the present invention is shown.With reference to figure 13, show
The region B of diagram 12 enlarged diagram.Semiconductor package shown in the semiconductor package 1a and Fig. 1 and Fig. 2 of the present embodiment
Assembling structure 1 is roughly the same, and it does not exist together as described below.In the semiconductor package 1a of the present embodiment, the first substrate
10 part of upper surface 101 covers one first upper dielectric layer 105, and the part of lower surface 102 covering 1 of the first substrate 10 the
Dielectric layer 106 once.Conductive pad 103 is revealed in first upper dielectric layer 105 on these first substrates, and under these first substrates
Conductive pad 104 is revealed in first time dielectric layer 106.In addition, it is situated between in the part of upper surface 121 covering one second of second substrate 12
Electric layer 126, and the part of lower surface 122 of second substrate 12 covers second time dielectric layer 127.Conductive pad on these second substrates
123 are revealed in second upper dielectric layer 126, and conductive pad 124 is revealed in second time dielectric layer 127 under these second substrates.
In the present embodiment, first upper dielectric layer 105 and the adhesive force of the covering material 18 are approximately identical to second time dielectric layer
Adhesive force between 127 and the covering material 18.
With reference to figure 14, the schematic cross-sectional view of another embodiment of semiconductor package of the present invention is shown.The present embodiment
Semiconductor package 1b is roughly the same with the semiconductor package 1 shown in Fig. 1 and Fig. 2, and it does not exist together as described below.At this
In the semiconductor package 1b of embodiment, being somebody's turn to do between the lower surface 122 of second substrate 12 and the upper surface 141 of crystal grain 14
The thickness of covering material 18 is defined as T, and the maximum particle diameter size that thickness T is less than or equal in these particle filled composites 182.Cause
This, thickness T can also be equal to 0 so that the lower surface 122 of second substrate 12 contacts the upper surface 141 of crystal grain 14.
The only principle and its effect of above-described embodiment only to illustrate the invention, and it is not used to the limitation present invention.Therefore, practise in
The personage of this technology, which modifies and changed to above-described embodiment, does not take off spirit of the invention still.The interest field of the present invention should be as
Listed by claims.
Claims (20)
- A kind of 1. semiconductor package, it is characterised in that including：One first substrate, there is a upper surface；One second substrate, there is a lower surface, the upper surface of the wherein first substrate is in face of the lower surface of the second substrate；One crystal grain, it is electrically connected to the upper surface of the first substrate；Several interior connecting elements, the first substrate and the second substrate are electrically connected with, the interior connecting element includes a top And a bottom, to form a junction surface, the bottom has a shoulder for wherein upper bond bottom, and the shoulder surrounds the engagement Portion, the bottom have more a top surface and a peripheral surface, and the top surface is plane, and the shoulder is to be located at the top surface and the peripheral surface Junction；AndOne covering material, between the upper surface of the first substrate and the lower surface of the second substrate, and coat the crystal grain and The interior connecting element.
- 2. semiconductor package as claimed in claim 1, it is characterised in that the first substrate has more several first substrates Upper conductive pad, the second substrate have more conductive pad under several second substrates；The top is electrically connected with the second substrate and led Electrical pad, the bottom are electrically connected with conductive pad on the first substrate.
- 3. semiconductor package as claimed in claim 1, it is characterised in that the first substrate has more a lower surface and number Conductive pad under individual first substrate, conductive pad is revealed in the first substrate lower surface, and the first substrate under the first substrate Upper conductive pad is revealed in the first substrate upper surface；The second substrate is with more conductive on a upper surface and several second substrates Pad, conductive pad is revealed in the second substrate upper surface on the second substrate, and conductive pad is revealed in this under the second substrate Second substrate lower surface.
- 4. semiconductor package as claimed in claim 1, it is characterised in that the volume of the bottom is more than the body on the top Product.
- 5. semiconductor package as claimed in claim 1, it is characterised in that the peripheral surface is cambered surface, and the top surface is Conductive pad on the parallel first substrate.
- 6. semiconductor package as claimed in claim 1 a, it is characterised in that back side of the crystal grain and the first substrate The distance of upper surface is the first height h1, and the distance of the shoulder and the upper surface of the first substrate is the second height h2, the shoulder Distance with the lower surface of the second substrate is third height h3, wherein h1 ＞ h2, and h2+h3 ＞ h1.
- 7. semiconductor package as claimed in claim 1, it is characterised in that the bottom connects with conductive pad on the first substrate Tactile region has one first width, and the top has one second width with the region that conductive pad contacts under the second substrate, should Bottom has a Breadth Maximum in itself, and the bottom has more a top surface, and the top surface has one the 3rd width, and the junction surface has one 4th width, the wherein Breadth Maximum are more than first width, second width and the 3rd width, and the 3rd width is more than 4th width.
- 8. semiconductor package as claimed in claim 1, it is characterised in that there are the covering material several holding tanks to hold Receive the interior connecting element, the shape of the side wall of the holding tank is consistent completely with the interior connecting element, and the interior connection The outer surface of element contacts the side wall of the holding tank.
- 9. semiconductor package as claimed in claim 1, it is characterised in that there are the covering material several holding tanks to hold Receive the interior connecting element, and the shape of the holding tank is defined by the interior connecting element.
- 10. semiconductor package as claimed in claim 1, it is characterised in that the covering material is non-conductive film, non-conductive Glue or ABF.
- 11. semiconductor package as claimed in claim 1, it is characterised in that the covering material has several particle filled composites, And the particle filled composite is uniformly distributed in the covering material.
- 12. semiconductor package as claimed in claim 1, it is characterised in that the covering material has several particle filled composites, And the covering material includes an a region A1 and region A2, wherein region A1 is that the leftmost side side of the covering material extends to the right One pre-determined distance, the pre-determined distance is the 10% of the covering material Breadth Maximum, and region A2 is the most right of the covering material Side extends the pre-determined distance to the left, wherein particle diameter distribution and density phase positioned at region A1 and region A2 particle filled composite Together.
- 13. semiconductor package as claimed in claim 1, it is characterised in that first substrate upper surface portion covering one First dielectric layer, the bottom surface section of second substrate cover one second dielectric layer, wherein first dielectric layer and the covering material Adhesive force be approximately identical to adhesive force between second dielectric layer and the covering material.
- A kind of 14. semiconductor package, it is characterised in that including：One first substrate, there is a upper surface；One second substrate, there is conductive pad under a lower surface and several second substrates, the upper surface of the wherein first substrate is face To the lower surface of the second substrate；One crystal grain, it is electrically connected to the upper surface of the first substrate；Several interior connecting elements, the first substrate and the second substrate are electrically connected with, the interior connecting element includes a top And a bottom, to form a junction surface, the top contacts with conductive pad under the second substrate for wherein upper bond bottom Region has one second width, and the bottom has a top surface, and the top surface is plane, and the top surface has one the 3rd width, the engagement Portion has one the 4th width, and wherein second width is more than the 4th width, and the 3rd width is more than second width；AndOne covering material, between the upper surface of the first substrate and the lower surface of the second substrate, and coat the crystal grain and The interior connecting element.
- 15. semiconductor package as claimed in claim 14, it is characterised in that the first substrate has several first substrates Upper conductive pad, the bottom have one first width with the region that conductive pad contacts on the first substrate, and the bottom has one in itself Breadth Maximum, the wherein Breadth Maximum are more than first width, second width and the 3rd width, and the 3rd width is more than 4th width.
- 16. semiconductor package as claimed in claim 14, it is characterised in that the upper surface of the first substrate has several Conductive pad on first substrate, and conductive pad is revealed in the first substrate upper surface on the first substrate, the first substrate has more There is a conductive pad under a lower surface and several first substrates, conductive pad is revealed in the first substrate lower surface under the first substrate, The lower surface of the second substrate has a conductive pad under the second substrate, and under the second substrate conductive pad be revealed in this second Base lower surface；The second substrate is conductive on the second substrate with more conductive pad on a upper surface and several second substrates Pad is revealed in the second substrate upper surface；The top is electrically connected with conductive pad under the second substrate, and the bottom is electrically connected with institute State conductive pad on first substrate.
- 17. semiconductor package as claimed in claim 14, the top of each interior connecting element is a pre-welding material；Often The bottom of the one interior connecting element is a soldered ball.
- 18. semiconductor package as claimed in claim 14, it is characterised in that the upper volume is less than the lower ball Volume.
- 19. described semiconductor package as claimed in claim 14, it is characterised in that the covering material has several receivings To accommodate the interior connecting element, the shape of the side wall of the holding tank is consistent groove completely with the interior connecting element, and described The outer surface of interior connecting element contacts the side wall of the holding tank.
- 20. semiconductor package as claimed in claim 14, it is characterised in that the covering material have several holding tanks with The interior connecting element is accommodated, and the shape of the holding tank is defined by the interior connecting element.
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| CN201711180440.XA CN107818959B (en) | 2013-12-04 | 2013-12-04 | Semiconductor packaging structure |
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| CN201711180440.XA CN107818959B (en) | 2013-12-04 | 2013-12-04 | Semiconductor packaging structure |
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| US20080017968A1 (en) * | 2006-07-18 | 2008-01-24 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
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| CN103117261A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Package structures and methods for forming the same |
| CN103367298A (en) * | 2012-04-09 | 2013-10-23 | 颀邦科技股份有限公司 | Semiconductor packaging structure and packaging method thereof |
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| JP2004327855A (en) * | 2003-04-25 | 2004-11-18 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| US7345361B2 (en) * | 2003-12-04 | 2008-03-18 | Intel Corporation | Stackable integrated circuit packaging |
| WO2007083351A1 (en) * | 2006-01-17 | 2007-07-26 | Spansion Llc | Semiconductor device and method for manufacturing same |
| US8198131B2 (en) * | 2009-11-18 | 2012-06-12 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor device packages |
| US9219030B2 (en) * | 2012-04-16 | 2015-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package on package structures and methods for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080017968A1 (en) * | 2006-07-18 | 2008-01-24 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
| CN102097341A (en) * | 2009-12-10 | 2011-06-15 | 日东电工株式会社 | Manufacturing method for semiconductor device |
| CN103117261A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Package structures and methods for forming the same |
| CN103367298A (en) * | 2012-04-09 | 2013-10-23 | 颀邦科技股份有限公司 | Semiconductor packaging structure and packaging method thereof |
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| CN107818959B (en) | 2021-09-03 |
| CN104701270B (en) | 2017-12-19 |
| CN104701270A (en) | 2015-06-10 |
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