CN107808024A - A kind of method that coiling is interconnected between the Insertion Loss evaluation board by signal - Google Patents
A kind of method that coiling is interconnected between the Insertion Loss evaluation board by signal Download PDFInfo
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- CN107808024A CN107808024A CN201710773957.3A CN201710773957A CN107808024A CN 107808024 A CN107808024 A CN 107808024A CN 201710773957 A CN201710773957 A CN 201710773957A CN 107808024 A CN107808024 A CN 107808024A
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- insertion loss
- redriver
- signal
- coiling
- cabling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- Computer Hardware Design (AREA)
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- General Engineering & Computer Science (AREA)
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- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The embodiment of the invention discloses a kind of method that coiling is interconnected between Insertion Loss evaluation board by signal, an Insertion Loss statistical form is established.According to the cabling situation of two boards, the key element of Insertion Loss is influenceed including line width line-spacing, cabling aspect, sheet material model etc., go out the Insertion Loss of unit length using IMLC simulation calculations, then two board track lengths are come out, both draw total Insertion Loss value of each signal position after being multiplied.Take maximum difference to draw maximum Insertion Loss difference value between each signal position by making the difference, finally by the tolerance amount of contrast redriver chip same parameters judge that this design can be covered with a parameter.The parameter setting that the present invention, which has, can be solved the problems, such as to need plus the interconnection of more boards of redriver chips is brought, saves plenty of time human cost for system development, improves design efficiency, succinct effective advantage.
Description
Technical field
The present invention relates to board design field.
Background technology
With the continuous development of big data, cloud computing and mass memory, the storage demand to mass data is increasing, this
Require that the hard-disk capacity that server unit is arranged in pairs or groups is increasing, be limited to the limitation of CPU high speed bus quantity, single cpu can be hung
The hard disk quantity of load is certain.
It is therefore desirable to have a chip extends high speed BUS quantity, in the market using it is maximum be PCIe
Switch chips, the bus number of 5 times of extension after server master board can be connect, and can be cascaded on the premise of signal meets, this
Sample just completes unit dilatation.
Above-mentioned apply is usually associated with long range board cabling in Practical Project and connected with cable, and this gives signal integrity
Bring very big challenge.If having disk phenomenon after delivering, the Consumer's Experience of bad luck will be caused.Such as：Backstage takes during shopping online
Business device will handle mass data, and one of disk, which goes offline, may all bring on-line shop to paralyse.
It is feasible on dilatation solution principle, implements and have serious problems of Signal Integrity, present industry is main
Way is that a suitable position addition signal repeater chip is looked between switch chips and hard disk（redriver）, this chip
Main function be similar to refuel(l)ing station, i.e., to the effective amplification of signal on the path of signal attenuation, when it is reached hard disk
Data are still effective.
Prior art seems that perfection solves long link and transmits this problem, but new problem occurs.Such as：Each
Redriver chips enter 4 and go out 4, it is necessary to which the program for being set in chip internal encourages to adjust, and the signal attenuation of every a pair of cablings is not
Unanimously need the parameter that adjusts also different, this brings very big workload, and easily error to machine debugging, this unstable
Moment is likely to break out, and Internet subscribers unprecedentedly improve to the attention degree of data, is also one for server provider
Very stubborn problem.
In addition, to select suitable board to place redriver chips during the interconnection of more boards, that is to say, that from transmitting terminal to
Redriver chips are straddle connections, and this brings many uncertainties to parameter setting again.
The content of the invention
The present invention is the technical problem solved.Therefore, the present invention provide it is a kind of by interconnected between signal Insertion Loss evaluation board around
The method of line, the parameter setting that it, which has, can be solved the problems, such as to need plus the interconnection of more boards of redriver chips is brought, is system
Plenty of time human cost is saved in exploitation, improves design efficiency, succinct effective advantage.
To achieve these goals, the present invention adopts the following technical scheme that.
Illustrate the technical scheme exemplified by the PCIe interconnected between CPU and redriver.
CPU is on mainboard, and by plate upward wiring to connector, the connector of connector and an other board A interconnects,
Redriver is placed herein on card, as shown in Figure 1.
In design, cabling space and connector position are limited to, cabling has certain radian, i.e. outside cabling can compare
Line length is walked in inner side, and the signal Insertion Loss that this results in 4 groups of access redriver chips is inconsistent, and without unnecessary winding space,
Can not solve Insertion Loss difference by way of coiling；It is more abundant to the cabling space of redriver chips from connector on A cards, this
Sample can by A cards compensate coiling with solve the problems, such as mainboard can not coiling, be finally reached the core from CPU to redriver
The Insertion Loss uniformity of piece.
By above thinking, an Insertion Loss statistical form is established.According to the cabling situation of two boards, including line width line-spacing,
Cabling aspect, sheet material model etc. influence the key element of Insertion Loss, and the Insertion Loss of unit length is gone out using IMLC simulation calculations, then two plates
Card track lengths come out, and both draw total Insertion Loss value of each signal position after being multiplied.
Maximum difference is taken to draw maximum Insertion Loss difference value between each signal position by making the difference, finally by contrast
Can the tolerance amount of redriver chip same parameters judge cover this design with a parameter.
Beneficial effects of the present invention：The method that the embodiment of the present invention proposes, can solve to need to add the more of redriver chips
The parameter setting problem that board interconnection is brought, plenty of time human cost is saved for system development, improve design efficiency, it is succinct high
Effect.
Brief description of the drawings
Fig. 1 is the circuit connection diagram of embodiment.
Embodiment
The invention will be further described with embodiment below in conjunction with the accompanying drawings.
As shown in figure 1, CPU is on mainboard, and by plate upward wiring to connector, the company of connector and an other board A
Device interconnection is connect, redriver is placed herein on card.
Method by interconnecting coiling between signal Insertion Loss evaluation board, is comprised the steps of：
1）, according to mainboard cabling situation plan from CPU to connector cabling；
2）, according to redriver plate cablings situation plan from connector to redriver chip cablings；
3）, mainboard and redriver calorie unit Insertion Loss calculated by Intel Insertion Loss software for calculation IMLC；
4）, count mainboard and redriver card track lengths；
5）, obtained each key element inserted Insertion Loss statistical form；
6）, according to the suitable redriver plates loss values of redriver capabilities settings, adjustment redriver cards length value to satisfaction
The requirement of loss values；
7）, according to the track lengths after adjustment complete coiling on redriver cards.
By above step, you can solve the problems of Signal Integrity that hard disk dilatation duration link topology is brought.
Although above-mentioned the embodiment of the present invention is described with reference to accompanying drawing, model not is protected to the present invention
The limitation enclosed, one of ordinary skill in the art should be understood that on the basis of technical scheme those skilled in the art are not
Need to pay various modifications or deformation that creative work can make still within protection scope of the present invention.
Claims (1)
1. the method for coiling is interconnected between a kind of Insertion Loss evaluation board by signal, it is characterised in that comprise the steps of：
1）, according to mainboard cabling situation plan from CPU to connector cabling；
2）, according to redriver plate cablings situation plan from connector to redriver chip cablings；
3）, mainboard and redriver calorie unit Insertion Loss calculated by Intel Insertion Loss software for calculation IMLC；
4）, count mainboard and redriver card track lengths；
5）, obtained each key element inserted Insertion Loss statistical form；
6）, according to the suitable redriver plates loss values of redriver capabilities settings, adjustment redriver cards length value to satisfaction
The requirement of loss values；
7）, according to the track lengths after adjustment complete coiling on redriver cards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710773957.3A CN107808024B (en) | 2017-08-31 | 2017-08-31 | Method for evaluating interconnection winding between boards through signal insertion loss |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710773957.3A CN107808024B (en) | 2017-08-31 | 2017-08-31 | Method for evaluating interconnection winding between boards through signal insertion loss |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107808024A true CN107808024A (en) | 2018-03-16 |
| CN107808024B CN107808024B (en) | 2021-06-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710773957.3A Active CN107808024B (en) | 2017-08-31 | 2017-08-31 | Method for evaluating interconnection winding between boards through signal insertion loss |
Country Status (1)
| Country | Link |
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| CN (1) | CN107808024B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120087405A1 (en) * | 2010-10-12 | 2012-04-12 | Pericom Semiconductor Corp. | Trace Canceller with Equalizer Adjusted for Trace Length Driving Variable-Gain Amplifier with Automatic Gain Control Loop |
| CN103995185A (en) * | 2014-06-13 | 2014-08-20 | 浪潮电子信息产业股份有限公司 | Method for carrying out insertion loss test through simple probe |
| US20140237301A1 (en) * | 2013-02-15 | 2014-08-21 | Ivan Herrera Mejia | Preset evaluation to improve input/output performance in high-speed serial interconnects |
| US9276549B1 (en) * | 2014-09-12 | 2016-03-01 | ScienBiziP Consulting(Shenzhen)Co., Ltd. | Via system of printed circuit board and method of making same |
| US20160085902A1 (en) * | 2014-09-23 | 2016-03-24 | Dell Products, Lp | System and Method of Determining High Speed Resonance due to Coupling From Broadside Layers |
| CN105843765A (en) * | 2016-04-19 | 2016-08-10 | 浪潮电子信息产业股份有限公司 | Method for improving SATA signal integrity |
| CN106487462A (en) * | 2016-10-21 | 2017-03-08 | 郑州云海信息技术有限公司 | A kind of insertion loss method of testing and system |
-
2017
- 2017-08-31 CN CN201710773957.3A patent/CN107808024B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120087405A1 (en) * | 2010-10-12 | 2012-04-12 | Pericom Semiconductor Corp. | Trace Canceller with Equalizer Adjusted for Trace Length Driving Variable-Gain Amplifier with Automatic Gain Control Loop |
| US20150311950A1 (en) * | 2010-10-12 | 2015-10-29 | Pericom Semiconductor Corporation | Trace canceller with equalizer adjusted for trace length driving variable-gain amplifier with automatic gain control loop |
| US20140237301A1 (en) * | 2013-02-15 | 2014-08-21 | Ivan Herrera Mejia | Preset evaluation to improve input/output performance in high-speed serial interconnects |
| CN103995185A (en) * | 2014-06-13 | 2014-08-20 | 浪潮电子信息产业股份有限公司 | Method for carrying out insertion loss test through simple probe |
| US9276549B1 (en) * | 2014-09-12 | 2016-03-01 | ScienBiziP Consulting(Shenzhen)Co., Ltd. | Via system of printed circuit board and method of making same |
| US20160085902A1 (en) * | 2014-09-23 | 2016-03-24 | Dell Products, Lp | System and Method of Determining High Speed Resonance due to Coupling From Broadside Layers |
| CN105843765A (en) * | 2016-04-19 | 2016-08-10 | 浪潮电子信息产业股份有限公司 | Method for improving SATA signal integrity |
| CN106487462A (en) * | 2016-10-21 | 2017-03-08 | 郑州云海信息技术有限公司 | A kind of insertion loss method of testing and system |
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| CN107808024B (en) | 2021-06-29 |
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