CN107799471A - A kind of semiconductor devices and its manufacture method and electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method and electronic installation Download PDFInfo
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- CN107799471A CN107799471A CN201610802975.5A CN201610802975A CN107799471A CN 107799471 A CN107799471 A CN 107799471A CN 201610802975 A CN201610802975 A CN 201610802975A CN 107799471 A CN107799471 A CN 107799471A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000000034 method Methods 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000009434 installation Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 230000005540 biological transmission Effects 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims description 88
- 239000002184 metal Substances 0.000 claims description 88
- 239000000463 material Substances 0.000 claims description 57
- 230000004888 barrier function Effects 0.000 claims description 37
- 238000002955 isolation Methods 0.000 claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 229910010041 TiAlC Inorganic materials 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 4
- 229910010038 TiAl Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 330
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 36
- 238000005229 chemical vapour deposition Methods 0.000 description 25
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000608 laser ablation Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- -1 LDD ion Chemical class 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method and electronic installation, is related to technical field of semiconductors.Including：Semiconductor substrate is provided, the first fin structure, the second fin structure and the 3rd fin structure are respectively formed with pull up transistor area, the pull-down transistor area and the transmission gate transistor area on a semiconductor substrate；Remove the first dummy gate structure and the second dummy gate structure forms first grid groove and second grid groove；The first P-type workfunction layer is formed in the bottom of first grid groove in the area that pulls up transistor and side wall；The second P-type workfunction layer is formed on the bottom of first grid groove and side wall；The 3rd P-type workfunction layer is formed on first grid groove and the bottom of second grid groove and side wall in pull-down transistor area；N-type workfunction layer is formed on the bottom and side wall of first grid groove and second grid groove.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method and electronics
Device.
Background technology
In technical field of semiconductors, static RAM (SRAM) device is as a kind of typical semiconductor device
Part, it is widely used among the electronic equipments such as computer, mobile phone, digital camera.At present, there are some designs by fin field effect
Transistor device of the transistor (FinFET) as sram cell, to improve SRAM density and performance.
In order to adjust the α ratios of SRAM device, β ratios and γ ratios to obtain more preferable device performance, in the prior art
There is a kind of method to be：For the pulling up transistor (PU) of SRAM device, pull-down transistor (PD) and transmission gate transistor (PG) respectively
The fin structure of varying number is selected, such as：Respectively 1,1,1, or 1,2,1, or 1,3,2.
Different types of SRAM device, its metal gate stack structure are very different, to meet read and write margin (read
Margin and write margin) demand.In addition, threshold voltage (Vt) mismatch of different metal gate stack structures
(mismatch) performance is also different, and therefore, the static noise margin (static noise margin) of SRAM device also can be complete
Difference, and static noise margin is a key parameter for determining SRAM yields.
Regulation of the work-function layer for device is extremely important in FinFET, is generally selected in device fabrication process
Metal gate process forms work-function layer afterwards, and in order to meet the needs of device, TiAlC is needed to use as work function for NMOS
Layer, but the diffusion in boundary TiAlC is different, therefore Al diffusion is easy to influence the mismatch performance of SRAM device.
Therefore, in order to solve the above problems, it is necessary to propose a kind of manufacture method of new semiconductor devices.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, a kind of a kind of manufacture method of semiconductor devices of offer of the embodiment of the present invention, including：
Semiconductor substrate is provided, the Semiconductor substrate includes pull up transistor area, pull-down transistor area and transmission gate crystalline substance
Body area under control, pull up transistor area, the pull-down transistor area and the transmission gate crystal on the semiconductor substrate
The first fin structure, the second fin structure and the 3rd fin structure are respectively formed with area under control；
The first dummy gate structure of first fin structure and second fin structure is developed across, and across institute
State the second dummy gate structure of the 3rd fin structure；
Remove first dummy gate structure and form first grid groove, and remove second dummy gate structure and form the
Two gate recess；
In the bottom for pulling up transistor the first grid groove in area and form the first p-type work function in side wall
Layer；
The second P-type workfunction layer is formed on the bottom of the first grid groove and side wall；
Bottom and the side wall of the first grid groove and the second grid groove in the pull-down transistor area
The 3rd P-type workfunction layer of upper formation；
N-type workfunction layer is formed on the bottom and side wall of the first grid groove and the second grid groove.
Further, the 3rd fin structure is connected with second fin structure.
Further, at least one the 4th fin structure is also formed with the pull-down transistor area.
Further, the first grid groove is on the bearing of trend of the 4th fin structure the 4th described in exposed portion
Fin structure.
Further, it is further comprising the steps of before first P-type workfunction layer is formed：It is recessed in the first grid
High k dielectric layer is formed on the bottom and side wall of groove and the second grid groove, and the high k dielectric layer is made annealing treatment
The step of.
Further, after second P-type workfunction layer is formed, formed before the 3rd work-function layer, in addition to
The step on the first barrier layer is formed on second P-type workfunction layer to pull up transistor in area and pull-down transistor area
Suddenly.
Further, first P-type workfunction layer and second P-type workfunction layer, the material of the 3rd p-type work function
Material includes TiN.
Further, the material of the N-type workfunction layer includes one kind or combinations thereof in TiAl or TiAlC.
Further, it is further comprising the steps of after the N-type workfunction layer is formed：
The second barrier layer is formed on the N-type workfunction layer；
Metal gate electrode layer is filled in the first grid groove and the second grid groove.
Further, the step of forming the metal gate electrode layer includes：
Deposition forms metal material on the semiconductor substrate, and carries out cmp to the metal material,
To form the metal gate electrode layer, wherein, the top surface of the metal gate electrode layer and the first grid groove and described the
Flushed at the top of two gate recess.
Further, before the first grid groove and the second grid groove is formed, in the first fin knot
Isolation structure is also formed with Semiconductor substrate on the outside of structure, second fin structure and the 3rd fin structure, it is described
The top surface of isolation structure is less than the top surface of the first fin structure, second fin structure and the 3rd fin structure.
Further, before the high k dielectric layer is formed, the first grid groove and the second grid are additionally included in
The step of boundary layer, is formed on the bottom of groove.
Further aspect of the present invention provides a kind of semiconductor devices, including：
Semiconductor substrate, the Semiconductor substrate include pull up transistor area, pull-down transistor area and transmission gate transistor
Area, divide in pull up transistor area, pull-down transistor area and the transmission gate transistor area on the semiconductor substrate
Not formed with the first fin structure, the second fin structure and the 3rd fin structure；
First metal gate stack structure, it is formed at the area and across first fin structure, bag of pulling up transistor
Include the first P-type workfunction layer stacked gradually from bottom to top, the second P-type workfunction layer and N-type workfunction layer；
Second metal gate stack structure, it is formed in the pull-down transistor area, and across the second fin structure and institute
The first metal gate stack structure is stated to be connected, it is its described second P-type workfunction layer for including stacking gradually from bottom to top, described
3rd P-type workfunction layer and the N-type workfunction layer；
3rd metal gate stack structure, it is formed in the transmission gate transistor area, across the 3rd fin structure,
It includes the 3rd P-type workfunction layer stacked gradually from bottom to top and the N-type workfunction layer.
Further, the 3rd fin structure is connected with second fin structure.
Further, at least one the 4th fin structure is also formed with the pull-down transistor area.
Further, the second metal gate stack structure is across the 4th fin structure.
Further, between second P-type workfunction layer and N-type workfunction layer to pull up transistor in area, Yi Jisuo
State second P-type workfunction layer in pull-down transistor area and the 3rd P-type workfunction layer is additionally provided with the first barrier layer.
Further, formed with the second barrier layer on the N-type workfunction layer, formed with gold on second barrier layer
Belong to gate electrode layer.
Further, half on the outside of first fin structure, second fin structure and the 3rd fin structure
Isolation structure is also formed with conductor substrate, the top surface of the isolation structure is less than the first fin structure, the second fin knot
The top surface of structure and the 3rd fin structure.
Further aspect of the present invention provides a kind of electronic installation, and it includes foregoing semiconductor devices.
Manufacturing method according to the invention, it can cause to pull up PMOS first and the border of pull-down NMOS is conciser, phase
Influence between mutually is weaker, improves the mismatch performance of device；Secondly, metal gate stack structure is simpler, and and fin
Quantity be combined, it is easy to read and write margin is met the requirement of device；Furthermore formed below the of N-type workfunction layer
Three P-type workfunction layers, aluminium diffusion is completely eliminated, therefore also improve the mismatch performance of device, therefore, according to the system of the present invention
Method is made, the performance and yield of device can be improved.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 H show a kind of correlation step shape of the manufacture method of semiconductor devices in one embodiment of the invention
Into structure sectional view；
Fig. 2 shows the vertical view for the structure that a kind of manufacture method of semiconductor devices in one embodiment of the invention is obtained
Figure；
Fig. 3 shows a kind of indicative flowchart of the manufacture method of semiconductor devices of one embodiment of the invention；
Fig. 4 shows the schematic diagram of the electronic installation in one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
In order to solve the technical problem that presently, there are, the present invention provides a kind of manufacture method of semiconductor devices, such as Fig. 3 institutes
Show, it is mainly included the following steps that：
In step S301, there is provided Semiconductor substrate, the Semiconductor substrate include pull up transistor area, pull-down transistor
Area and transmission gate transistor area, pull up transistor area, the pull-down transistor area and the institute on the semiconductor substrate
State and the first fin structure, the second fin structure and the 3rd fin structure are respectively formed with transmission gate transistor area；
In step s 302, it is developed across the first dummy grid knot of first fin structure and second fin structure
Structure, and the second dummy gate structure across the 3rd fin structure；
In step S303, remove first dummy gate structure and form first grid groove, and it is pseudo- to remove described second
Grid structure forms second grid groove；
In step s 304, formed in the bottom for pulling up transistor the first grid groove in area and in side wall
First P-type workfunction layer；
In step S305, the second P-type workfunction layer is formed on the bottom of the first grid groove and side wall；
In step S306, the first grid groove and the second grid groove in the pull-down transistor area
Bottom and side wall on formed the 3rd P-type workfunction layer；
In step S307, N is formed on the bottom and side wall of the first grid groove and the second grid groove
Type work-function layer.
Manufacturing method according to the invention, the border to pull up transistor with pull-down transistor can make it that first
(boundary) more concise, mutual influence is weaker, improves the mismatch performance of device；Secondly, metal gate stack
Structure is simpler, and is combined with the quantity of fin, it is easy to read and write margin is met the requirement of device；Furthermore in N-type work(
The 3rd P-type workfunction layer formed below of function layer, aluminium diffusion is completely eliminated, therefore also improve the mismatch of device
Can, therefore, manufacturing method according to the invention, the performance and yield of device can be improved.
Embodiment one
Below, the manufacture method of the semiconductor devices of the present invention is described in detail with reference to figure 1A- Fig. 1 H, wherein, Figure 1A-
Fig. 1 H show cuing open for the structure that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
View；Fig. 2 shows the top view for the structure that a kind of manufacture method of semiconductor devices in one embodiment of the invention is obtained,
It is and corresponding with the structure in Fig. 1 H along the structure that Fig. 2 section lines are obtained.
Specifically, first, as shown in Figure 1A, there is provided Semiconductor substrate 100, the Semiconductor substrate 100 include upper crystal pulling
Body area under control, pull-down transistor area and transmission gate transistor area, the area that pulls up transistor on the semiconductor substrate, drop-down
The first fin structure 1021, the second fin structure 1022 and are respectively formed with transistor area and the transmission gate transistor area
Three fin structures 1023.
Specifically, the Semiconductor substrate 100 can be at least one of following material being previously mentioned：Silicon, insulator
Silicon (SSOI) is laminated on upper silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).Semiconductor substrate 100 uses silicon substrate in this embodiment.
Wherein described Semiconductor substrate 100 can include the active area for being used to be formed SRAM various composed components, for example,
For forming the area that pulls up transistor of the pulling up transistor of SRAM (PU), the drop-down of the pull-down transistor (PD) for forming SRAM
Transistor area, and for forming the transmission gate transistor area of transmission gate transistor (PG), wherein, pull up transistor as PMOS,
Pull-down transistor and transmission gate transistor are NMOS.
Then pad oxide skin(coating) (Pad oxide) is formed on the semiconductor substrate, wherein the pad oxide skin(coating)
The forming method of (Pad oxide) can be formed by the method for deposition, such as the side such as chemical vapor deposition, ald
Method, it can also be formed, will not be repeated here by the surface of Semiconductor substrate described in thermal oxide.
Further, the step of performing ion implanting can also be further included in this step, to be served as a contrast in the semiconductor
Various well regions are formed in bottom, for example, N-type well region (NW) is formed in the area that pulls up transistor, in pull-down transistor area and the biography
P type trap zone (PW) is formed in defeated door transistor area, wherein the ionic species and method for implanting that inject can be normal in this area
Method, do not repeat one by one herein.
Pull up transistor area, pull-down transistor area and the transmission gate transistor area on the semiconductor substrate
Inside it is respectively formed with the first fin structure 1021, the second fin structure 1022 and the 3rd fin structure 1023.
Wherein, the first fin structure 1021, the second fin structure 1022 and the 3rd fin structure 1023 serve as a contrast in semiconductor
Extend certain length on bottom in same direction, each fin structure can also be formed at it is multiple in Semiconductor substrate 200
Strip structure.
Further, at least one fourth fin parallel with the second fin structure 1022 is also formed with pull-down transistor area
Structure 1024, the 4th fin structure 1024 and the second fin structure 1022 are used to be formed SRAM pull-down transistor.
In one example, the second fin structure 1022 is connected with the 3rd fin structure 1023, and it can be respectively same
The different piece in pull-down transistor area and transmission gate transistor area respectively on one fin structure.
In one example, in order to obtain structure as shown in Figure 1A, following process steps can be performed：
First, step 1011 is performed, multiple fin structures are formed on a semiconductor substrate, for example, the first fin structure
1021st, the second fin structure 1022, the 3rd fin structure 1023 and the 4th fin structure 1024, the width whole phase of fin structure
Together, or fin is divided into multiple fin structure groups with different in width, and the length of fin structure can also differ.
Specifically, the forming method of the fin structure is not limited to a certain kind, and a kind of exemplary shape is given below
Into method：Hard mask layer (not shown) is formed on a semiconductor substrate, and this area can be used by forming the hard mask layer
The various suitable techniques that technical staff is familiar with, such as chemical vapor deposition method, the hard mask layer can be from lower and
The oxide skin(coating) and silicon nitride layer of upper stacking；The hard mask layer is patterned, is formed for etching Semiconductor substrate with thereon
Multiple masks being isolated from each other of fin are formed, in one embodiment, using self-aligned double patterning case (SADP) process implementing institute
State patterning process；Semiconductor substrate is etched to be formed on fin structure.
Then, step 1012 is can also carry out, in first fin structure 1021, second fin structure 1022 and institute
State and isolation structure 101 is formed in the Semiconductor substrate in the outside of the 3rd fin structure 1023, the top surface of the isolation structure 101 is less than
The top surface of first fin structure, second fin structure and the 3rd fin structure.
Specifically, depositing isolation material layer, to be filled up completely with the gap between fin structure.In one embodiment, adopt
Implement the deposition with the chemical vapor deposition method with flowable.The material of spacer material layer can with selective oxidation thing,
Such as high-aspect-ratio technique (HARP) oxide, it is specifically as follows silica.
Then spacer material layer described in etch-back, to the object height of the fin structure, to form isolation structure 101.
Specifically, spacer material layer described in etch-back, with fin described in exposed portion, and then the fin with certain height is formed.
Then, step 1013 is performed, is developed across first fin structure 1021, the 4th fin structure 1024 and second
First dummy gate structure of fin structure 1022, and the second dummy grid knot of the 3rd fin structure 1023 is also developed across simultaneously
Structure, wherein dummy gate structure include dummy grid dielectric layer and dummy grid material layer.
It is pointed out that the term " across " used in the present invention, such as across fin structure (such as the first fin
Structure, second fin structure etc.) dummy gate structure, refer to be each formed with puppet in the upper surface of the part of fin structure and side
Grid structure, and the dummy gate structure is also formed on the part surface of Semiconductor substrate.Herein for the explanation of " across "
It is equally applicable to cited below across metal gate stack structure of fin structure etc..
In one example, first can be sequentially depositing to form dummy grid dielectric layer and dummy grid material on a semiconductor substrate
Layer.
Wherein, the dummy grid dielectric layer can select conventional oxide, such as SiO2, the dummy grid material layer can
To select semi-conducting material commonly used in the art, such as polysilicon etc. can be selected, it is not limited to it is a certain, it is not another herein
One enumerates.
The deposition process of the dummy grid material layer can select the methods of chemical vapor deposition or ald.
Then the dummy grid dielectric layer and dummy grid material layer are patterned, to form first dummy gate structure and
Two dummy gate structures.Specifically, photoresist layer is formed in the dummy grid material layer, then exposure imaging, to form opening,
Then using the photoresist layer as dummy grid material layer described in mask etch.
Afterwards, also optionally, skew side is formed in the side wall of the first dummy gate structure and the second dummy gate structure
Wall (Spacer).
Specifically, the offset side wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.As an embodiment of the present embodiment, the offset side wall is silica, silicon nitride collectively constitutes, and concrete technology is：
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on a semiconductor substrate, then using engraving method
Form offset side wall.Skew side can also be respectively formed in the top surface and side wall of the first dummy gate structure and the second dummy gate structure
The walling bed of material, afterwards the step of in by the method for planarization, such as cmp, by the offset side wall material on top surface
The bed of material removes, and forms the offset side wall being located only within side wall.
Alternatively, LDD ion implantings step and work are performed in NMOS dummy gate structures and PMOS dummy gate structures both sides
Change.
Alternatively, gap is formed on the offset side wall of the NMOS dummy gate structures and the PMOS dummy gate structures
Wall.
Specifically, on the offset side wall formed formed clearance wall (Spacer), the clearance wall can be silica,
A kind of or their combinations are formed in silicon nitride, silicon oxynitride.As an embodiment of the present embodiment, the clearance wall is
Silica, silicon nitride collectively constitute, and concrete technology is：The first silicon oxide layer, the first silicon nitride layer are formed on a semiconductor substrate
And second silicon oxide layer, clearance wall is then formed using engraving method.
Then, step 1014 is performed, performs source and drain ion implanting, and the of the both sides of the first foregoing dummy gate structure
Respective source-drain electrode is formed respectively in one fin structure 1021, the second fin structure 1022 and the 4th fin structure 1024,
The source-drain electrode of transmission gate transistor is formed in 3rd fin structure 1023 of the both sides of two dummy gate structures, wherein, in the second fin
When chip architecture 1022 is connected with the 3rd fin structure 1023, shape in the drain electrode of transmission gate transistor and the second fin structure 1022
Into pull-down transistor drain electrode electrical connection, or shared identical drain electrode.
Then, step 1015 is performed, the interlayer dielectric layer (not shown) is deposited and planarizes, to fill each puppet
Gap between grid structure.
Specifically, interlevel dielectric deposition and planarize, planarization is described to interlayer dielectric layer to the dummy gate structure
Top.
Wherein, the interlayer dielectric layer can select dielectric material commonly used in the art, such as various oxides etc.,
Interlayer dielectric layer can select SiO in the embodiment2, its thickness is not limited to a certain numerical value.
The non-limiting examples of the planarization process include mechanical planarization method and chemically mechanical polishing planarization side
Method.
Afterwards, continue as shown in Figure 1A, the first dummy gate structure and the second dummy gate structure to be removed, with the semiconductor
First grid groove and second grid groove are formed on substrate.
Wherein, remove first dummy gate structure and form first grid groove, remove the second dummy gate structure shape
Into the second grid groove, the first grid groove pulls up transistor in area and the pull-down transistor area positioned at described,
And on the bearing of trend of first fin structure and second fin structure the first fin structure described in exposed portion and
Second fin structure, and further, when four fin structures 1024 is formed in pull-down transistor area, the first grid
Groove can also the 4th fin structure 1024 described in exposed portion.
The second grid groove is located in the transmission gate transistor area, and in the extension side of the 3rd fin structure
3rd fin structure described in upward exposed portion, wherein, in the present embodiment, the figure shown in Figure 1A to Fig. 1 H is recessed along grid
The bearing of trend extension of the groove and face vertical with the surface of Semiconductor substrate is gone to cut open semiconductor devices and obtain sectional view.
Specifically, the dummy grid material layer can be first removed in this step, then the dummy grid dielectric layer again.
Exemplarily, the dummy grid material layer (such as polysilicon layer) is removed, forms groove.The method of the removal can
To be photoetching and etching.Gas used includes HBr in etching process, and it is as main etch gas；Also include as quarter
Lose the O of make-up gas2Or Ar, it can improve the quality of etching.
Then the dummy grid dielectric layer is removed from SiCoNi method, to expose the fin.It is in this step
Reduce and remove damage during the dummy grid dielectric layer to other materials layer, be no longer etched from HF, but select
With the higher SiCoNi processing procedures of selectivity, the dummy grid dielectric layer is removed by methods described, device will not be caused to damage.
Then, continue as shown in Figure 1A, in the bottom and side wall of the first grid groove and the second grid groove
On sequentially form the high P-type workfunction layer 1041 of k dielectric layer 103 and first.
Alternatively, before the high k dielectric layer 103 is formed, the first grid groove and described second are additionally included in
The step of boundary layer (not shown), is formed on the bottom of gate recess.
The constituent material of interface (IL) layer includes Si oxide (SiOx), and the effect for forming boundary layer is to improve high k dielectric
Interfacial characteristics between layer and Semiconductor substrate.IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or
Other suitable film layers.Thermal oxide, chemical vapor deposition (CVD), ald (ALD) or physical vapor can be used
Deposit the suitable technique such as (PVD) and form boundary layer.The thickness range of boundary layer is 5 angstroms to 10 angstroms.
The k values (dielectric constant) of high k dielectric layer 103 are usually more than 3.9, and its constituent material includes hafnium oxide, hafnium oxide
Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia
Titanium, aluminum oxide etc., preferably hafnium oxide, zirconium oxide or aluminum oxide.Chemical vapour deposition technique (CVD), atomic layer can be used
The suitable technique such as sedimentation (ALD) or physical vaporous deposition (PVD) forms high k dielectric layer 103.High k dielectric layer 103
Thickness range is 10 angstroms to 30 angstroms.
Alternatively, after high k dielectric layer 103 is formed, high k dielectric layer 103 can also be made annealing treatment.At the annealing
It can be any suitable method for annealing well known to those skilled in the art to manage, such as rapid thermal annealing, furnace anneal etc..Example
Such as, using atomic layer deposition method deposit hafnium oxides as high k dielectric layer 103, in order to obtain the pure crystalline texture of hafnium oxide, it is necessary to
High k dielectric layer is made annealing treatment, such as 400~600 DEG C, annealed 30s~600s, and the annealing is deposited after being referred to as and moved back
Fiery (PDA).
The material of first P-type workfunction layer (PWF) 1041 can select be but be not limited to TixN1-x, TaC, MoN, TaN or
Person's combinations thereof or other suitable film layers.Wherein it is preferred that the material of the first P-type workfunction layer can use TiN.
The suitable technique such as CVD, ALD or PVD can be used to form the first P-type workfunction layer 1041.First P-type workfunction layer 1041
Thickness range be 10 angstroms to 580 angstroms.
Exemplarily, pulled up transistor described in area and the pull-down transistor area, the high p-type of k dielectric layer 103 and first
Work-function layer 1041 is formed in the first grid groove, and across first fin structure 1021, the 4th fin
Structure 1024 and second fin structure 1022, in the transmission gate transistor area, the high p-type work(of k dielectric layer 103 and first
Function layer 1041 is formed in the second grid groove, and across the 3rd fin structure 1023.
Then, as shown in Figure 1B, the first P in the pull-down transistor area and the transmission gate transistor area is removed
Type work-function layer 1041, the high k dielectric layer 103 of exposure, with the bottom for pulling up transistor the first grid groove in area
The first P-type workfunction layer is formed in portion and side wall.
Specifically, the photoresist layer (not shown) of patterning, the photoresist of the patterning are formed on a semiconductor substrate 100
First P-type workfunction layer 1041 in the floor exposure pull-down transistor area and the transmission gate transistor area, covers institute
State the area that pulls up transistor.
Afterwards, any lithographic method well known to those skilled in the art can be used to realize to the first p-type work content in this step
Several layers 1041 of removal, including but not limited to wet etching or dry etching.Wherein carved preferably with dry etching, dry method
Erosion can be any combination of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.
Single lithographic method can be used, or more than one lithographic method can also be used.
Then, as shown in Figure 1 C, on the bottom and side wall of the first grid groove and the second grid groove according to
The second P-type workfunction layer 1042 of secondary formation and the first barrier layer 105.
Wherein, the second P-type workfunction layer 1042 in the area that pulls up transistor formed the first P-type workfunction layer 1041 it
On, second P-type workfunction layer 1042 in the pull-down transistor area and in the transmission gate transistor area is formed
On high k dielectric layer 103.
Specifically, the second P-type workfunction layer 1042 can use and the identical material of the first foregoing P-type workfunction layer 1041
Material, such as can be all TiN, different materials can also be used.
Wherein, the material of the second P-type workfunction layer 1042 can select be but be not limited to TixN1-x, TaC, MoN, TaN or
Person's combinations thereof or other suitable film layers.Wherein it is preferred that the second P-type workfunction layer 1042 can use TiN.Can
To form the second P-type workfunction layer 1042 using CVD, ALD or PVD etc. suitable technique.Second P-type workfunction layer 1042
Thickness range is 10 angstroms to 580 angstroms.
The material on first barrier layer 105 includes tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, nitrogen
Change the one or more in tungsten, in the present embodiment, the first barrier layer 105 is preferably tantalum nitride (TaN).
First barrier layer 105 can deposit by such as physical vapour deposition (PVD), ald, rotary coating (spin-on)
Or the processing procedure of other proper methods is formed.First barrier layer 105 can in the temperature between -40~400 DEG C with about between 0.1~
Formed under the pressure of 100 millitorrs (mTorr).In addition, the first barrier layer 105 may also include multiple film layers.
Then, as shown in figure iD, the first barrier layer 105 in the transmission gate transistor area and second p-type are removed
Work-function layer 1042, expose the high k dielectric layer 103, only to form on the bottom of the first grid groove and side wall
Two P-type workfunction layers.
Specifically, the photoresist layer (not shown) of patterning, the photoresist of the patterning are formed on a semiconductor substrate 100
Floor exposes second P-type workfunction layer 1042 in the transmission gate transistor area, and pull up transistor Qu Hesuo described in covering
State pull-down transistor area.
Afterwards, it can first etch the first barrier layer 105 of removal and remove the second P-type workfunction layer 1042 again, this area can be used
Any lithographic method known to technical staff is realized to the first barrier layer 105 in this step and the second P-type workfunction layer 1042
Remove, including but not limited to wherein preferably with dry etching, dry etching can be anti-for wet etching or dry etching
Answer any combination of ion etching, ion beam etching, plasma etching, laser ablation or these methods.It can also use single
One lithographic method, or more than one lithographic method can also be used.
Then, as referring to figure 1E, the shape on the bottom and side wall of the first grid groove and the second grid groove
Into the 3rd P-type workfunction layer 1043.
Wherein, the 3rd P-type workfunction layer 1043 in the area that pulls up transistor and in the pull-down transistor area is formed
On first barrier layer 105, the 3rd P-type workfunction layer 1043 in the transmission gate transistor area is formed in high k dielectric layer
On 103.
Specifically, the 3rd P-type workfunction layer 1043 can use and the first foregoing P-type workfunction layer 1041 and the 2nd P
The identical material of type work-function layer 1042, such as can be all TiN, different materials can also be used.
Wherein, the material of the 3rd P-type workfunction layer 1043 can select be but be not limited to TixN1-x, TaC, MoN, TaN or
Person's combinations thereof or other suitable film layers.Wherein it is preferred that the 3rd P-type workfunction layer 1043 can use TiN.Can
To form the 3rd P-type workfunction layer 1043 using CVD, ALD or PVD etc. suitable technique.3rd P-type workfunction layer 1043
Thickness range is 10 angstroms to 580 angstroms.
Afterwards, as shown in fig. 1F, the 3rd P-type workfunction layer 1043 to be pulled up transistor described in removal in area, with
The 3rd P is formed on the first grid groove and the bottom of the second grid groove and side wall in the pull-down transistor area
Type work-function layer.
Specifically, the photoresist layer (not shown) of patterning, the photoresist of the patterning are formed on a semiconductor substrate 100
Second P-type workfunction layer 1042 to be pulled up transistor described in floor exposure in area, covers the transmission gate transistor area and institute
State pull-down transistor area.
Afterwards, any lithographic method well known to those skilled in the art can be used to realize to the 3rd p-type described in this step
The removal of work-function layer 1043, including but not limited to wet etching or dry etching wherein preferably with dry etching, are done
Method etching can be any group of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods
Close.Single lithographic method can also be used, or more than one lithographic method can also be used.
Wherein, in this step, the 3rd p-type work content in transmission gate transistor area and the pull-down transistor area is remained
Several layers 1043, the 3rd P-type workfunction layer 1043 can rise to the aluminium in the N-type workfunction layer (for example, TiAlC) that is subsequently formed
To barrier effect.
Then, as shown in Figure 1 G, the shape on the bottom and side wall of the first grid groove and the second grid groove
Into N-type workfunction layer 106.
The material of N-type workfunction layer 106 can select be but be not limited to TaAlC, TaC, Ti, Al, TixAl1-x or its
The film layer that he is adapted to.The material of N-type workfunction layer 106 is preferably TiAlC.CVD, ALD or PVD etc. can be used to be adapted to
Technique formed N-type workfunction layer 106.The thickness range of N-type workfunction layer 106 is 10 angstroms to 80 angstroms.
N-type workfunction layer 106 is formed on the bottom and side wall of the first grid groove and the second grid groove,
Namely N-type workfunction layer 106 has been respectively formed it in the area that pulls up transistor, pull-down transistor area and transmission gate transistor area.
Finally, as shown in fig. 1H, metal gate electrode is filled in the first grid groove and the second grid groove
Layer 107.
In one example, before metal gate electrode layer 107 is formed, in addition to the shape on the N-type workfunction layer 106
The step of into the second barrier layer (not shown).
Wherein, the material on the second barrier layer can include TiN or other suitable materials.
The material of metal gate electrode layer 107 can select to be but be not limited to Al, W or other suitable film layers.Can be with
The technique being adapted to using CVD, ALD or PVD etc. forms metal gate electrode layer 107.
In one example, form metal W using chemical vapor deposition method and be used as metal gate electrode layer 107.Wherein,
CVD techniques use WF6As reacting gas, WF is decomposed6Deposition forms metal W.
Exemplarily, deposited metal gate electrode layer 107 fills all gate recess, and spills into the table of interlayer dielectric layer
Above face, then flatening process is performed, such as cmp or wet etching etc., until exposing interlayer dielectric layer (not
Show) surface, even if also the top surface of the metal gate electrode layer 107 and the first grid groove and the second grid are recessed
Flushed at the top of groove.The multiple film layers one that will can be also deposited in the lump in abovementioned steps in interlayer dielectric layer surface in the process
And remove.
Wherein, in one example, as shown in Fig. 2 metal gate electrode layer 107 is located at the portion in the first grid groove
Divide across first fin structure 1021, second fin structure 1022 and the 4th fin structure 1024.
So far the making of the semiconductor devices for the present invention is completed, wherein the semiconductor devices of the present invention can be
SRAM device, as shown in Fig. 2 the SRAM device includes being formed at pull up transistor (PU) in the area that pulls up transistor, it is formed at down
Pull-down transistor (PD) in crystal pulling area under control and the transmission gate transistor (PU) being formed in transmission gate transistor area.
In one example, the first metal gate stack structure to pull up transistor is across first fin structure
1021, including boundary layer, high k dielectric layer 103, the first P-type workfunction layer 1041, the second p-type work(stacked gradually from bottom to top
Function layer 1042, the first barrier layer 103, N-type workfunction layer 106, the second barrier layer (not shown) and metal gate electrode layer 107；
And the second metal gate stack structure of pull-down transistor is across the second fin structure 1022 and the 4th fin structure 1024, and with
The the first metal gate stack structure to pull up transistor is connected, and the second metal gate stack structure includes from bottom to top layer successively
Folded boundary layer, high k dielectric layer 103, the second P-type workfunction layer 1042, the first barrier layer 103, the 3rd P-type workfunction layer
1043rd, N-type workfunction layer 106, the second barrier layer (not shown) and metal gate electrode layer 107, therefore, the metal to pull up transistor
The metal gate stack structure of gate stack structure and pull-down transistor electrically connects；3rd metal gates of transmission gate transistor are folded
Rotating fields can be connected across the 3rd fin structure 1023, the 3rd fin structure 1023 with the second fin structure 1022,
3rd metal gate stack structure include stack gradually from bottom to top boundary layer (not shown), high k dielectric layer 103, the 3rd p-type
Work-function layer 1043, N-type workfunction layer 106, the second barrier layer (not shown) and metal gate electrode layer 107.
In summary, manufacturing method according to the invention, the side to pull up transistor with pull-down transistor can make it that first
Boundary (boundary) is more concise, and mutual influence is weaker, improves the mismatch performance of device；Secondly, metal gates are folded
Rotating fields are simpler, and are combined with the quantity of fin, it is easy to read and write margin is met the requirement of device；Furthermore in N-type
The 3rd P-type workfunction layer formed below of work-function layer, aluminium diffusion is completely eliminated, therefore also improve the mismatch of device
Can, therefore, manufacturing method according to the invention, the performance and yield of device can be improved.
Embodiment two
The present invention also provides a kind of semiconductor devices formed using the foregoing method implemented in one, and the semiconductor devices can
Think SRAM device.
Below, the semiconductor devices of the present invention is described in detail with reference to such as Fig. 1 H and Fig. 2.
First, semiconductor devices of the invention includes：Semiconductor substrate 100, the Semiconductor substrate 100 include upper crystal pulling
Body area under control, pull-down transistor area and transmission gate transistor area, the area that pulls up transistor on the semiconductor substrate, drop-down
The first fin structure 1021, the second fin structure 1022 and are respectively formed with transistor area and the transmission gate transistor area
Three fin structures 1023.
Wherein described Semiconductor substrate 100 can include the active area for being used to be formed SRAM various composed components, for example,
Pulling up transistor includes formed with PMOS device, its pull up transistor (PU) as SRAM, pull-down transistor in area in area
Nmos device, its pull-down transistor (PD) as SRAM, include nmos device in transmission gate transistor area, it is as SRAM's
Transmission gate transistor (PG).
Further, various well regions are formed in the Semiconductor substrate 100, for example, forming N-type trap in the area that pulls up transistor
Area (NW), P type trap zone (PW) is formed in pull-down transistor area and in the transmission gate transistor area, wherein the ion species injected
Class and method for implanting can be method commonly used in the art, not repeat one by one herein.
Pull up transistor area, pull-down transistor area and the transmission gate transistor area on the semiconductor substrate
Inside it is respectively formed with the first fin structure 1021, the second fin structure 1022 and the 3rd fin structure 1023.
Wherein, the first fin structure 1021, the second fin structure 1022 and the 3rd fin structure 1023 serve as a contrast in semiconductor
Extend certain length on bottom in same direction, each fin structure can also be formed at it is multiple in Semiconductor substrate 200
Strip structure.
Further, at least one fourth fin parallel with the second fin structure 1022 is also formed with pull-down transistor area
Structure 1024, the 4th fin structure 1024 and the second fin structure 1022 are used to be formed SRAM pull-down transistor.
In one example, the second fin structure 1022 is connected with the 3rd fin structure 1023, and it can be respectively same
The different piece in pull-down transistor area and transmission gate transistor area respectively on one fin structure.
Wherein, the width of fin structure is all identical, or fin is divided into multiple fin structure groups with different in width,
The length of fin structure can also differ.
Further, in first fin structure 1021, second fin structure 1022, the 3rd fin structure
1023 and the outside of the 4th fin structure 1024 Semiconductor substrate 100 on be also formed with isolation structure 101, the isolation structure
101 top surface is less than the top surface of each fin structure.
The material of isolation structure 101 can be with selective oxidation thing, such as high-aspect-ratio technique (HARP) oxide, specifically can be with
Can also be that silica obtained etc. is deposited by the chemical vapor deposition method of flowable for silica.
The semiconductor devices of the present invention also includes being formed at described pull up transistor in area and across the first fin knot
First metal gate stack structure of structure 1021, it includes high k dielectric layer 103, the first p-type work content stacked gradually from bottom to top
Several layers of the 1041, second P-type workfunction layer 1042, N-type workfunction layer 106 and metal gate electrode layer 107.
In one example, in second P-type workfunction layer 1042 and N-type workfunction layer to pull up transistor in area
The first barrier layer 105 is additionally provided between 106.
Further, semiconductor devices of the invention also includes being formed at the second metal gates in the pull-down transistor area
Laminated construction, it is connected across the second fin structure 1022 and with the first metal gate stack structure, and it is included under
The high k dielectric layer 103 that is stacked gradually on and, second P-type workfunction layer 1042, the 3rd P-type workfunction layer
4043rd, the N-type workfunction layer 106 and the metal gate electrode layer 107.
Exemplarily, should when four fin structures 1024 is set in pull-down transistor area on the semiconductor substrate
Second metal gate stack structure is also across the 4th fin structure 1024.
Further, second P-type workfunction layer 1042 in the pull-down transistor area and the 3rd p-type work content
It is also equipped with the first barrier layer 105 for several layers 4013.
Wherein, the first barrier layer 105 to pull up transistor in area and pull-down transistor area is continuously across the first fin knot
The fin structure 1022 of structure 1021 and second, wherein, on the outside of the second fin structure set four fin structures 1024 when, also across
4th fin structure 1024.
Further, semiconductor devices of the invention also includes the 3rd metal being formed in the transmission gate transistor area
Gate stack structure, it is across the 3rd fin structure 1023, including the high k dielectric layer stacked gradually from bottom to top
103rd, the 3rd P-type workfunction layer 1043, the N-type workfunction layer 106 and the metal gate electrode layer 107.
Exemplarily, boundary layer (not shown) is also equipped with the lower section of high k dielectric layer 103, the boundary layer is formed in portion
Point surface of Semiconductor substrate 100 and the first fin structure 1021, the second fin structure 1022, the 3rd fin structure 1023 and the
On the surface of four fin structures 1024.
Further, folded in the first metal gate stack structure, the second metal gate stack structure and the 3rd metal gates
In Rotating fields, it is provided with the second barrier layer between the metal gate electrode layer 107 and the N-type workfunction layer 106 and (does not show
Go out).Wherein, the material on the second barrier layer can include TiN or other suitable materials.
The constituent material of interface (IL) layer includes Si oxide (SiOx), and the effect for forming boundary layer is to improve high k dielectric
Interfacial characteristics between layer and Semiconductor substrate.IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or
Other suitable film layers.Thermal oxide, chemical vapor deposition (CVD), ald (ALD) or physical vapor can be used
Deposit the suitable technique such as (PVD) and form boundary layer.The thickness range of boundary layer is 5 angstroms to 10 angstroms.
The k values (dielectric constant) of high k dielectric layer 103 are usually more than 3.9, and its constituent material includes hafnium oxide, hafnium oxide
Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia
Titanium, aluminum oxide etc., preferably hafnium oxide, zirconium oxide or aluminum oxide.Chemical vapour deposition technique (CVD), atomic layer can be used
The suitable technique such as sedimentation (ALD) or physical vaporous deposition (PVD) forms high k dielectric layer 103.High k dielectric layer 103
Thickness range is 10 angstroms to 30 angstroms.
The 1041, second P-type workfunction layer of first P-type workfunction layer (PWF) (PWF) 1042 and the 3rd P-type workfunction layer
(PWF) 1043 material can select to be but be not limited to TixN1-x, TaC, MoN, TaN either combinations thereof or other are suitable
The film layer of conjunction.Wherein it is preferred that the material of each P-type workfunction layer can use TiN.Can use CVD, ALD or
Technique suitable PVD etc. forms P-type workfunction layer.The thickness range of each P-type workfunction layer 1041 is 10 angstroms to 580 angstroms.Its
In, each P-type workfunction layer can also use different materials, can also have different thickness.
The material on first barrier layer 105 includes tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, nitrogen
Change the one or more in tungsten, in the present embodiment, the first barrier layer 105 is preferably tantalum nitride (TaN).
First barrier layer 105 can deposit by such as physical vapour deposition (PVD), ald, rotary coating (spin-on)
Or the processing procedure of other proper methods is formed.In addition, the first barrier layer 105 may also include multiple film layers.
The material of N-type workfunction layer 106 can select be but be not limited to TaAlC, TaC, Ti, Al, TixAl1-x or its
The film layer that he is adapted to.The material of N-type workfunction layer 106 is preferably TiAlC.CVD, ALD or PVD etc. can be used to be adapted to
Technique formed N-type workfunction layer 106.The thickness range of N-type workfunction layer 106 is 10 angstroms to 80 angstroms.
The material of metal gate electrode layer 107 can select to be but be not limited to Al, W or other suitable film layers.Can be with
The technique being adapted to using CVD, ALD or PVD etc. forms metal gate electrode layer 107.
In one example, form metal W using chemical vapor deposition method and be used as metal gate electrode layer 107.Wherein,
CVD techniques use WF6As reacting gas, WF is decomposed6Deposition forms metal W.
In one example, in the first metal gate stack structure, the second metal gate stack structure and the 3rd metal gate
Offset side wall (Spacer) is formed in the side wall of pole laminated construction.
Specifically, the offset side wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.As an embodiment of the present embodiment, the offset side wall is silica, silicon nitride collectively constitutes, and concrete technology is：
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on a semiconductor substrate, then using engraving method
Form offset side wall.Skew side can also be respectively formed in the top surface and side wall of the first dummy gate structure and the second dummy gate structure
The walling bed of material, afterwards the step of in by the method for planarization, such as cmp, by the offset side wall material on top surface
The bed of material removes, and forms the offset side wall being located only within side wall.
In the inclined of the first metal gate stack structure, the second metal gate stack structure and the 3rd metal gate stack structure
Move on side wall and form clearance wall.
Specifically, on the offset side wall formed formed clearance wall (Spacer), the clearance wall can be silica,
A kind of or their combinations are formed in silicon nitride, silicon oxynitride.As an embodiment of the present embodiment, the clearance wall is
Silica, silicon nitride collectively constitute, and concrete technology is：The first silicon oxide layer, the first silicon nitride layer are formed on a semiconductor substrate
And second silicon oxide layer, clearance wall is then formed using engraving method.
Further, it is also formed with crystal pulling in the first fin structure 1021 of the first metal gate stack structure both sides
The source electrode of body pipe and drain electrode, the second fin structure 1022 and the 4th fin structure in the second metal gate stack structure both sides
Respective source-drain electrode is formed in 1024 respectively, the shape in the 3rd fin structure 1023 of the both sides of the 3rd metal gate stack structure
Into the source-drain electrode of transmission gate transistor, wherein, when the second fin structure 1022 is connected with the 3rd fin structure 1023, transmission
The drain electrode electrical connection of the pull-down transistor formed in the drain electrode of door transistor and the second fin structure 1022, or shared identical
Drain electrode.
Formed with interlayer dielectric layer, the first metal gate stack structure, second on the semiconductor substrate surface
Metal gate stack structure and the 3rd metal gate stack structure are located in the interlayer dielectric layer, the top surface of the interlayer dielectric layer
Flushed with the top surface of metal gate stack structure.
The interlayer dielectric layer can select dielectric material commonly used in the art, such as various oxides etc., and interlayer is situated between
Electric layer can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma
(HDP) material layer for having doped or undoped silica that manufacturing process is formed, such as undoped silica glass (USG),
Phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be adulterate boron or adulterate phosphorus from spin coating
Cloth glass (spin-on-glass, SOG), the tetraethoxysilane (PTEOS) for adulterating phosphorus or the tetraethoxysilane for adulterating boron
(BTEOS)。
Other elements are also possible that for complete device, for example, the metal of the extractions such as source electrode, drain electrode, grid is mutual
Link structure etc., will not be repeated here.
Wherein semiconductor devices of the invention can be SRAM device, as shown in Fig. 2 the SRAM device includes being formed at
Crystal pulling area under control pulls up transistor (PU), the pull-down transistor being formed in pull-down transistor area (PD) and is formed at transmission gate
Transmission gate transistor (PU) in transistor area, wherein, the first metal gate stack structure to pull up transistor and lower crystal pulling
The second metal gate stack structure electrical connection of pipe, at least drain electrode of a pull-down transistor and the drain electrode of transmission gate transistor are electrically connected
Connect or share a drain electrode.
In summary, semiconductor devices of the invention using foregoing manufacture method due to being prepared, therefore is also had
The advantages of corresponding, pull up transistor the influence more concise, mutual with the border of pull-down transistor (boundary) first
It is weaker, improve the mismatch performance of device；Secondly, metal gate stack structure is simpler, and is combined with the quantity of fin,
It is easy to the requirement for making read and write margin meet device；Furthermore in the 3rd P-type workfunction layer formed below of N-type workfunction layer,
Aluminium diffusion is completely eliminated, therefore also improves the mismatch performance of device, therefore, therefore the semiconductor devices of the present invention has more
High performance.
Embodiment three
Present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment two, the semiconductor device
Part is prepared according to the methods described of embodiment one.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, DPF, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, or any intermediate products including circuit.The electronic installation of the embodiment of the present invention, due to having used above-mentioned circuit,
Thus there is better performance.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401
Display portion 402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：
Semiconductor substrate, the Semiconductor substrate include pull up transistor area, pull-down transistor area and transmission gate transistor
Area, divide in pull up transistor area, pull-down transistor area and the transmission gate transistor area on the semiconductor substrate
Not formed with the first fin structure, the second fin structure and the 3rd fin structure；
First metal gate stack structure, it is formed at the area and across first fin structure, bag of pulling up transistor
Include the high k dielectric layer stacked gradually from bottom to top, the first P-type workfunction layer, the second P-type workfunction layer, N-type workfunction layer and gold
Belong to gate electrode layer；
Second metal gate stack structure, it is formed in the pull-down transistor area, and across the second fin structure and institute
State the first metal gate stack structure to be connected, its high k dielectric layer for including stacking gradually from bottom to top, described 2nd P
Type work-function layer, the 3rd P-type workfunction layer, the N-type workfunction layer and the metal gate electrode layer；
3rd metal gate stack structure, the transmission gate transistor area is formed at, across the 3rd fin structure, its
Including stack gradually from bottom to top the high k dielectric layer, the 3rd P-type workfunction layer, the N-type workfunction layer and described
Metal gate electrode layer.
The semiconductor devices has advantages below：Pull up transistor first with the border of pull-down transistor (boundary) more
Add simplicity, mutual influence is weaker, improves the mismatch performance of device；Secondly, metal gate stack structure is simpler,
And it is combined with the quantity of fin, it is easy to read and write margin is met the requirement of device；Furthermore in the lower section of N-type workfunction layer
Formed with the 3rd P-type workfunction layer, aluminium diffusion is completely eliminated, therefore also improves the mismatch performance of device, therefore, therefore this
The semiconductor devices of invention has higher performance.
Because the electronic installation of the present invention includes foregoing semiconductor devices, so the semiconductor devices has the advantage that,
Same electronic installation also has.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (20)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that including：Semiconductor substrate is provided, the Semiconductor substrate includes pull up transistor area, pull-down transistor area and transmission gate transistor Area, pull up transistor area, the pull-down transistor area and the transmission gate transistor area on the semiconductor substrate Inside it is respectively formed with the first fin structure, the second fin structure and the 3rd fin structure；The first dummy gate structure of first fin structure and second fin structure is developed across, and across described Second dummy gate structure of three fin structures；Remove first dummy gate structure and form first grid groove, and remove second dummy gate structure and form second gate Pole groove；In the bottom for pulling up transistor the first grid groove in area and form the first P-type workfunction layer in side wall；The second P-type workfunction layer is formed on the bottom of the first grid groove and side wall；Shape on the first grid groove and the bottom of the second grid groove and side wall in the pull-down transistor area Into the 3rd P-type workfunction layer；N-type workfunction layer is formed on the bottom and side wall of the first grid groove and the second grid groove.
- 2. manufacture method according to claim 1, it is characterised in that the 3rd fin structure and the second fin knot Structure is connected.
- 3. manufacture method according to claim 1, it is characterised in that be also formed with least in the pull-down transistor area One the 4th fin structure.
- 4. manufacture method according to claim 3, it is characterised in that the first grid groove is in the 4th fin knot 4th fin structure described in exposed portion on the bearing of trend of structure.
- 5. manufacture method according to claim 1, it is characterised in that before first P-type workfunction layer is formed, also Comprise the following steps：High k dielectric layer is formed on the bottom and side wall of the first grid groove and the second grid groove, And the step of being made annealing treatment to the high k dielectric layer.
- 6. manufacture method according to claim 1, it is characterised in that after second P-type workfunction layer is formed, shape Into before the 3rd work-function layer, second p-type to pull up transistor in area and pull-down transistor area is additionally included in The step of the first barrier layer is formed in work-function layer.
- 7. manufacture method according to claim 1, it is characterised in that first P-type workfunction layer and second p-type Work-function layer, the material of the 3rd p-type work function include TiN.
- 8. manufacture method according to claim 1, it is characterised in that the material of the N-type workfunction layer include TiAl or One kind or combinations thereof in person TiAlC.
- 9. manufacture method according to claim 1, it is characterised in that after the N-type workfunction layer is formed, in addition to Following steps：The second barrier layer is formed on the N-type workfunction layer；Metal gate electrode layer is filled in the first grid groove and the second grid groove.
- 10. manufacture method according to claim 9, it is characterised in that the step of forming the metal gate electrode layer includes：Deposition forms metal material on the semiconductor substrate, and carries out cmp to the metal material, with shape Into the metal gate electrode layer, wherein, the top surface of the metal gate electrode layer and the first grid groove and the second gate Flushed at the top of the groove of pole.
- 11. manufacture method according to claim 1, it is characterised in that forming the first grid groove and described the Before two gate recess, half on the outside of first fin structure, second fin structure and the 3rd fin structure Isolation structure is also formed with conductor substrate, the top surface of the isolation structure is less than the first fin structure, the second fin knot The top surface of structure and the 3rd fin structure.
- 12. manufacture method according to claim 5, it is characterised in that before the high k dielectric layer is formed, in addition to The step of boundary layer being formed in the bottom of the first grid groove and the second grid groove.
- A kind of 13. semiconductor devices, it is characterised in that including：Semiconductor substrate, the Semiconductor substrate include pull up transistor area, pull-down transistor area and transmission gate transistor area, Formed respectively in pull up transistor area, pull-down transistor area and the transmission gate transistor area in the Semiconductor substrate There are the first fin structure, the second fin structure and the 3rd fin structure；First metal gate stack structure, is formed at the area and across first fin structure of pulling up transistor, including from The first P-type workfunction layer, the second P-type workfunction layer and the N-type workfunction layer stacked gradually on down；Second metal gate stack structure, it is formed in the pull-down transistor area, and across the second fin structure and described One metal gate stack structure is connected, its second P-type workfunction layer for including stacking gradually from bottom to top, described 3rd P-type workfunction layer and the N-type workfunction layer；3rd metal gate stack structure, it is formed in the transmission gate transistor area, across the 3rd fin structure, it is wrapped Include the 3rd P-type workfunction layer stacked gradually from bottom to top and the N-type workfunction layer.
- 14. semiconductor devices according to claim 13, it is characterised in that the 3rd fin structure and second fin Chip architecture is connected.
- 15. semiconductor devices according to claim 13, it is characterised in that be also formed with the pull-down transistor area At least one the 4th fin structure.
- 16. semiconductor devices according to claim 15, it is characterised in that the second metal gate stack structure across 4th fin structure.
- 17. semiconductor devices according to claim 13, it is characterised in that in the 2nd P to pull up transistor in area Second P-type workfunction layer between type work-function layer and N-type workfunction layer and in the pull-down transistor area and described 3rd P-type workfunction layer is additionally provided with the first barrier layer.
- 18. semiconductor devices according to claim 13, it is characterised in that formed with the N-type workfunction layer Two barrier layers, formed with metal gate electrode layer on second barrier layer.
- 19. semiconductor devices according to claim 13, it is characterised in that in first fin structure, described second Isolation structure, the top of the isolation structure are also formed with Semiconductor substrate on the outside of fin structure and the 3rd fin structure Face is less than the top surface of the first fin structure, second fin structure and the 3rd fin structure.
- 20. a kind of electronic installation, it is characterised in that including the semiconductor devices as described in any one of claim 13 to 19.
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| CN108615759A (en) * | 2018-04-13 | 2018-10-02 | 上海华力集成电路制造有限公司 | PMOS with HKMG |
| CN110571195A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | SRAM (static random Access memory), manufacturing method thereof and electronic device |
| TWI693698B (en) * | 2018-03-22 | 2020-05-11 | 美商超捷公司 | Two transistor finfet-based split gate non-volatile floating gate flash memory and method of fabrication |
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| CN108615759A (en) * | 2018-04-13 | 2018-10-02 | 上海华力集成电路制造有限公司 | PMOS with HKMG |
| CN110571195A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | SRAM (static random Access memory), manufacturing method thereof and electronic device |
| CN110571195B (en) * | 2018-06-05 | 2021-12-21 | 中芯国际集成电路制造(上海)有限公司 | SRAM (static random Access memory), manufacturing method thereof and electronic device |
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