CN107785376A - 3d交叉条非易失性存储器 - Google Patents
3d交叉条非易失性存储器 Download PDFInfo
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- CN107785376A CN107785376A CN201710612853.4A CN201710612853A CN107785376A CN 107785376 A CN107785376 A CN 107785376A CN 201710612853 A CN201710612853 A CN 201710612853A CN 107785376 A CN107785376 A CN 107785376A
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- layer
- transistor
- crystal semiconductor
- doped crystal
- semiconductor layer
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Classifications
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Abstract
介绍了用于非易失性存储器阵列的晶体无结型晶体管的半导体结构和方法。根据本公开的各个实施例提供了一种制造具有低热预算的单片3D交叉条非易失性存储器阵列的方法。该方法通过从晶种晶圆转移掺杂的晶体半导体材料的层以形成无结型晶体管的源极、漏极、和连接沟道来将晶体无结型晶体管并入非易失性存储器结构。本发明实施例涉及3D交叉条非易失性存储器。
Description
技术领域
本发明实施例涉及3D交叉条非易失性存储器。
背景技术
非易失性存储器通常用于各种器件,诸如计算机。非易失性存储器是即使当其未接通电源时能够保留数据的一类内存存储器。非易失性存储器可以被电寻址。电寻址非易失性存储器的实例包括闪速存储器、电可编程只读存储器(EPROM)、以及电可擦除可编程只读存储器(EEPROM)。非易失性存储器的功能包括将信息编入其中,从其中读取信息,和/或具有从其中擦除信息。
非易失性存储电路通常包括电组件,诸如,例如,二极管、电容器、和电阻器,它们中的每个可以与晶体管结合以形成电路。
发明内容
根据本发明的一些实施例,提供了一种形成非易失性存储器单元的阵列的方法,包括:提供衬底,所述衬底具有上部介电层和设置在所述上部介电层下方的多个晶体管;在所述晶体管之上形成多层互连件;形成掺杂的晶体半导体层;在所述上部介电层上方设置所述掺杂的晶体半导体层;蚀刻所述掺杂的晶体半导体层以形成相对于所述衬底表面水平取向的多条纳米线;在所述多条纳米线上形成电荷捕获堆叠层;在所述电荷捕获堆叠层上形成多个栅电极;在所述多条纳米线的第一纳米线和所述多个晶体管的第一晶体管之间形成第一互连件;以及在所述多个栅电极的第一栅电极和所述多个晶体管的第二晶体管之间形成第二互连件;其中,所述衬底是块状晶圆。
根据本发明的另一些实施例,提供了一种形成基于无结型场效应晶体管(JLFET)的非易失性存储器的方法,包括:提供衬底,所述衬底具有第一介电层和设置在所述第一介电层下方的多个晶体管;在所述晶体管之上形成多层互连件;在所述第一介电层上设置掺杂的晶体半导体层;蚀刻所述掺杂的晶体半导体层以在所述第一介电层上形成多个掺杂的晶体半导体结构;在所述多个掺杂的晶体半导体结构的每一个上形成多个栅极结构;在所述多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和所述多个晶体管的第一晶体管之间形成第一导电互连件;以及在所述多个栅极结构的第一栅极结构和所述多个晶体管的第二晶体管之间形成第二导电互连件;其中,所述多个栅极结构的每个栅极结构包括栅电极。
根据本发明的又一些实施例,还提供了一种基于无结型场效应晶体管(JLFET)的非易失性存储器结构,包括:衬底,具有第一介电层和设置在所述第一介电层下方的多个晶体管;多层互连件,位于所述晶体管之上;多个掺杂的晶体半导体层,位于所述第一介电层上;多个栅极结构,位于所述多个掺杂的晶体半导体结构的每一个上;第一导电互连件,电连接在所述多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和所述多个晶体管的第一晶体管之间;以及第二互连件,电连接在所述多个栅极结构的第一栅极结构和所述多个晶体管的第二晶体管之间。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制。实际上,为了清楚的说明和讨论,各种部件的尺寸可以被任意增大或缩小。
图1是根据一些实施例的无结型晶体管结构的等轴视图。
图2是根据本公开的n型硅无结型晶体管的截面图。
图3是根据一些实施例的p型硅无结型晶体管的截面图。
图4A至图4C示出了根据一些实施例的N型无结型晶体管的示例性操作状态。
图5A至图5C是根据一些实施例的形成n型无结型晶体管的各个制造步骤的截面图。
图5D至图5F是根据一些实施例的形成n型无结型晶体管的各个制造步骤的等轴视图。
图6是根据一些实施例的p型无结型晶体管结构的等轴视图。
图7是根据一些实施例的非易失性存储器阵列的顶视图。
图8A至图8F是根据一些实施例示出的制造3D交叉条非易失性存储器阵列的中间阶段的示例性结构的截面图。
图9是根据一些实施例示出方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。以下描述组件和布置的具体实例以简化本发明。当然,这些仅仅是实例而不旨在限制。例如,在以下描述中,在第二部件上方形成第一部件可以包括第一部件和第二部件直接接触的实施例,并且也可以包括设置在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且,本发明在各个实例中可以重复参考数字和/或字母。该重复其本身并未指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且本文使用的空间相对描述符可以同样地作相应的解释。
如在此使用的缩写“在此使用是指场效应晶体管。FET的一个非常常见类型被称为金属氧化物半导体场效应晶体管(MOSFET)。过去,MOSFET已经是在诸如半导体晶圆的衬底的平坦表面中和上构建的平坦结构。但是半导体制造中的最近进步已经导致垂直结构的使用。
当用于MOSFET的上下文中时,术语“上下文中和“源极和漏极”是指形成FET的四个端子中的两个的源极和漏极结。
当用于无结型FET的上下文中时,术语“上下文中和“源极和漏极”是指根据一些实施例形成无结型FET的三个端子中的两个的源极和漏极端子。
术语“无结型晶体管”是指具有第一S/D端子、第二S/D端子、以及设置在第一S/D端子和第二S/D端子之间的沟道的晶体管架构。无结型晶体管的沟道具有高掺杂浓度并且具有与第一S/D端子和第二S/D端子相同的导电类型。无结型晶体管在此称为“体管在此称为。在一些实施例中,超高掺杂是掺杂浓度大于或等于5×1018原子/立方厘米。当JLFET的第一S/D端子和第二S/D端子以及沟道全部是n型时,JLFET称为n型JLFET。同样地,当JLFET的第一S/D端子和第二S/D端子以及沟道全部是p型时,JLFET称为p型JLFET。JLFET还包括在沟道上方设置的并且通过栅极电介质与沟道分离的栅电极。
表述“晶体层”在此是指单晶材料的层或结构。同样地,表述“外延生长”在此是指单晶材料的层或结构。外延生长材料可以被掺杂或未被掺杂。
如在此使用的术语“垂直”意味着名义上垂直于衬底的表面。
根据本公开的各个实施例,提供了制作具有3D交叉条非易失性存储器的集成电路的方法。根据一些实施例的方法,在相对低的热预算内将晶体JLFET并入3D交叉条非易失性存储器中。具体地,掺杂的晶体半导体材料的层从晶种晶圆转移以形成源极、漏极、并且连接JLFET的沟道。制作3D非易失性存储器的其它方法使用高温退火步骤以在掺杂工艺之后使掺杂的源极和漏极区域结晶。常规的退火工艺要么是在600性存的温度下持续几小时的固相结晶退火,那么是在高温(例如,1,100续几)下持续几纳秒的短退火。这些工艺要求高热预算。使用转移的掺杂的晶体层形成JLFET的一个益处是退火工艺要么可以在转移至衬底上之前的JLFET结构上执行,要么可以通过将掺杂的晶体半导体层直接地并入JLFET结构被消除。
在描述与3D单片交叉条非易失性存储器结构的设计和制造相关的实施例之前,呈现了用于JLFET的实施例操作工艺。
图1示出了根据本公开的JLFET 1的等轴视图。例如纳米线、鳍、纳米带的半导体纳米线结构形成源极104S、漏极104D、以及由栅电极108部分地围绕的沟道(由栅极电介质覆盖并且在图1中不可见)。源极104S和漏极104D是半导体纳米线的不被栅电极108围绕的部分。栅极电介质106设置在栅电极108和沟道之间。因此,沟道由栅电极108和栅极电介质106覆盖,并且在图1中不可见。
在常规的MOSFET中,S/D结与栅极结构自对准。以相似的方式,JLFET的S/D端子与JLFET的栅极结构自对准。
图2示出了n型JLFET的实施例。从n型晶体硅半导体材料图案化第一源极/漏极端子204S、沟道204C和第二源极/漏极端子204D。栅电极208是p掺杂的多晶硅。栅极电介质206设置在栅电极208和沟道204C之间。
图3示出了p型JLFET的实施例。从p型晶体硅半导体材料图案化第一源极/漏极端子304S、沟道304C和第二源极/漏极端子304D。栅电极308是n型多晶硅。栅极电介质306设置在栅电极308和沟道304C之间。
图4A至图4C是根据一些实施例示出的n型JLFET的样本(sample)操作的若干图。具有各种栅极电压VG(A)<VG(B)<VG(C)的器件(n型器件的实例)的操作如下:
如图4A所示,对于低栅极电压,例如,0V,栅电极208下方的沟道区域204C耗尽载体并且没有电流能够在源极204S和漏极204D之间流动。器件实际上处于断开状态。
如图4B中所示,对于更高栅极电压,例如,0.4V,栅电极208下方的沟道区域204C部分地耗尽载体,并且一些电流能够在源极204S和漏极204D之间流动。
如图4C中所示,对于仍然更高栅极电压,例如,1V,栅电极208下方的区域不再耗尽载体,并且能够在源极204S和漏极204D之间流动。该器件处于导通状态。
应该理解,如果通过增加栅极下方区域中的电子浓度,栅极电压增加超过VG(C),电流可能进一步增加。
图5A至图5F提供了制造的各个阶段期间的包括JLFET的半导体器件的各个图。此处提供的制造工艺是示例性的,并且可以执行在这些附图中未示出的许多其他步骤。
如图5A中所示,制造工艺开始于晶种晶圆500和器件晶圆510。晶圆500包括第一衬底502和晶体半导体层504'。晶圆500也可以包括其他合适的层,诸如其他介电层或注入层。其它合适的层可以放置在第一衬底502和晶体半导体层504'之间,或嵌在第一衬底502内。第一衬底502用作用于机械地支撑晶体半导体层504'的晶种晶圆,并且可以包括任何合适的材料,例如,硅。在一些实施例中,晶体半导体层504'是硅基材料。例如,晶体半导体层504'包括晶体硅并且可以具有各个不同的晶体取向,例如,具有(100)、(110)、或(111)晶体取向。在一个实施例中,晶体半导体层504'通过外延生长工艺直接形成在第一衬底502上方。例如,晶体半导体层504'可以是外延生长的硅或硅锗。在另一实施例中,通过固相外延(SPE)再生长方法获得晶体半导体层504'的晶体结构。在另一实施例中,通过离子注入和退火、或任何其它掺杂技术获得晶体半导体层504'的晶体结构。晶体半导体层504'的顶面可以由诸如二氧化硅层的氧化物层(未在附图中示出)覆盖。
在一个实施例中,晶体半导体层504'是掺杂的半导体层。晶体半导体层504'可以是掺杂有磷(Si:P)或掺杂有磷和碳两者(Si:CP)的n型掺杂硅层。碳可以阻碍磷从硅基材料向外扩散。在一些实施例中,晶体半导体层504'可以是掺杂有砷的n型掺杂的硅层。也可以包括其它类型的掺杂剂。在一些实施例中,磷掺杂剂浓度在从约5×1018原子/立方厘米至约5×1019原子/立方厘米的范围内。在一些实施例中,碳掺杂剂浓度在从约0%至约5%(原子百分比)的范围内。晶体半导体层504'也可以是p型重掺杂的硅层。例如,晶体半导体层504'可以重掺杂有硼。也可以包括用于形成p型掺杂的硅层的其它类型的掺杂剂,例如,锗或铟。离子注入已经用作用于许多技术节点的掺杂工艺。根据本公开的实施例不限于如用作晶体半导体层504'的掺杂工艺的离子注入。可以随后对掺杂工艺执行退火工艺。
器件晶圆510包括第二衬底512和隔离层514。第二衬底512可以是硅衬底。可选地,第二衬底512可以包括另一元素半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。第二衬底512也可以是n型或p型掺杂的硅层。第二衬底可以是包含,例如,配置为CMOS电路的多个晶体管的处理的集成电路晶圆。这些电路可以包括由各种晶体管、电容器、电阻器和互连件制成的逻辑、模拟、RF(射频)部件。隔离层514可以是层间介电(ILD)层/金属间介电(IMD)层。隔离层514包括,例如,可以通过本领域已知的任何合适方法(诸如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD))形成的介电材料,诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的组合物、它们的组合等。还应该注意,隔离层514可以包括嵌入有诸如铜互连件以及钨、钴或氮化钛通孔的金属互连件的多个介电层。
器件晶圆510还可以包括逻辑电路、CMOS电路、模数转换器、数据处理电路、存储电路、偏置电路、参考电路等。
图5B示出了实施接合工艺以接合晶种晶圆500和器件晶圆510的接合工艺。通过来自晶种晶圆500的晶体半导体层504'和来自器件晶圆510的隔离层514彼此相对,使用,例如,诸如电介质与电介质接合(例如,氧化物与氧化物接合)、金属与电介质接合(例如,氧化物与铜接合)、它们的任何组合等的直接接合工艺接合晶种晶圆500和器件晶圆510。在晶种晶圆500的顶面(即,晶体半导体层504'的表面)至器件晶圆510的顶面(即,隔离层514的表面)之间发生接合。在接合之前,将被接合的晶圆的表面被清洗以从晶圆表面去除任何剩余液体或颗粒。接合工艺形成晶圆组件520。
接合可以为晶圆级,其中,晶种晶圆500和器件晶圆510接合在一起,并且然后被分离。可选地,可以在管芯与管芯级或管芯与晶圆级执行接合。
参照图5C,执行薄化工艺以从晶圆组件520去除第一衬底502。通过使用诸如研磨和化学机械抛光(CMP)的合适的技术实现薄化工艺。除了薄化工艺,还要求接合和分离工艺。薄化工艺的结果,第一衬底502被去除或分离并且晶体半导体层504'被暴露。
进一步处理晶体半导体层504'以形成纳米线、鳍、或纳米带(本文中称为“纳米线”)504。纳米线504用作JLFET的源极/漏极和沟道区域。纳米线使用包括但不限于形成和图案化光刻胶层,蚀刻暴露部分以及剥离图案化的光刻胶的已知工艺操作从晶体半导体层504'光刻图案化。尽管,图5C显示具有矩形截面区域的纳米线504,但是纳米线504可以形成为任何合适的形状。
参照图5D至图5F,显示了由制作n型JLFET的实施例工艺导致的各种中间结构的等轴视图。可以使用前述晶圆组件520制造n型JLFET。在示例性实施例中,纳米线504是掺杂的n型晶体硅材料,隔离层514包括嵌入有铜互连件的ILD层,并且第二衬底512包括掺杂的p型硅材料。第二衬底512和隔离层514可以包括逻辑电路、CMOS电路、模数转换器、数据处理电路、存储器电路、存储器控制电路、偏置电路、参考电路等。在一些实施例中,晶圆组件520包括在纳米线504和隔离层514之间的界面处设置的绝缘体层(在图5D至图5F中未示出)。
在图5E中,在纳米线504的至少一部分周围形成栅极介电层206'。在一个实施例中,在纳米线504和隔离层514的暴露表面上初始地沉积栅极介电层206'。对于电荷捕获非易失性存储器阵列,栅极介电层206'是诸如但不限于氧化物-氮化物-氧化物(ONO)的材料的堆叠件。ONO堆叠件在硅表面上方是可靠的,并且通常用作电容器绝缘体。可以通过热氧化硅表面以形成超薄底部氧化物层、沉积LPCVD氮化硅层、以及氧化氮化硅层以形成顶部氧化物层来形成ONO堆叠件。诸如NO、Ta2O5、TiO2、锆钛酸铅(PZT)、或锶钡(BST)的其它材料可以用作栅极介电层206'。
如图5F中所示,在栅极介电层206'的一部分周围形成一个或多个栅电极208以形成n型JLFET。栅极介电层206'的与栅电极208接触的部分形成多个栅极电介质206,多个栅极电介质206因为被栅电极208覆盖所以在图6中不可见的。栅极电介质206和栅电极208一起组成栅极区域,栅极区域被配置为控制连接源极/漏极区域的沟道区域的导电性。栅电极208可以由任何合适的金属或导电材料形成,例如,TiN、Pt、Ni、硅化物、掺杂的p型硅材料、或其他材料/它们的组合。可以使用光刻-蚀刻先栅极工艺或镶嵌工艺形成栅电极208。在一个实施例中,可以进一步处理栅极介电层206'以仅保留栅电极208下方的部分,从而暴露源极/漏极区域,以用于进一步的处理。因此,n型JLFET包括源极/漏极区域、沟道区域、以及包括栅极电介质206和栅电极208的栅极区域。图5F示出了串联连接的多个JLFET,其中,多个JLFET中的每个具有一对S/D端子。
在图6中,使用如关于图5A至图5F描述的相似工艺形成p型JLFET。在该示例性实施例中,纳米线504重掺杂有p型掺杂剂,诸如硼、镓或铟。第二衬底512也可以是掺杂有n型、p型、或H型掺杂剂的硅层。第二衬底512还可以是未掺杂的硅层。另外,第二衬底512可以是包含例如,CMOS电路的处理的集成电路晶圆。这些电路可以包括由各种晶体管、电容器、电阻器和互连件制成的逻辑、模拟、RF(射频)部件。因此,p型JLFET可以包括源极/漏极区域、沟道区域、以及具有栅极电介质306和栅电极308的栅极区域。因为栅极电介质306由栅电极308覆盖,因此仅有栅极介电层306'在图6中是可见的。
以上关于图1至图6描述的JLFET可以用于形成各种结构,诸如但不限于,下面关于图7至图8F描述的3D非易失性存储器阵列。
图7示出了包括JLFET的非易失性电荷捕获存储器阵列700的顶视图。在该示例性实施例中,纳米线504和电极108分别用作位线和字线以形成具有交叉条架构的非易失性存储器阵列。结果,非易失性存储器700的存储器单元位于字线和位线的交点处,从而允许单元单独地寻址。栅极电介质106(未在图7中示出)也形成在每个JLFET处。栅极电介质106可以是诸如氧化物-氮化物-氧化物(ONO)的材料的合适的电荷捕获堆叠件。非易失性存储器阵列700可以形成在如下面更详细地论述的器件晶圆510(未在图7中示出)上。
图8A描述了在转移晶体半导体层504'之前沿图7的切线702截取的一个实施例器件晶圆510的截面图。如上面参照图5A所述的,器件晶圆510可以包括在其中和/或其上形成的一个或多个器件或部件。诸如一个或多个器件或部件的一个实例在图8A中示出,其包括在第二衬底512和隔离层514中形成的金属互连件803和晶体管805。可能具有嵌入有互连件803和晶体管805的多个隔离层514'。诸如铜通孔的金属互连件803为器件晶圆510的各个部分提供电连接。在示例性实施例中,隔离层514可以是嵌入有铜通孔的ILD层。
图8B是沿图7的切口702截取的截面图,其示出了具有在顶面上形成的转移的晶体半导体层504'的器件晶圆510。如上面参照图5A至图5C描述的,晶体半导体层504'可以通过合适的晶圆接合方法从晶种晶圆500转移。例如,直接接合工艺、金属与电介质接合工艺、它们的任何组合等。在转移工艺之前,晶体半导体层504'掺杂有期望的掺杂剂类型和浓度以制作n型或p型JLFET。
图8C示出了已经被进一步处理以形成纳米线504的晶体半导体层504'。如图8C中所示,在隔离层514上方形成多条纳米线504。纳米线504用作JLFET的源极、漏极和沟道区域。使用包括光刻和蚀刻工艺的合适的工艺从晶体半导体层504'图案化纳米线504。多条纳米线504用作3D非易失性存储器阵列700的位线。
在图8D中,与上面参照图5F描述的工艺相似,包括栅极电介质106(未示出)和栅电极108的栅极区域形成在多条纳米线504上方。如图7和图8D中所示,每个栅电极108可以用于控制对应的JLFET。在该示例性实施例中,每个JLFET用作非易失性存储器单元。第二隔离层804被示出形成在多个JLFET上方。在另外的实施例中,第二隔离层804提供了用于堆叠附加的存储器阵列的表面。类似于隔离层514,第二隔离层804可以是通过诸如旋涂、CVD、和PECVD的本领域已知的任何合适的方法由低k介电材料形成的ILD层。第二隔离层804可以类似地包括嵌入有金属互连件的多个介电层。
在图8E中,在隔离层514和第二隔离层804中形成连接栅电极108和金属互连件803的字线互连件803W,从而提供了器件晶圆510中非易失性存储器阵列700和晶体管805之间的垂直的电互连。该3D交叉条架构创建了具有比2.5千兆比特/平方毫米更高存储密度和更小器件覆盖区的结构。字线互连件803W可以是诸如导电通孔或导线的金属互连件,并且也可以是多层互连件(MLI),包括诸如传统的通孔或接触件的垂直和水平互连件,和诸如金属线的水平互连件。MLI结构可以包括导线、导电通孔、和/或插接介电层(例如,层间电介质(ILD))。MLI结构还提供至晶体管以及在晶体管之间的电连接。各个层级中的导电线可以包括铜、铝、钨、钽、钛、镍、钴、金属硅化物、金属氮化物、多晶硅、它们的组合、和/或可能包括一层或多层或衬垫的其它材料。衬垫包括粘合层、阻挡层、蚀刻停止层、以及抗反射涂层。插接介电层或层间介电层(例如,ILD层)可以包括二氧化硅、掺氟硅玻璃(FSG)、或至少一个低k介电材料。MLI可以通过通常在CMOS制造中合适的工艺形成,诸如但不限于,CVD、PVD、ALD、镀敷、旋涂、和/或其它工艺。在一个实例中,使用镶嵌工艺以形成铜多层互连结构。在示例性镶嵌工艺中,在介电层中形成开口,开口分离垂直间隔的金属层。通常地,使用传统的光刻和蚀刻技术形成开口。形成之后,开口填充有氮化钛、钨或其它金属、金属合金、或金属和/或金属合金的堆叠件以形成通孔。然后通过化学机械抛光(CMP)去除介电层的表面上的过量的金属材料。铜或导电材料形成连接至通孔的互连线。
图8F是在形成位线互连件803B之后沿图7的切线704截取的示例性非易失性存储器阵列700和器件晶圆510的截面图。位线互连件803B还提供了器件晶圆510中的非易失性存储器阵列700和晶体管805之间的垂直电连接。位线互连件803B还可以是金属互连件,诸如但不限于钨通孔或导线。位线互连件803B的各个层可以用于连接上述的各种部件。位线互连件803B还可以是多层互连件,包括诸如传统的通孔或接触件的垂直和水平互连件,和诸如金属线的水平互连件。在一个实例中,使用镶嵌工艺以形成基于铜的多层互连结构。
图9是使用晶体JLFET形成3D交叉条非易失性存储器阵列的说明性方法900的流程图。可以在方法900的各个操作之间执行其他操作。
方法900开始于操作902,提供了具有形成在其中或其上的一种或多种器件或部件的衬底。该衬底可以包括多个层,例如,ILD层、介电层、或注入层,并且可以具有嵌在其中的器件或电连接件。在一些实施例中,衬底是具有形成在其中或其上的一个或多个器件或部件的块状Si晶圆。
方法900继续进行操作904,将半导体层转移至衬底,其中半导体层是掺杂的晶体半导体层。晶体半导体层可以是晶种晶圆的一部分或附接至晶种层。在转移工艺之前,晶体半导体层掺杂有适用于n型或p型JLFET的期望的掺杂剂类型和浓度。转移工艺可以开始于将半导体层接合至衬底。可以使用直接接合工艺、金属与电介质接合工艺、和它们的任何组合等。如果半导体层附接至晶种层或是晶种晶圆的一部分,转移工艺可以继续进行去除晶种层或晶种晶圆的剩余部分。可通过使用诸如研磨、化学机械抛光(CMP)、Smart CutTM工序、ELTRANC工序和/或化学蚀刻的合适的技术实现去除工艺。薄化工艺的结果,晶种层或晶种晶圆的剩余部分被去除以及晶体半导体层被转移至衬底并且被暴露以用于后续处理。
方法900继续进行操作906,从掺杂的晶体半导体层形成纳米线。纳米线随后被用作JLFET的源极/漏极端子和沟道区域。可以使用包括光刻和蚀刻工艺的合适的工艺从晶体半导体层制造纳米线。纳米线可以被图案化为任何合适的形状。
方法900继续进行操作908,在纳米线的部分周围形成栅极介电层和栅电极。栅极电介质可以包括高k介电材料、氧化物-氮化物-氧化物(ONO)堆叠件的材料、或其它合适的材料,并且可以通过ALD、PECVD、和/或其它合适的沉积工艺形成。在栅极电介质的一部分上方形成栅电极。栅电极和栅极电介质一起组成栅极区域,栅极区域被配置为控制沟道区域的导电性。栅电极可以包括任何合适的导电材料并且可以使用光刻-蚀刻先栅极工艺或镶嵌工艺形成。晶体纳米线和栅电极分别用作位线和字线以形成具有交叉条架构的非易失性电荷捕获存储器阵列。结果,非易失性存储器阵列的存储器单元位于字线和位线的交点处,从而允许单元单独地寻址。
方法900继续进行操作910,形成为非易失性存储器阵列提供电连接的互连件。互连件包括位线互连件和字线互连件,并且形成在ILD层或衬底中以在非易失性存储器阵列和其它电路和电源之间提供电连接。该3D交叉条架构创建了具有比2.5千兆比特/平方毫米更高存储密度和更小覆盖区的结构。位线和字线互连件可以是金属互连件,诸如通孔或导线。
根据本公开的实施例的一个益处是创建JLFET而不需要热处理。上述的所有操作,包括接合晶种层500,去除第一衬底502,蚀刻,形成源极/漏极和沟道区域,以及形成栅极电介质106和栅电极108,均在低温下执行,这不会对器件晶圆510或形成的晶圆组件520造成损坏。在一个实施例中,所有处理步骤在小于600℃的温度下执行。这样的低温处理使这样的器件的若干层的堆叠成为可能,包括低温处理的每个层的添加不会对之前形成的器件层造成损坏。
根据本公开的实施例的另一益处是在接合和转移工艺之前可以执行其他工艺,这些工艺要求加热并且对形成掺杂的晶体半导体层504'可能是必要的,其他工艺诸如结晶、离子注入或退火。这防止在下面的层中形成的器件(例如,在器件晶圆510中形成的一个或多个器件或部件)受到用于制造具有晶体源极、漏极、和沟道区域的JLFET中的处理温度的损坏。
在一个实施例中,一种形成非易失性存储器单元的阵列的方法提供了具有上部介电层和在上部介电层下方形成的多个晶体管的衬底。在晶体管之上形成多层互连件。衬底可以是块状晶圆。掺杂的晶体半导体层设置在上部介电层上方并且被蚀刻以形成相对于衬底表面水平取向的多条纳米线。在多条纳米线上形成电荷捕获堆叠层。在电荷捕获堆叠层上形成多个栅电极。在多条纳米线的第一纳米线和多个晶体管的第一晶体管之间形成第一互连件。在多个栅极结构的第一栅极结构和多个晶体管的第二晶体管之间形成第二互连件。
在另一实施例中,一种形成基于JLFET的非易失性存储器的方法提供了具有第一介电层和在第一介电层下方形成的多个晶体管的衬底。在晶体管之上形成多层互连件。掺杂的晶体半导体层设置在第一介电层上并且被蚀刻以在第一介电层上形成多个掺杂的晶体半导体结构。在多个掺杂的晶体半导体结构的每一个上形成多个栅极结构。在多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和多个晶体管的第一晶体管之间形成第一导电互连件。在多个栅极结构的第一栅极结构和多个晶体管的第二晶体管之间形成第二导电互连件。多个栅极结构的每个栅极结构包括栅电极。
在另外的实施例中,基于JLFET的非易失性存储器结构包括具有第一介电层、设置在第一介电层下方的多个晶体管、以及位于第一介电层上的多个掺杂的晶体半导体结构的衬底。基于JLFET的非易失性存储器结构还包括位于晶体管之上的多层互连件和在多个掺杂的晶体半导体结构的每一个上的多个栅极结构。该结构还包括在多个掺杂的晶体半导体结构中的第一个和多个晶体管中的第一晶体管之间电连接的第一互连件,以及在多个栅极结构中的第一栅极结构和在多个晶体管中的第二晶体管之间电连接的第二互连件。
应该理解,详细的描述部分,并不是本公开部分的概述或摘要,旨在用于解释权利要求。公开部分的概述和摘要可以陈述设想的示例性实施例中的一个或多个但不是全部,并且因此,不旨在限于附加的权利要求。
根据本发明的一些实施例,提供了一种形成非易失性存储器单元的阵列的方法,包括:提供衬底,所述衬底具有上部介电层和设置在所述上部介电层下方的多个晶体管;在所述晶体管之上形成多层互连件;形成掺杂的晶体半导体层;在所述上部介电层上方设置所述掺杂的晶体半导体层;蚀刻所述掺杂的晶体半导体层以形成相对于所述衬底表面水平取向的多条纳米线;在所述多条纳米线上形成电荷捕获堆叠层;在所述电荷捕获堆叠层上形成多个栅电极;在所述多条纳米线的第一纳米线和所述多个晶体管的第一晶体管之间形成第一互连件;以及在所述多个栅电极的第一栅电极和所述多个晶体管的第二晶体管之间形成第二互连件;其中,所述衬底是块状晶圆。
在上述方法中,形成所述掺杂的晶体半导体层包括外延生长半导体层。
在上述方法中,还包括:在所述上部介电层上方设置所述掺杂的晶体半导体层之前,向半导体层中注入至少一种掺杂剂物质以形成所述掺杂的晶体半导体层。
在上述方法中,所述掺杂的晶体半导体层被n型掺杂至具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度。
在上述方法中,所述掺杂的晶体半导体层被p型掺杂至具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度。
在上述方法中,外延生长所述半导体层包括外延生长硅。
在上述方法中,外延生长所述半导体层包括外延生长硅锗。
在上述方法中,形成所述第一互连件包括穿过所述上部介电层蚀刻第一开口,并且形成所述第二互连件包括穿过所述上部介电层蚀刻第二开口。
在上述方法中,形成所述电荷捕获堆叠层包括:在所述多条纳米线中的每条纳米线上沉积第一氧化物层;在所述第一氧化物层上沉积氮化物层;以及在所述氮化物层上沉积第二氧化物层。
在上述方法中,所述多个栅电极被布置成相对于所述衬底表面水平取向并且相对于所述多条纳米线垂直取向的多个行。
根据本发明的另一些实施例,提供了一种形成基于无结型场效应晶体管(JLFET)的非易失性存储器的方法,包括:提供衬底,所述衬底具有第一介电层和设置在所述第一介电层下方的多个晶体管;在所述晶体管之上形成多层互连件;在所述第一介电层上设置掺杂的晶体半导体层;蚀刻所述掺杂的晶体半导体层以在所述第一介电层上形成多个掺杂的晶体半导体结构;在所述多个掺杂的晶体半导体结构的每一个上形成多个栅极结构;在所述多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和所述多个晶体管的第一晶体管之间形成第一导电互连件;以及在所述多个栅极结构的第一栅极结构和所述多个晶体管的第二晶体管之间形成第二导电互连件;其中,所述多个栅极结构的每个栅极结构包括栅电极。
在上述方法中,所述掺杂的晶体半导体层被n型掺杂至具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度。
在上述方法中,所述掺杂的晶体半导体层被p型掺杂至具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度。
在上述方法中,形成所述多个栅极结构包括在所述多个掺杂的晶体半导体层上方沉积氧化物-氮化物-氧化物电荷捕获堆叠件。
在上述方法中,形成所述多个栅极结构还包括:沉积栅电极层;以及图案化所述栅电极层。
根据本发明的又一些实施例,还提供了一种基于无结型场效应晶体管(JLFET)的非易失性存储器结构,包括:衬底,具有第一介电层和设置在所述第一介电层下方的多个晶体管;多层互连件,位于所述晶体管之上;多个掺杂的晶体半导体层,位于所述第一介电层上;多个栅极结构,位于所述多个掺杂的晶体半导体结构的每一个上;第一导电互连件,电连接在所述多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和所述多个晶体管的第一晶体管之间;以及第二互连件,电连接在所述多个栅极结构的第一栅极结构和所述多个晶体管的第二晶体管之间。
在上述基于无结型场效应晶体管的非易失性存储器结构中,所述多个掺杂的晶体半导体结构是具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度的n掺杂的晶体硅。
在上述基于无结型场效应晶体管的非易失性存储器结构中,所述多个掺杂的晶体半导体结构是具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度的p掺杂的晶体硅。
在上述基于无结型场效应晶体管的非易失性存储器结构中,所述多个栅极结构的第一栅极结构包括电荷捕获栅极介电堆叠件,并且还包括位于所述电荷捕获栅极介电堆叠件上的导电栅电极。
在上述基于无结型场效应晶体管的非易失性存储器结构中,所述多个掺杂的晶体半导体结构布置成多列并且所述多个栅极结构布置成多行。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成非易失性存储器单元的阵列的方法,包括:
提供衬底,所述衬底具有上部介电层和设置在所述上部介电层下方的多个晶体管;
在所述晶体管之上形成多层互连件;
形成掺杂的晶体半导体层;
在所述上部介电层上方设置所述掺杂的晶体半导体层;
蚀刻所述掺杂的晶体半导体层以形成相对于所述衬底表面水平取向的多条纳米线;
在所述多条纳米线上形成电荷捕获堆叠层;
在所述电荷捕获堆叠层上形成多个栅电极;
在所述多条纳米线的第一纳米线和所述多个晶体管的第一晶体管之间形成第一互连件;以及
在所述多个栅电极的第一栅电极和所述多个晶体管的第二晶体管之间形成第二互连件;
其中,所述衬底是块状晶圆。
2.根据权利要求1所述的方法,其中,形成所述掺杂的晶体半导体层包括外延生长半导体层。
3.根据权利要求1所述的方法,还包括:在所述上部介电层上方设置所述掺杂的晶体半导体层之前,向半导体层中注入至少一种掺杂剂物质以形成所述掺杂的晶体半导体层。
4.根据权利要求1所述的方法,其中,所述掺杂的晶体半导体层被n型掺杂至具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度。
5.根据权利要求1所述的方法,其中,所述掺杂的晶体半导体层被p型掺杂至具有在5×1018原子/立方厘米至5×1019原子/立方厘米的范围内的掺杂浓度。
6.根据权利要求2所述的方法,其中,外延生长所述半导体层包括外延生长硅。
7.根据权利要求2所述的方法,其中,外延生长所述半导体层包括外延生长硅锗。
8.根据权利要求1所述的方法,其中,形成所述第一互连件包括穿过所述上部介电层蚀刻第一开口,并且形成所述第二互连件包括穿过所述上部介电层蚀刻第二开口。
9.一种形成基于无结型场效应晶体管(JLFET)的非易失性存储器的方法,包括:
提供衬底,所述衬底具有第一介电层和设置在所述第一介电层下方的多个晶体管;
在所述晶体管之上形成多层互连件;
在所述第一介电层上设置掺杂的晶体半导体层;
蚀刻所述掺杂的晶体半导体层以在所述第一介电层上形成多个掺杂的晶体半导体结构;
在所述多个掺杂的晶体半导体结构的每一个上形成多个栅极结构;
在所述多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和所述多个晶体管的第一晶体管之间形成第一导电互连件;以及
在所述多个栅极结构的第一栅极结构和所述多个晶体管的第二晶体管之间形成第二导电互连件;
其中,所述多个栅极结构的每个栅极结构包括栅电极。
10.一种基于无结型场效应晶体管(JLFET)的非易失性存储器结构,包括:
衬底,具有第一介电层和设置在所述第一介电层下方的多个晶体管;
多层互连件,位于所述晶体管之上;
多个掺杂的晶体半导体层,位于所述第一介电层上;
多个栅极结构,位于所述多个掺杂的晶体半导体结构的每一个上;
第一导电互连件,电连接在所述多个掺杂的晶体半导体结构的第一掺杂的晶体半导体结构和所述多个晶体管的第一晶体管之间;以及
第二互连件,电连接在所述多个栅极结构的第一栅极结构和所述多个晶体管的第二晶体管之间。
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CN107785376B (zh) | 2020-06-19 |
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TW201813060A (zh) | 2018-04-01 |
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