CN107768349A - Two-sided SiP three-dimension packagings structure - Google Patents
Two-sided SiP three-dimension packagings structure Download PDFInfo
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- CN107768349A CN107768349A CN201710875230.6A CN201710875230A CN107768349A CN 107768349 A CN107768349 A CN 107768349A CN 201710875230 A CN201710875230 A CN 201710875230A CN 107768349 A CN107768349 A CN 107768349A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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Abstract
The present invention relates to a kind of two-sided SiP three-dimension packagings structure, and it includes core pinboard（1）, the core pinboard（1）Front is pasted with fan-out-type wafer level packaging structure（2）, the first passive device（3）With the first 3D conductive components（4）, the core pinboard（1）The back side is pasted with chip（7）, the second passive device（8）With the 2nd 3D conductive components（6）, the 2nd 3D conductive components（6）The back side is provided with the first soldered ball（10）, the encapsulating structure top surface and side are provided with screen layer（15）, the first 3D conductive components（4）Screen layer at front（15）It is provided with opening（16）.The present invention can use prefabricated 3D conductive components to turn into the supporting construction of stacked package, the earth terminal using 3D conductive components as electromagnetic shielding, can reduce the dimensional height of encapsulation module, improve the high frequency performance of encapsulation module, effectively prevent electromagnetic interference.
Description
Technical field
The present invention relates to a kind of two-sided SiP three-dimension packagings structure, belong to technical field of semiconductor encapsulation.
Background technology
According to the development of semiconductor technology, electronic device becomes miniaturization and increasingly gentlier to meet the needs of user,
Therefore, for realizing that the multi-chip package technology of the semiconductor chip identical or different with single package is strengthened.With partly leading
The encapsulation that body chip is realized is compared, and multi-chip package is favourable, tool for package size or weight and installation process
Say, multi-chip package is mainly used in the mobile terminals for requiring miniaturization and loss of weight body.
But with the high-density line in encapsulation procedure, the use of a variety of encapsulating materials and various chips and work(
The use of energy device so that whole packaging body is very complicated, and the collocation of various materials is not easy to balance, and easily causes overall warpage to become
Shape.
In addition used in electronic product now to electronic circuit component must all possess electromagnetic armouring structure.Its is main
Purposes is to prevent the mutual caused electromagnetic interference phenomenon between various circuit elements from occurring.Among electronic product, only have
Standby outstanding electromagnetic armouring structure is just stabilized and possesses the running of high-reliability, and is trusted and favor by user.
How to prevent electromagnetic interference is also the problem of needing to need to consider in module packaging.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of two-sided SiP three-dimension packagings knot for above-mentioned prior art
Structure, it can use supporting construction of the prefabricated 3D conductive components as stacked package, using 3D conductive components as electromagnetic shielding
Earth terminal, using the combination of wafer-level packaging and other devices in module, the dimensional height of encapsulation module can be reduced, improved
The high frequency performance of encapsulation module, effectively prevents electromagnetic interference.
Technical scheme is used by the present invention solves the above problems：A kind of two-sided SiP three-dimension packagings structure, it includes core
Heart pinboard, the core pinboard front is pasted with fan-out-type wafer level packaging structure and the first passive device, described to be fanned out to
Type wafer level packaging structure and the first passive device periphery are provided with the first 3D conductive components, the fan-out-type wafer-level packaging knot
Structure, the first passive device and the first 3D conductive component outer encapsulatings have the first plastic packaging material, and the first 3D conductive components front is exposed to
One plastic packaging material, core switching back are pasted with chip and the second passive device, outside the chip and the second passive device
Enclose and be provided with the 2nd 3D conductive components, the chip, the second passive device and the 2nd 3D conductive component outer encapsulatings have the second plastic packaging
Material, the 2nd 3D conductive components back side are exposed to the second plastic packaging material, and the 2nd 3D conductive components back side is provided with the first weldering
Ball, the encapsulating structure top surface and side are provided with screen layer, and the screen layer at the first 3D conductive components front is provided with
Opening.
The opening connection outer enclosure body or function element.
The fan-out-type wafer level packaging structure and the first passive device are located in same horizontal line, the chip and second
Passive device is located in same horizontal line, and the fan-out-type wafer level packaging structure and the second passive device are located at same vertical line
On, first passive device and chip are located on same vertical line.
Be provided with first substrate below the encapsulating structure, the encapsulating structure by the first metal ball and first substrate just
Face is connected, and the first substrate back side is provided with the second soldered ball, and bottom is provided between the encapsulating structure and first substrate
Fill glue.
A kind of two-sided SiP three-dimension packagings structure, it includes core pinboard, and the core pinboard front, which is pasted with, to be fanned out to
Type wafer level packaging structure and the first passive device, fan-out-type wafer level packaging structure and the first passive device periphery are set
There is metal coupling, the fan-out-type wafer level packaging structure, the first passive device and metal coupling outer encapsulating have the first plastic packaging material,
Core switching back is pasted with chip and the second passive device, and the chip and the second passive device periphery are provided with the
Two 3D conductive components, the chip, the second passive device and the 2nd 3D conductive component outer encapsulatings have the second plastic packaging material, and described second
The 3D conductive components back side is provided with the first soldered ball, and the encapsulating structure top surface and side are provided with screen layer, the core switching
The line layer of plate is connected with the screen layer of side.
Compared with prior art, the advantage of the invention is that：
1st, the rewiring core pinboard and the internal wafer used made in encapsulation module using wafer scale or panel level
Class encapsulation structure can reduce the height and size of overall package module；
2nd, master chip, other chips（Such as MEMS, control chip, integrated passive devices）It is low using wafer level packaging structure, use
The insulating materials of loss, high frequency performance can be improved；Other wafer level packaging structure individually can make in addition, can test
It is applied to after qualified in this module packaging, it is but unqualified in final test can prevents that multi-chip is separately implantable SiP modules, can be with
Chip loss is reduced, and ensures the high yield of final products；
3rd, the stability of flexibility and the warpage control of the height design of overall package module can be improved：The 3D of top and the bottom is led
Electric part is prefabricated individually designed, can there is the combination of potting resin in all-metal post and metal column, and there is flexible CTE to set
Meter can control integrally-built warpage, and the design of its height can also flexibly be designed；Fan-out-type wafer-level packaging
Angularity can be adjusted by adjusting the thickness of plastic packaging and the height of bump design；
4th, 3D conductive components act not only as stacking or are embedded to the support current-carrying part of encapsulation, can also be as electromagnetic shielding
Earth terminal, electromagnetic interference can be prevented.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of two-sided SiP three-dimension packagings constructive embodiment 1 of the present invention.
Fig. 2 is a kind of schematic diagram of two-sided SiP three-dimension packagings constructive embodiment 2 of the present invention.
Fig. 3 is a kind of schematic diagram of two-sided SiP three-dimension packagings constructive embodiment 3 of the present invention.
Wherein：
Core pinboard 1
Fan-out-type wafer level packaging structure 2
First passive device 3
First 3D conductive components 4
First plastic packaging material 5
2nd 3D conductive components 6
Chip 7
Second passive device 8
Second plastic packaging material 9
First soldered ball 10
First substrate 11
Second soldered ball 12
Underfill 13
Second substrate 14
Screen layer 15
Opening 16
Metal coupling 17.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment 1：
Referring to Fig. 1, the three-dimension packaging structure of two-sided SiP in the present embodiment a kind of, it includes core pinboard 1, the core
The front of pinboard 1 is pasted with the passive device 3 of fan-out-type wafer level packaging structure 2 and first, the fan-out-type wafer-level packaging knot
The periphery of 2 and first passive device of structure 3 is provided with the first 3D conductive components 4, the fan-out-type wafer level packaging structure 2, the first quilt
Dynamic element 3 and the outer encapsulating of the first 3D conductive components 4 have the first plastic packaging material 5, and the front of the first 3D conductive components 4 is exposed to the first plastic packaging
Material 5, the back side of core pinboard 1 are pasted with the passive device 8 of chip 7 and second, outside the passive device 8 of chip 7 and second
Enclose and be provided with the 2nd 3D conductive components 6, the chip 7, the second passive device 8 and the outer encapsulating of the 2nd 3D conductive components 6 have second
Plastic packaging material 9, the back side of the 2nd 3D conductive components 6 are exposed to the second plastic packaging material 9, and the back side of the 2nd 3D conductive components 6 is set
There is the first soldered ball 10, the encapsulating structure top surface and side are provided with screen layer 15, at the front of the first 3D conductive components 4
Screen layer 15 is provided with opening 16；
The opening 16 can connect outer enclosure body or other function elements；
The passive device 3 of fan-out-type wafer level packaging structure 2 and first is located in same horizontal line, the chip 7 and second
Passive device 8 is located in same horizontal line, and the passive device 8 of fan-out-type wafer level packaging structure 2 and second hangs down positioned at same
On straight line, first passive device 3 and chip 7 are located on same vertical line, it is ensured that chip, fan-out-type wafer-level packaging with
And most short signal transmission line between passive device, the loss in transmission line is reduced, ensures the stability of signal transmission.
Embodiment 2：
Referring to Fig. 2, the difference of embodiment 2 and embodiment 1 is：First substrate 11 is provided with below the encapsulating structure, it is described
Encapsulating structure is connected by the first metal ball 10 with the front of first substrate 11, and the back side of first substrate 11 is provided with the second weldering
Ball 12, underfill 13 is provided between the encapsulating structure and first substrate 11.
Embodiment 3：
Fig. 3 is participated in, the three-dimension packaging structure of two-sided SiP in the present embodiment a kind of, it includes core pinboard 1, the core
The front of pinboard 1 is pasted with the passive device 3 of fan-out-type wafer level packaging structure 2 and first, the fan-out-type wafer-level packaging knot
The periphery of 2 and first passive device of structure 3 is provided with metal coupling 17, the fan-out-type wafer level packaging structure 2, the first passive device
3 and the outer encapsulating of metal coupling 17 have the first plastic packaging material 5, the back side of core pinboard 1 is pasted with the passive device of chip 7 and second
8, the periphery of 7 and second passive device of chip 8 is provided with the 2nd 3D conductive components 6, the chip 7, the and of the second passive device 8
The outer encapsulating of 2nd 3D conductive components 6 has the second plastic packaging material 9, and the back side of the 2nd 3D conductive components 6 is provided with the first soldered ball 10, institute
State encapsulating structure top surface and side is provided with screen layer 15, the line layer of the core pinboard 1 and the phase of screen layer 15 of side
Connection.
In addition to the implementation, it is all to use equivalent transformation or equivalent replacement present invention additionally comprises there is other embodiment
The technical scheme that mode is formed, it all should fall within the scope of the hereto appended claims.
Claims (5)
- A kind of 1. two-sided SiP three-dimension packagings structure, it is characterised in that：It includes core pinboard（1）, the core pinboard （1）Front is pasted with fan-out-type wafer level packaging structure（2）With the first passive device（3）, the fan-out-type wafer-level packaging knot Structure（2）With the first passive device（3）Periphery is provided with the first 3D conductive components（4）, the fan-out-type wafer level packaging structure （2）, the first passive device（3）With the first 3D conductive components（4）Outer encapsulating has the first plastic packaging material（5）, the first 3D conductive components（4） Front is exposed to the first plastic packaging material（5）, the core pinboard（1）The back side is pasted with chip（7）With the second passive device（8）, The chip（7）With the second passive device（8）Periphery is provided with the 2nd 3D conductive components（6）, the chip（7）, it is second passive Element（8）With the 2nd 3D conductive components（6）Outer encapsulating has the second plastic packaging material（9）, the 2nd 3D conductive components（6）Expose at the back side In the second plastic packaging material（9）, the 2nd 3D conductive components（6）The back side is provided with the first soldered ball（10）, the encapsulating structure top surface Side is provided with screen layer（15）, the first 3D conductive components（4）Screen layer at front（15）It is provided with opening（16）.
- A kind of 2. two-sided SiP three-dimension packagings structure according to claim 1, it is characterised in that：The opening（16）Connection Outer enclosure body or function element.
- A kind of 3. two-sided SiP three-dimension packagings structure according to claim 1, it is characterised in that：The fan-out-type wafer scale Encapsulating structure（2）With the first passive device（3）In same horizontal line, the chip（7）With the second passive device（8）It is located at In same horizontal line, the fan-out-type wafer level packaging structure（2）With the second passive device（8）On same vertical line, institute State the first passive device（3）And chip（7）On same vertical line.
- A kind of 4. two-sided SiP three-dimension packagings structure according to claim 1, it is characterised in that：Below the encapsulating structure It is provided with first substrate（11）, the encapsulating structure passes through the first metal ball（10）With first substrate（11）Front is connected, institute State first substrate（11）The back side is provided with the second soldered ball（12）, the encapsulating structure and first substrate（11）Between be provided with bottom Fill glue（13）.
- A kind of 5. two-sided SiP three-dimension packagings structure, it is characterised in that：It includes core pinboard（1）, the core pinboard （1）Front is pasted with fan-out-type wafer level packaging structure（2）With the first passive device（3）, the fan-out-type wafer-level packaging knot Structure（2）With the first passive device（3）Periphery is provided with metal coupling（17）, the fan-out-type wafer level packaging structure（2）, first Passive device（3）And metal coupling（17）Outer encapsulating has the first plastic packaging material（5）, the core pinboard（1）The back side is pasted with core Piece（7）With the second passive device（8）, the chip（7）With the second passive device（8）Periphery is provided with the 2nd 3D conductive components （6）, the chip（7）, the second passive device（8）With the 2nd 3D conductive components（6）Outer encapsulating has the second plastic packaging material（9）, it is described 2nd 3D conductive components（6）The back side is provided with the first soldered ball（10）, the encapsulating structure top surface and side are provided with screen layer （15）, the core pinboard（1）Line layer and side screen layer（15）It is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710875230.6A CN107768349B (en) | 2017-09-25 | 2017-09-25 | Two-sided SiP three-dimension packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710875230.6A CN107768349B (en) | 2017-09-25 | 2017-09-25 | Two-sided SiP three-dimension packaging structure |
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| CN107768349A true CN107768349A (en) | 2018-03-06 |
| CN107768349B CN107768349B (en) | 2019-11-01 |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473363A (en) * | 2018-11-12 | 2019-03-15 | 深圳市江波龙电子股份有限公司 | System-in-package structure and production method |
| CN109999343A (en) * | 2019-03-30 | 2019-07-12 | 深圳硅基仿生科技有限公司 | The electronic packing body and retina stimulator of built-in type device |
| WO2020101572A1 (en) * | 2018-11-12 | 2020-05-22 | Agency For Science, Technology And Research | Multi-chip system and method of forming the same |
| CN112259528A (en) * | 2020-09-28 | 2021-01-22 | 立讯电子科技（昆山）有限公司 | SIP structure with double-sided selective electromagnetic shielding package and preparation method thereof |
| CN113066771A (en) * | 2021-03-23 | 2021-07-02 | 浙江集迈科微电子有限公司 | Multilayer stacks microsystem structure |
| CN113140538A (en) * | 2021-04-21 | 2021-07-20 | 上海闻泰信息技术有限公司 | Adapter plate, packaging structure and manufacturing method of adapter plate |
| CN114242685A (en) * | 2021-12-01 | 2022-03-25 | 展讯通信（上海）有限公司 | Double-sided packaging assembly and forming method thereof |
| US11398454B2 (en) | 2019-10-18 | 2022-07-26 | Samsung Electronics Co., Ltd. | System-in-package module |
| WO2023024573A1 (en) * | 2021-08-23 | 2023-03-02 | 荣耀终端有限公司 | Electronic device and chip packaging method |
| US11652064B2 (en) * | 2019-12-06 | 2023-05-16 | Qualcomm Incorporated | Integrated device with electromagnetic shield |
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