CN107767831B - Silicon-based liquid crystal pixel circuit and display device thereof - Google Patents

Silicon-based liquid crystal pixel circuit and display device thereof Download PDF

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Publication number
CN107767831B
CN107767831B CN201711079021.7A CN201711079021A CN107767831B CN 107767831 B CN107767831 B CN 107767831B CN 201711079021 A CN201711079021 A CN 201711079021A CN 107767831 B CN107767831 B CN 107767831B
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latch
switch unit
unit
pixel circuit
input
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CN107767831A (en
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刘帅辰
文鹏
郑宝荣
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Aiyouyou Shenzhen Technology Co ltd
Xiaochun Stereoscopic Technology Co ltd
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Aiyouyou Shenzhen Technology Co ltd
Xiaochun Stereoscopic Technology Co ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention relates to a silicon-based liquid crystal pixel circuit, which comprises a refreshing signal unit, a latch and a switch unit; the refreshing signal unit is connected with the input end of the latch and is used for inputting a refreshing signal to the latch according to a set time sequence; the input end of the latch is respectively connected with the output end of the refreshing signal unit and the output end of the switch unit and is used for receiving and storing the data bit transmitted by the switch unit when the switch unit is switched on; and the switch unit is used for controlling the transmission of the data bit so as to control the storage of the latch, and is switched on when the latch inputs the refresh signal and is switched off after the data bit transmitted by the switch unit is input. According to the silicon-based liquid crystal pixel circuit, the refreshing signal unit places the latch at a potential to enable the switch unit to be switched on and then switched off, the latch stores the potential at two ends, the switch unit is switched off, and when the input voltage is input to the switch unit, the switch unit cannot be switched on, so that error data cannot be written into the pixel circuit during modulation.

Description

Liquid crystal on silicon pixel circuit and display device thereof
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a silicon-based liquid crystal pixel circuit and a display device thereof.
Background
Liquid Crystal On Silicon (LCOS) is a matrix Liquid Crystal display device based On a reflective mode and having a very small size, and has characteristics of high light utilization efficiency, high aperture ratio, low manufacturing cost, and the like. In addition, the resolution of the LCOS can be made very high, which is not comparable to other technologies in the application of portable projection devices, so LCOS is very popular with manufacturers. In recent years, the liquid crystal on silicon mainly adopts a pulse width modulation mode to control the light emitting time length of the liquid crystal so as to achieve the purpose of adjusting reflected light. The selection of a specific pulse width modulation method determines the display effect of the liquid crystal on silicon and the size of the video cache on the chip, and the true single pulse modulation mode can enable the liquid crystal on silicon to achieve a better display effect, but compared with other modes, the video cache used is the most. At present, researchers have developed a pixel circuit that uses only one video buffer to perform true single pulse modulation, and does not need to increase too much blank time for waiting for new data writing, but there are some problems that cannot be overcome by a SRAM (Static Random Access Memory) based pixel circuit.
Disclosure of Invention
In view of the above, it is desirable to provide a liquid crystal on silicon pixel circuit and a display device thereof, which can solve the problem that error data can be written into the pixel circuit.
A liquid crystal on silicon pixel circuit, the pixel circuit comprising: the device comprises a refreshing signal unit, a latch and a switch unit;
the refreshing signal unit is connected with the input end of the latch and is used for inputting refreshing signals to the latch according to a set time sequence;
the input end of the latch is respectively connected with the output end of the refreshing signal unit and the output end of the switch unit, and the latch is used for receiving and storing the data bit transmitted by the switch unit when the switch unit is switched on;
and the switch unit is used for controlling the transmission of the data bit so as to control the storage of the latch, and is switched on when the latch inputs a refresh signal and is switched off after the data bit transmitted by the switch unit is input.
In one embodiment, the switching unit includes a first transistor; the output end of the first transistor is connected with the input end of the latch, the control end of the first transistor is connected with the output end of the latch, and the input end of the first transistor is connected with an external data source. .
In one embodiment, the first transistor includes one of an NMOS transistor and a PMOS transistor.
In one embodiment, the refresh signal unit includes a second transistor, an output terminal of the second transistor is connected to the input terminal of the latch, a control terminal of the second transistor is connected to an external set signal, and an input terminal of the second transistor is grounded or connected to a high level.
In one embodiment, the pixel circuit further comprises a first inverter; the input end and the output end of the first phase inverter are respectively and correspondingly connected with the output end of the latch and the control end of the switch unit; the first inverter is used for inverting the high potential at the output end of the latch so as to turn off the switch unit.
In one embodiment, the latch comprises a second inverter and a third inverter; the second inverter is connected in parallel with the third inverter and in opposite directions.
In one embodiment, the switching unit further comprises a diode; the output end of the diode is connected with the input end of the latch, and the diode is used for cutting off after the latch stores data.
In one embodiment, the pixel circuit further includes:
and the input unit is connected with the input end of the switch unit and is used for inputting a level signal carrying data to the switch unit.
In one embodiment, the output end of the input unit is further connected to the control end of the switch unit, and is used for feeding back the potential of the input unit to the switch unit after the switch unit is turned on, so as to turn off the switch unit.
A display device comprises the liquid crystal on silicon pixel circuit.
In the liquid crystal on silicon pixel circuit, the latch is set or reset through the refreshing signal unit so as to enable the switch unit to be conducted, and the refreshing signal unit is disconnected after the switch unit is conducted; and then, during the on period of the switch unit, the latch stores the data transmitted by the switch unit, the potentials at two ends of the latch are changed, so that the switch unit is disconnected, and when level data is input to the switch unit, the switch unit cannot be switched on, so that error data cannot be written into the pixel circuit during the modulation period.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that drawings of other embodiments can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of an LCOS pixel circuit according to an embodiment;
FIG. 2 is a block diagram illustrating an example of an LCOS pixel circuit of the embodiment of FIG. 1;
FIG. 3 is a circuit diagram of one embodiment of an LCOS pixel circuit of the embodiment shown in FIG. 2;
FIG. 4 is a block diagram illustrating an example of an LCOS pixel circuit of the embodiment of FIG. 1;
FIG. 5 is a circuit diagram of one embodiment of the LCOS pixel circuit of the embodiment shown in FIG. 4;
FIG. 6 is a circuit diagram of one embodiment of an LCOS pixel circuit of the embodiment shown in FIG. 4;
FIG. 7 is a circuit diagram of one embodiment of a liquid crystal on silicon pixel circuit of the embodiment shown in FIG. 1;
FIG. 8 is a circuit diagram of one embodiment of an LCOS pixel circuit of the embodiment of FIG. 1;
FIG. 9 is a block diagram of an embodiment of a LCOS pixel circuit of the embodiment of FIG. 1;
FIG. 10 is a circuit diagram of one embodiment of a liquid crystal on silicon pixel circuit of the embodiment shown in FIG. 1;
FIG. 11 is a circuit diagram of one embodiment of a LCOS pixel circuit of the embodiment shown in FIG. 1.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, one embodiment provides a liquid crystal on silicon pixel circuit that prevents erroneous data from being written under certain conditions. The LCOS pixel circuit includes a refresh signal unit 110, a latch 120, and a switch unit 130.
The refresh signal unit 110 is connected to the input terminal a of the latch 120, and is configured to input a refresh signal to the latch 120 according to a set timing. Specifically, the refresh signal unit 110 sets the latch 120 to a high level or a low level in a periodic manner, and turns off after the setting is successful. For example, the control terminal of the refresh signal unit 110 is connected to the set signal, and the input terminal of the refresh signal unit 110 is connected to the high level V DD The output terminal of the refresh signal unit 110 is connected to the input terminal of the latch 120, and when a new period occurs, the refresh signal unit 110 outputs a high level, so as to set the input terminal a of the latch 120 at a high level. The refresh signal unit 110 includes a second transistor M3.
And an input end a of the latch 120 is respectively connected to the output end of the refresh signal unit 110 and the output end of the switch unit 130, and is used for receiving and storing the data transmitted by the switch unit 130 when the switch unit 130 is turned on. Specifically, the input terminals a of the latch 120 are respectively connected to the output terminal of the switching unit 130 and the output terminal of the refresh signal unit 110. Wherein the latch 120 includes a second inverter and a third inverter. The second inverter is connected with the third inverter in parallel and in opposite directions. Latch 120 may store the input data and keep the potentials of input a and output b of latch 120 opposite. The latch 120 receives the potential output by the refresh signal unit 110, and sets a potential at the input terminal of the latch 120, and after the potential passes through the latch 120, the output terminal b of the latch 120 also sets a potential opposite to the input terminal a of the latch 120, so that the potential is temporarily stored in the latch 120, and then when the switch unit 130 is turned on, the potentials of the input terminal a and the output terminal b of the latch 120 are changed, so that the originally turned-on switch unit 130 is turned off, and in this period, the switch unit 130 cannot be turned on any more, so that writing of subsequent error data is prevented.
The switching unit 130 is used for controlling the transmission of the data bit, further controlling the storage of the latch 120, and is turned on when the refresh signal is input to the latch 120 and turned off after the data bit transmitted by the switching unit 130 is input. Specifically, the input terminal of the switching unit 130 is connected to an external data source, the output terminal of the switching unit 130 is connected to the input terminal a of the latch 120, and when the switching unit 130 is turned on, the potentials at the two terminals of the latch 120 are changed, and at the same time, the switching unit 130 is turned off from on. The switching unit 130 includes electronic components having an on or off function, such as a diode and a transistor. In one embodiment, the switching unit 130 includes a first transistor M2. In another embodiment, the transistor includes one of an NMOS transistor and a PMOS transistor.
In summary, in the liquid crystal on silicon pixel circuit provided in the foregoing embodiment, the refresh signal unit 110 sets or resets the latch 120, so that the two ends of the latch 120 are temporarily stored with an opposite potential and then disconnected, after the switch unit 130 is turned on, the latch 120 stores the data transmitted by the switch unit 130, and at the same time, the potentials at the two ends of the latch 120 are changed, so that the switch unit 130 is disconnected, and in this period, when level data is input to the switch unit 130, the switch unit 130 cannot be turned on, so that no error data is written into the pixel circuit during the modulation period.
In one embodiment, referring to fig. 2, the pixel circuit further includes a first inverter 140. The input end and the output end of the first inverter 140 are respectively connected to the output end b of the latch 120 and the control end c of the switching unit 130. The first inverter 140 is used to invert the high potential of the output terminal b of the latch 120 to turn off the switching unit 130. Specifically, referring to fig. 3, when the refresh signal unit 110 is set at the input end a of the latch 120 and has a high potential, the output end b of the latch 120 is at a low potential, the input end of the switch unit 130 receives a low level input by an external data source, and the first inverter 140 inverts the low potential of the output end b of the latch 120, so that the control end c of the switch unit 130 obtains a high potential to be turned on, and at the same time, the potential of the input end a of the latch 120 is changed from the high potential to the low potential and the potential of the output end b is changed from the low potential to the high potential, at this time, the first inverter 140 inverts the high potential of the output end b of the latch 120 and outputs the inverted high potential to the control end of the switch unit 130, so that the control end c of the switch unit 130 is turned off from the original high potential to the low potential. Then, the external data source cannot turn on the switching unit 130 during the period even if a high level is input at the input terminal of the switching unit 130, thereby preventing erroneous data from being written into the pixel circuit. In addition, the first inverter mainly has a function of inverting the potential of the output terminal b of the latch 120 and outputting the inverted potential to the control terminal c of the switch unit 130 to control the switch unit 130 to be turned on or off, and in other embodiments, the output terminal b of the latch 120 and the control terminal c of the switch unit 130 are connected through a not gate to realize the inversion of the potential to control the switch unit 130 to be turned off.
In another embodiment, referring to fig. 4, the pixel circuit further includes a first inverter 140. An input terminal and an output terminal of the first inverter 140 are respectively connected to the input terminal a of the latch 120 and the control terminal c of the switching unit 130. The first inverter 140 is used to invert the high potential of the input terminal a of the latch 120, so that the switching unit 130 is turned off. Specifically, referring to fig. 5, when the refresh signal unit 110 is set at the input end a of the latch 120 with a low voltage level, the output end b of the latch 120 is at a high voltage level, the input end of the switch unit 130 receives the high voltage level input by the external data source, and the first inverter 140 inverts the low voltage level at the input end a of the latch 120, so that the control end c of the switch unit 130 is turned on by a high voltage level, and at the same time, the voltage level at the input end a of the latch 120 is changed from the low voltage level to the high voltage level, and the voltage level at the output end b is changed from the high voltage level to the low voltage level, at this time, the first inverter 140 inverts the high voltage level at the input end s of the latch 120 and outputs the inverted voltage level to the control end c of the switch unit 130, so that the control end c of the switch unit 130 is turned off by the original high voltage level to the low voltage level. Then, the external data source cannot turn on the switching unit 130 during the period even if a low level is input at the input terminal of the switching unit 130, thereby preventing erroneous data from being written into the pixel circuit. In addition, the inverter herein mainly has a function of inverting the potential of the input terminal a of the latch 120 and outputting the inverted potential to the control terminal c of the switch unit 130 to control the switch unit 130 to be turned on or off, and in other embodiments, the input terminal a of the latch 120 and the control terminal c of the switch unit 130 are connected through a not gate to realize the inversion of the potential to control the switch unit 130 to be turned off.
In other embodiments, referring to fig. 6, the voltage level of the input terminal a of the latch 120 may also be directly fed back to the control terminal c of the switch unit 130. For example, when the refresh signal unit 110 is placed at the input terminal a of the latch 120 with a high voltage, the output terminal b of the latch 120 is at a low voltage, and the refresh signal unit is turned off; the input end of the switch unit 130 receives a low level input from the outside, and since the input end of the latch 120 is connected to the control end of the switch unit 130, the control end of the switch unit 130 obtains a high potential to be turned on, and meanwhile, the potential of the input end a of the latch 120 is changed from the high potential to the low potential, and the potential of the output end b is changed from the low potential to the high potential, at this time, the control end c of the switch unit 130 is at the low potential, so that when the input end of the switch unit 130 inputs a high level, the external data source cannot turn on the switch unit 130 in the period, and further, the writing of error data into the pixel circuit is prevented.
In one embodiment, the switching unit 130 further includes a diode D. The output of diode D is connected to the input of latch 120 and diode D is used to turn off after latch 120 stores data. Specifically, referring to fig. 7, the anode of the diode D is connected to the input unit of the external data source, and the cathode of the diode D is connected to the input end a of the latch 120. When the refresh signal unit 110 is placed at the input end a of the latch 120 and has a low potential, the output end b of the latch 120 is at a high potential, and when the anode of the diode D receives a high level input by an external data source, the diode D is turned on because the cathode of the diode D is at a low potential, and meanwhile, the potential of the input end a of the latch 120 is changed from the low potential to the high potential, and the potential of the output end b is changed from the high potential to the low potential. Then, at this time, the potential of the cathode of the diode D is high, and the diode D enters the off state, so that the diode D cannot be turned on in the period when the anode of the diode D inputs a low level, thereby preventing erroneous data from being written into the pixel circuit.
In another embodiment, referring to fig. 8, the anode of the diode D is connected to the input terminal a of the latch 120, and the cathode of the diode D is connected to an external input unit. When the refresh signal unit 110 is set at a high potential at the input end a of the latch 120, the output end b of the latch 120 is at a low potential, and when the cathode of the diode D receives a low level input from an external data source, the anode of the diode D is at the high potential, the diode D is turned on, and meanwhile, the potential at the input end a of the latch 120 is changed from the high potential to the low potential, and the potential at the output end is changed from the low potential to the high potential. At this time, the potential of the anode of the diode D is a low potential, and the diode D enters an off state, so that the diode D cannot be turned on in the period when the cathode of the diode D inputs a high level, thereby preventing erroneous data from being written into the pixel circuit.
In one embodiment, referring to fig. 9, the pixel circuit further includes an input unit 150 connected to the input terminal of the switch unit 130, and configured to input a level signal carrying data to the switch unit 130. Specifically, the input unit includes a third transistor M3, while the end of the word line WL is a control end of the third transistor M3, and the end of the bit line BL is an input end of the third transistor M3, and a level signal is input while ensuring that the third transistor M3 is turned on.
In one embodiment, the output terminal of the input unit 150 is further connected to the control terminal c of the switching unit 130, and is used for feeding back the potential of the input unit 150 to the switching unit 130 after the switching unit 130 is turned on, so as to turn off the switching unit 130. Specifically, referring to fig. 10, when the refresh signal unit 110 is placed at the input end a of the latch 120 with a low voltage, the output end b of the latch 120 is at a high voltage, and the refresh signal unit 110 is turned off; the input end of the switch unit 130 receives a high level input from the outside, because the output end of the input unit 150 is connected to the control end of the switch unit 130, the control end of the switch unit 130 obtains a high potential to be conducted, and simultaneously the potential of the input end a of the latch 120 is converted from a low potential to a high potential, and the potential of the output end b is converted from a high potential to a low potential, at this time, the output end of the switch unit 130 is a high potential, so that when an external data source inputs a low level at the input end of the switch unit 130, the control end c of the switch unit 130 obtains a low potential, and thus the switch unit 130 cannot be conducted in the period, and further, error data is prevented from being written into the pixel circuit. In another embodiment, referring to fig. 11, the output terminal of the input unit 150 is connected to the control terminal c of the switch unit 130 and the connection relationship is not-gate, that is, the phase of the output terminal of the input unit 150 is opposite to the phase of the control terminal c of the switch unit 130. For example, when the refresh signal unit 110 is set at the input end a of the latch 120 and has a high voltage level, the output end b of the latch 120 is set at a low voltage level, and the refresh signal unit 110 is turned off; the input end of the switch unit 130 receives a low level input by an external data source, and since the output end of the input unit 150 is connected to the control end c of the switch unit 130, the control end c of the switch unit 130 obtains a high level to be turned on, and meanwhile, the potential of the input end a of the latch 120 is changed from the high level to the low level, and the potential of the output end b is changed from the low level to the high level, at this time, the output end of the switch unit 130 is at the low level, so that when the input end of the switch unit 130 inputs a high level, the control end c of the switch unit 130 obtains a low level, and thus the switch unit 130 cannot be turned on in the period, and further, error data is prevented from being written into the pixel circuit.
An embodiment also provides a display device. The display device comprises the liquid crystal on silicon pixel circuit of any one of the embodiments.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A liquid crystal on silicon pixel circuit, the pixel circuit comprising: the device comprises a refreshing signal unit, a latch and a switch unit;
the refreshing signal unit is connected with the input end of the latch and is used for inputting refreshing signals to the latch according to a set time sequence;
the input end of the latch is respectively connected with the output end of the refreshing signal unit and the output end of the switch unit, and the latch is used for receiving and storing the data bit transmitted by the switch unit when the switch unit is switched on;
the switch unit is used for controlling the transmission of the data bit so as to control the storage of the latch, and is switched on when the latch inputs a refresh signal and is switched off after the data bit transmitted by the switch unit is input;
the latch is also used for turning off the switch unit by using the potential transition of the input end and the output end when the switch unit is turned on.
2. The LCOS pixel circuit according to claim 1, wherein said switching unit comprises a first transistor; the output end of the first transistor is connected with the input end of the latch, the control end of the first transistor is connected with the output end of the latch, and the input end of the first transistor is connected with an external data source.
3. The LCOS pixel circuit of claim 2, wherein the first transistor comprises one of an NMOS transistor and a PMOS transistor.
4. The LCOS pixel circuit according to claim 1, wherein said refresh signal unit comprises a second transistor, an output terminal of said second transistor is connected to an input terminal of said latch, a control terminal of said second transistor is connected to an external set signal, and an input terminal of said second transistor is grounded or connected to a high level.
5. The LCOS pixel circuit according to claim 1, further comprising a first inverter; the input end and the output end of the first phase inverter are respectively and correspondingly connected with the output end of the latch and the control end of the switch unit; the first inverter is used for inverting the high potential at the output end of the latch so as to turn off the switch unit.
6. A liquid crystal on silicon pixel circuit as recited in claim 1, wherein the latch comprises a second inverter and a third inverter; the second inverter is connected in parallel with the third inverter and in opposite directions.
7. The LCOS pixel circuit of claim 1, wherein the switching unit further comprises a diode; the output end of the diode is connected with the input end of the latch, and the diode is used for cutting off after the latch stores data.
8. The LCOS pixel circuit of claim 1, further comprising:
and the input unit is connected with the input end of the switch unit and is used for inputting the level signal carrying the data to the switch unit.
9. The LCOS pixel circuit according to claim 8, wherein the output terminal of the input unit is further connected to the control terminal of the switch unit for feeding back the potential of the input unit to the switch unit to turn off the switch unit after the switch unit is turned on.
10. A display device comprising a liquid crystal on silicon pixel circuit according to any one of claims 1 to 9.
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