CN107766270B - Data reading management method and device for PCIe (peripheral component interface express) equipment - Google Patents

Data reading management method and device for PCIe (peripheral component interface express) equipment Download PDF

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CN107766270B
CN107766270B CN201710986687.4A CN201710986687A CN107766270B CN 107766270 B CN107766270 B CN 107766270B CN 201710986687 A CN201710986687 A CN 201710986687A CN 107766270 B CN107766270 B CN 107766270B
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read
response
tag
data
request
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CN107766270A (en
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王克非
张磊
李显微
王志奇
陈梨
詹晋川
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Shenzhen Netforward Microelectronic Co ltd
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Shenzhen Forward Industrial Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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Abstract

The embodiment of the invention provides a data reading management method and device for PCIe (peripheral component interface express) equipment, belonging to the technical field of I/O (input/output) equipment. The data reading management method for the PCIe device comprises the following steps: receiving a read request from a read request channel; calling a read request tag from a read request tag queue according to the read request, and storing the read request tag into a read response tag queue configured by a read response channel corresponding to the read request channel; sending a PCIe request message, wherein a read request label and a read request are encapsulated in the PCIe request message; receiving a PCIe response message, and analyzing response data and a read response tag contained in the PCIe response message; and when the read response tag corresponds to the read request tag, writing the response data into a read response channel corresponding to the matched read response tag queue. Therefore, strict order preservation of the multi-channel data reading of the PCIe device is guaranteed, and a new strategy is provided for multi-channel data reading management of the PCIe device.

Description

Data reading management method and device for PCIe (peripheral component interface express) equipment
Technical Field
The present invention relates to the field of I/O device technologies, and in particular, to a data read management method and apparatus for PCIe devices.
Background
PCI Express (PCIe) is currently the most widely used I/O bus standard, which can provide interconnection devices for point-to-point serial differential signal links and has the characteristics of high performance, high bandwidth, dual simplex, and the like. Thus, the early parallel PCI bus was replaced, thereby meeting the speed and bandwidth requirements of the rapidly evolving microprocessors and memories.
As shown in FIG. 1, a PCIe bus protocol architecture is shown that includes a core layer, a transaction layer, a physical layer, a data link layer, and a physical layer. In the Data reading process, a Data message is first generated in a core Layer (DeviceCore) of a transmitting device, and then passes through a Transaction Layer (Transaction Layer), a Data link Layer (Data link Layer) and a Physical Layer (Physical Layer) of the device, and finally is transmitted. And the data at the receiving end also needs to pass through the physical layer, the data link and the transaction layer and finally reach the core layer. More specifically, the Transaction Layer receives data from the PCIe device core Layer, encapsulates the data into a TLP (Transaction Layer Packet), and sends the TLP to the data link Layer; in addition, the transaction layer can also receive the data message from the data link layer and then forward the data message to the core layer of the PCIe device. The data link layer ensures that the message from the transaction layer of the sending end can be reliably and completely sent to the data link layer of the receiving end, the message from the transaction layer is added with a sequence number prefix and a CRC (cyclic redundancy check) suffix when passing through the data link layer, and the data link layer ensures the reliable transmission of the message by using an ACK/NAK protocol.
The PCIe bus adopts a message-based data transmission architecture on data reading, and separates and independently transmits the request message and the response message, thereby improving the utilization rate of bus bandwidth, but also increasing the complexity of PCIe equipment data processing. In a read transaction of a Direct Memory Access (DMA), PCIe encapsulates the read transaction into two messages, namely a Memory read request message and a read response message, because a request and a response are transmitted independently, a tag (label) is required to identify a corresponding relationship between the request and the response, the tag is a digital number, PCIe allows multiple Memory read request messages to be sent, all sent read request messages tag are not allowed to be repeated, a Host extracts a corresponding tag after receiving the read request, adds the tag to a read response message when returning DMA data, and PCIe device may reuse the tag of the read request after receiving all data of one read request.
The inventor of the application finds out that: host accesses may be out of order, so read responses are not returned in the order of read requests; however, the PCIe device needs to process the data sequentially, so the DMA controller is required to match and reorder the tag and the data. In one case, if the PCIe device has multiple DMA read request channels, the read requests between the multiple channels are interleaved, but the PCIe device requires the returned data to be in order for each channel, which is more complicated, and affects the data reading efficiency and success rate of the PCIe device.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a data reading management method and apparatus for PCIe device, so as to at least solve the technical problem in the prior art that data reading efficiency and success rate of the PCIe device are low because each pair of request and response channels are required to implement order preservation when the PCIe device reads data.
In order to achieve the above object, an embodiment of the present invention provides a data read management method for a PCIe device, where the PCIe device is configured with a plurality of read request channels, a plurality of read response channels in one-to-one correspondence with the read request channels, and a read request tag queue for storing a plurality of tags, and the plurality of read response channels are respectively configured with a plurality of read response tag queues correspondingly, the method includes: receiving a read request from a read request channel; calling a read request tag from the read request tag queue according to the read request, and storing the read request tag into a read response tag queue configured by a read response channel corresponding to the read request channel; sending a PCIe request message, wherein the PCIe request message is packaged with the read request label and the read request; receiving a PCIe response message, and analyzing response data and a read response tag contained in the PCIe response message; and when the read response tag corresponds to the read request tag, writing the response data into a read response channel corresponding to the matched read response tag queue.
Optionally, when the read response tag corresponds to the read request tag, writing the response data into the read response channel corresponding to the matched read response tag queue includes: when the read response tag corresponds to the read request tag, judging whether the data length of the response data is matched with the request data length required by the read request; and if the data length of the response data is matched with the request data length, writing the response data into a read response channel corresponding to the matched read response tag queue.
Optionally, if the data length of the response data matches the request data length, writing the response data into the read response channel corresponding to the matching read response tag queue includes: if the data length of the response data is matched with the request data length, judging whether the data size of the response data is smaller than the residual storage capacity of the read response channel; and when the data size of the response data is smaller than the residual storage capacity, writing the response data into a read response channel corresponding to the matched read response tag queue.
Optionally, after writing the response data into the read response channel corresponding to the matching read response tag queue, the method further includes: clearing the read response tag from the matching read response tag queue; and saving the read response tag back to the read request tag queue.
Optionally, before receiving a read request from a read request channel, the method further includes: counting the number of the read request tags saved in one or more of the read response channels; arbitrating the read request corresponding to the read request channel according to the counted number of the read request tags.
Another aspect of the embodiments of the present invention provides a data reading management apparatus for a PCIe device, where the PCIe device is configured with a plurality of read request channels, a plurality of read response channels corresponding to the read request channels one to one, and a read request tag queue for storing a plurality of tags, and the plurality of read response channels are respectively configured with a plurality of read response tag queues correspondingly, the apparatus includes: a channel read request receiving unit for receiving a read request from a read request channel; a tag configuration unit, configured to invoke a read request tag from the read request tag queue according to the read request, and store the read request tag in a read response tag queue configured by a read response channel corresponding to the read request channel; a request message sending unit, configured to send a PCIe request message, where the read request tag and the read request are encapsulated in the PCIe request message; the response message processing unit is used for receiving a PCIe response message and analyzing response data and a read response label contained in the PCIe response message; and the read management unit is used for writing the response data into a read response channel corresponding to the matched read response tag queue when the read response tag corresponds to the read request tag.
Optionally, the read management unit includes: the data length matching component is used for judging whether the data length of the response data is matched with the request data length required by the read request or not when the read response tag corresponds to the read request tag; and a length write data component for writing the response data into a read response channel corresponding to the matched read response tag queue if the data length of the response data matches the request data length.
Optionally, the reading management unit further includes: a data capacity matching component, configured to determine whether a data size of the response data is smaller than a remaining storage capacity of the read response channel if the data length of the response data matches the request data length; and a capacity write data component, configured to write the response data into the read response channel corresponding to the matching read response tag queue if the data size of the response data is smaller than the remaining storage capacity.
Optionally, the apparatus further comprises: a tag clearing unit for clearing the read response tag from the matching read response tag queue; and the tag write-back unit is used for saving the read response tag back to the read request tag queue.
Optionally, the apparatus further comprises: a tag counter for counting the number of the read request tags saved in one or more of the read response channels; a read request arbiter for arbitrating the read requests corresponding to a read request channel according to the counted number of the read request tags.
According to the technical scheme, by means of the read request tag queue in which the tags are stored and the read response tag queues correspondingly configured for the read response channels, the read request tag is called once when the PCIe request message is sent out once, and the read request tag is stored in the read response tag queue of the corresponding channel in a backup mode, so that when the disordered PCIe response message is received, the stored read request tag can be matched with the response tag in the PCIe response message, and the response data in the PCIe response message can be written into the corresponding response channel. A new strategy is provided for the multi-channel data reading management of the PCIe device, so that the strict order preservation of the multi-channel data reading of the PCIe device is guaranteed, and the data reading efficiency and success rate of the PCIe device are improved.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of the architecture of a PCIe bus protocol architecture;
FIG. 2 is a schematic diagram of the working principle of the data read management apparatus for PCIe devices according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating a principle of a data read management apparatus for a PCIe device according to an embodiment of the present invention applying a total tag counter and a private tag counter to perform data read;
FIG. 4 is a schematic flow chart of the operation performed by the DMA read request processing module of FIG. 3;
FIG. 5 is a schematic flow diagram of the operation performed by the DMA read response processing module of FIG. 3.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Referring to fig. 2, a schematic diagram of an operating principle of a data read management apparatus for a PCIe device according to an embodiment of the present invention is shown, where the PCIe device is configured with a plurality of read request channels and a plurality of read response channels corresponding to the read request channels one to one, for example, as shown in fig. 1, a DMA (Direct Memory Access) read request channel 1 and a corresponding DMA read response channel 1, a DMA read request channel 2 and a corresponding DMA read response channel 2, and the like. The general requirements in reading data are such that: the data written in different read response channels can only be the response data requested by the read request sent by the corresponding read request channel, and the disorder is not allowed to occur; for example, the data requested by the read request issued by the DMA read request channel 1 is written into the DMA read response channel 1, but not into other response channels such as the DMA read response channels 2 and 3.
In view of this, the data reading management apparatus 10 in the embodiment of the present invention has a DMA read request processing module 101 and a DMA read response processing module 102, where the DMA read request processing module 101 specifically includes a channel read request receiving unit 1011, a tag configuration unit 1012 and a request message sending unit 1013, and the DMA read response processing module 102 includes a read management unit 1021 and a response message processing unit 1021. More specifically, the channel read request receiving unit 1011 may be configured to receive read requests sent by each read request channel, and the request message sending unit 1013 is configured to calculate a PCIe message header according to the read request and information such as a read request tag (label), and encapsulate the PCIe message header into a PCIe message, and send the PCIe message to the PCIe interface, so that the PCIe interface may send the message according to a PCIe protocol specification; the response packet processing unit 1021 in the DMA read response processing module 102 may be configured to obtain a PCIe read response packet from the PCIe interface for buffering, and the read management unit 1022 may write response data in the response packet into a corresponding DMA read response channel; the data read management device 10 further includes a DMA read request tag queue and a DMA read response tag queue associated with the DMA read request processing module 101 and the DMA read response processing module 102, and the data read management device 10 shown in fig. 2 may maintain only one DMA read request tag queue and all PCIe read request tag fields are to be read from the queue; so if the queue is empty, indicating that the tag in the queue has been used up, the receive channel read request should be stopped. And as shown in fig. 2, each channel in the data reading management apparatus 10 is correspondingly provided with a DMA read response tag queue, and the DMA read response tag queue may store a DMA read request tag that has been sent by the corresponding channel but has not returned a response. More specifically, the management process regarding data reading may be: the channel read request receiving unit 1011 receives a read request from a read request channel, calls the read request tag from a DMA read request tag queue according to the read request by relying on the interaction between the tag configuration unit 1012 and the DMA read request tag queue and the DMA read response tag queue, and stores the read request tag into a read response tag queue configured by a read response channel corresponding to the read request channel, for example, if the read request is from channel 1, the called read request tag is backed up into the DMA read response tag queue corresponding to channel 1, and the request message sending unit 1013 may further encapsulate the read request tag and the read request into a PCIe request message and send the PCIe request message to a PCIe interface; then, the response message processing unit 1021 acquires a PCIe read response message from the PCIe interface, and parses response data and read response tags included in the PCIe response message from the PCIe response message, and then the read management unit 1022 matches the read response tag with each read request tag stored in the DMA read response tag queue, and when the read response tag corresponds to one of the read request tags, writes the response data into a read response channel corresponding to the matched read response tag queue; for example, when the DMA read request tag stored in the corresponding channel 1 corresponds to the received read response tag, the response data encapsulated with the read response tag may be written to the DMA read response channel 1. By the embodiment of the invention, the response data required by the DMA request from the DMA read request channel is written into the DMA read response channel corresponding to the DMA read request channel, and the strict order preservation of the read request channel and the read response channel in the data reading process of the multi-channel PCIe equipment is ensured.
More preferably, the read management unit 1022 further includes a data length matching component and a length writing data component (not shown), and the DMA read request processing module 101 further includes a request data length parsing unit (not shown); more specifically, the request data length parsing unit may parse the obtained read request to obtain a request length required by the read request, and cache the request length; when the DMA read response processing module 102 receives the PCIe read response packet, the data length matching component is configured to continue to use the cached request length to match the data length of the response data if the matching of the response tag in the PCIe read response packet is successful, and the length write data component is configured to write the response data into the read response channel corresponding to the response tag only when the matching result is passed. Therefore, strict order preservation of the read request channel and the read response channel in the data reading process of the multi-channel PCIe device is guaranteed, and accuracy and efficiency of data reading are guaranteed.
More preferably, a data capacity matching component and a capacity writing data component (not shown) are also contained in the read management unit 1022; more specifically, the data capacity matching component may determine whether the data size of the response data is smaller than the remaining storage capacity of the read response channel when the data length of the response data matches the request data length; and when the residual storage capacity of the read response channel is determined to be capable of accommodating the response data, the response data is written into the corresponding read response channel. Therefore, the situation that data is continuously written into the read response channel when the capacity of the channel is not enough is avoided, and the reliability of data reading is guaranteed.
More preferably, a tag clearing unit and a tag write-back unit (not shown) are further disposed in the DMA read response processing module 102, where the tag clearing unit may be configured to eliminate, from the DMA read response tag queue, a read response tag originally encapsulated in a PCIe response message with response data after the response data corresponding to the read request is written into the read response channel, and the tag write-back unit may be configured to write back the tag to be eliminated into the DMA read request tag queue. Therefore, the tag in the DMA read request tag queue can be recycled in the process of executing the message request and the message response.
As a further disclosure and optimization of the embodiment of the present invention, the management of the tags in the device 10 during the data reading process may be implemented by using a tag counter, for example, a total tag counter may be used to maintain the sum of the number of read requests tags in all read response channels, and a private tag counter may be configured for each read response channel and maintain the number of read requests tags inside the channel, where the number of tags maintained by each private tag counter should satisfy the following relationship:
Figure BDA0001440669910000091
where N is the sum of all tags in the device 110 and the number of private tags for channel i is Ki。
More specific maintenance methods for the total tag counter and the private tag counter may be: after each DMA read request is sent out, adding 1 to a private tag counter of a channel corresponding to the read request; and after the data corresponding to one read response tag is completely returned to the DMA read response channel, the private tag counter of the channel is decreased by 1, and the total tag counter is decreased by 1.
The following description will be made with reference to the schematic flowchart of the working principle of the data reading management apparatus shown in fig. 3, which applies the data reading of the total tag counter and the private tag counter:
step 201: initializing a total tag counter and a private tag counter of each DMA read channel to be 0;
step 202: if a DMA read request exists in a certain DMA channel and the tag quantity of the total counter or the private tag quantity of the channel is smaller than a specified value, sending an arbitration request to a DMA read request arbiter;
step 203: the DMA read request arbiter arbitrates a read request from a plurality of DMA read request channels in a polling or priority arbitration mode, and sends the arbitrated read request to the DMA read request processing module;
step 204: reading a tag corresponding to the channel from the DMA read request tag queue, constructing a PCIe read message by combining the DMA read request, sending the PCIe read message to a PCIe interface, and recording the data length required to be returned by the tag in an array L [ tag ];
step 205: writing the tag into a DMA read response tag queue of a corresponding channel, and updating private and total tag counters, for example, adding 1 to both;
step 206: the Host returns data to the PCIe interface out of order, the data returned by the Host is cached in the cache, and the cache can be accessed according to the tag index and performs tag matching according to the access;
step 207: when the data length returned by the tag is equal to L [ tag ], setting rsp _ done [ tag ] to 1;
step 208: if the DMA read response tag queue is not empty, and rsp _ done [ tag ] corresponding to the tag of the queue head is 1, and the read response queue of the corresponding channel has enough space to receive data, sending an arbitration request to a DMA read response arbiter;
step 209: the DMA read response arbiter arbitrates one of the DMA channels and returns the data to the channel;
step 210: corresponding rsp _ done [ tag ] clear 0, L [ tag ] clear 0, release the cache in the read response buffer, write the tag back to the DMA read request tag queue, update the private and total tag counters, e.g., both subtract 1.
Further, steps 202-210 may be performed in a loop to complete the data reading operation.
More specific details regarding the workflow illustrated in fig. 3 will be described below in conjunction with fig. 4 and 5. Referring to FIG. 4, a schematic flow diagram of the operation performed by the DMA read request processing module is shown, which includes a read request arbiter and a DMA read request state machine, and n read request queues rqt _ fifo [0] rqt _ fifo [ n-1], a DMA read request tag queue and n DMA read response tag queues configured to act in association therewith. In the initialization state, the DMA read tag queue is in a full state, and assuming that the depth thereof is N, tag numbers stored in the read tag queue (fifo) are 0 to N-1, N DMA read response tag queues are empty, the DMA read request length buffer is all empty, and the read request length buffer is set to be accessible with a tag index. The specific working process can be as follows: the DMA read request module has n read requests rqt queues at the entry for storing DMA read requests for each channel, n rqt _ fifo empty (empty) signals are sent to the arbiter, when the empty signal is not 0 and rqt _ has _ tag of the corresponding channel is also valid from the tag counter maintaining the number of tag of each channel, an arbitration request is sent to the arbiter, the arbiter selects one output rqt _ hit and i from all arbitration requests to the DMA read request state machine for processing when the PCIe interface signal ready signal (PCIe _ ready) is valid, wherein rqt _ hit indicates that the result of the current arbitration output is valid, and i is the arbitrated channel number. More specifically, the rqt _ has _ tag [0] -rqt _ has _ tag [ n-1] signals may be used to identify whether there are n channels with free tags and to determine whether to use them to send DMA requests, and accordingly there is one private tag counter (rqt _ private _ tag [ i ]) for each channel i, and a total tag counter (rqt _ total _ tag) is shared by all channels, and rqt _ has _ tag [ i ] is generated as follows:
rqt_has_tag[i]＝(rqt_private_tag[i]<rqt_private_tag_max[i])|(rqt_total_tag<N)
rqt _ private _ tag _ max [ i ] is the maximum value of the private tag of each channel, and can be configured as required, so that the fairness of work among different channels can be realized, all the channels can be fully utilized, and the work of the channels is not overloaded.
However, the following conditions are satisfied:
0<rqt_private_tag_max[i]<N
after receiving the result of the read request arbiter, the DMA read request state machine first reads out a DMA read request from the rqt queue of the corresponding channel i, and at the same time reads out a read request tag (rqt _ tag) from the read request tag queue, constructs a PCIe read request message using the information, sends out the message through the PCIe interface, writes rqt _ tag into the DMA read response tag queue corresponding to i, writes the length of the request data into the DMA read request length buffer, and updates the priority rqt _ priority and tag counter of the arbiter as follows:
rqt_priority＝rqt_priority+1；
rqt_private_tag[i]＝rqt_private_tag[i]+1；
rqt_total_tag＝rqt_total_tag+1；
this allows the processing of a DMA read request to be completed before the next request can be processed repeatedly in the manner described above.
After receiving the PCIe read request message, the Host reads data from the memory through the memory access interface and packages the data into a PCIe read response message, which is returned to the PCIe device.
Referring to fig. 5, which is a schematic diagram illustrating a principle flow of work performed by the DMA read response module, in order to reorder data, the DMA read response processing module first stores a PCIe read response packet in a PCIe read response buffer, where the read response buffer is a buffer area formed by N data blocks, the DMA read response processing module writes data into a corresponding data block with tag in the read response packet as an index, and marks an rsp _ done [ tag ] signal of the data block as valid after all read responses of one tag are returned.
When the read response tag queue of the channel is not empty, a read response tag (rsp _ tag) is output, if the rsp _ done [ tag ] signal corresponding to the rsp _ tag is valid, and the read response queue of the channel has enough space to receive data, a request is sent to a read response arbiter, the read response arbiter selects one channel j from all the requests, the data in the read response buffer is written into the read response queue rsp _ fifo [ j ] of the channel j, the corresponding read response buffer is released, the rsp _ done [ j ] signal is cleared to 0, the read response tag rsp _ tag is read from the DMA read response tag queue of the channel j and written into the read request tag queue, and the priority rsp _ priority and tag counter of the arbiter are updated:
rsp_priority＝rsp_priority+1；
rqt_private_tag[i]＝rqt_private_tag[i]-1；
rqt_total_tag＝rqt_total_tag-1；
this allows the processing of a DMA read request to be completed before the next request can be processed repeatedly in the manner described above.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In addition, any combination of various different implementation manners of the embodiments of the present invention is also possible, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the spirit of the embodiments of the present invention.

Claims (10)

1. A data reading management method for a PCIe device is characterized in that the PCIe device is configured with a plurality of read request channels, a plurality of read response channels corresponding to the read request channels one by one, and a read request tag queue for storing a plurality of tags, and the plurality of read response channels are respectively configured with a plurality of read response tag queues correspondingly, the method comprises the following steps:
receiving a read request from a read request channel;
calling a read request tag from the read request tag queue according to the read request, and storing the read request tag into a read response tag queue configured by a read response channel corresponding to the read request channel;
sending a PCIe request message, wherein the PCIe request message is packaged with the read request label and the read request;
receiving a PCIe response message, and analyzing response data and a read response tag contained in the PCIe response message; and
and when the read response tag corresponds to the read request tag, writing the response data into a read response channel corresponding to the matched read response tag queue.
2. The method of claim 1, wherein the writing the response data into the read response channel corresponding to the matching read response tag queue when the read response tag corresponds to the read request tag comprises:
when the read response tag corresponds to the read request tag, judging whether the data length of the response data is matched with the request data length required by the read request; and
and if the data length of the response data is matched with the request data length, writing the response data into a read response channel corresponding to the matched read response tag queue.
3. The method of claim 2, wherein the writing the response data into the read response channel corresponding to the matching read response tag queue if the data length of the response data matches the request data length comprises:
if the data length of the response data is matched with the request data length, judging whether the data size of the response data is smaller than the residual storage capacity of the read response channel; and
and when the data size of the response data is smaller than the residual storage capacity, writing the response data into a read response channel corresponding to the matched read response tag queue.
4. The method of claim 1, further comprising, after said writing said response data into said read response channel corresponding to said matching read response tag queue:
clearing the read response tag from the matching read response tag queue; and
and saving the read response tag back to the read request tag queue.
5. The method of claim 1, wherein prior to said receiving a read request from a read request channel, the method further comprises:
counting the number of the read request tags saved in one or more of the read response channels;
arbitrating the read request corresponding to the read request channel according to the counted number of the read request tags.
6. A data read management apparatus for a PCIe device, where the PCIe device is configured with a plurality of read request channels and a plurality of read response channels one-to-one corresponding to the plurality of read request channels, and a read request tag queue for storing a plurality of tags, and the plurality of read response channels are respectively configured with a plurality of read response tag queues correspondingly, the apparatus includes:
a channel read request receiving unit for receiving a read request from a read request channel;
a tag configuration unit, configured to invoke a read request tag from the read request tag queue according to the read request, and store the read request tag in a read response tag queue configured by a read response channel corresponding to the read request channel;
a request message sending unit, configured to send a PCIe request message, where the read request tag and the read request are encapsulated in the PCIe request message;
the response message processing unit is used for receiving a PCIe response message and analyzing response data and a read response label contained in the PCIe response message;
and the read management unit is used for writing the response data into a read response channel corresponding to the matched read response tag queue when the read response tag corresponds to the read request tag.
7. The apparatus of claim 6, wherein the read management unit comprises:
the data length matching component is used for judging whether the data length of the response data is matched with the request data length required by the read request or not when the read response tag corresponds to the read request tag; and
and the length write data component is used for writing the response data into the read response channel corresponding to the matched read response tag queue if the data length of the response data is matched with the request data length.
8. The apparatus of claim 7, wherein the read management unit further comprises:
a data capacity matching component, configured to determine whether a data size of the response data is smaller than a remaining storage capacity of the read response channel if the data length of the response data matches the request data length; and
and the capacity write data component is used for writing the response data into the read response channel corresponding to the matched read response tag queue when the data size of the response data is smaller than the residual storage capacity.
9. The apparatus of claim 6, further comprising:
a tag clearing unit for clearing the read response tag from the matching read response tag queue;
and the tag write-back unit is used for saving the read response tag back to the read request tag queue.
10. The apparatus of claim 6, further comprising:
a tag counter for counting the number of the read request tags saved in one or more of the read response channels;
a read request arbiter for arbitrating the read requests corresponding to a read request channel according to the counted number of the read request tags.
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